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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Moved sig_reader to lpp.lpp_sim_pkg.
Jeandet Alexis -
r643:a691a9e23336 default draft
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY std;
6 USE std.textio.ALL;
7
8 LIBRARY lpp;
9 USE lpp.data_type_pkg.ALL;
10
11 ENTITY sig_reader IS
12 GENERIC(
13 FNAME : STRING := "input.txt";
14 WIDTH : INTEGER := 1;
15 RESOLUTION : INTEGER := 8;
16 GAIN : REAL := 1.0
17 );
18 PORT(
19 clk : IN std_logic;
20 end_of_simu : out std_logic;
21 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
22 );
23 END sig_reader;
24
25 ARCHITECTURE beh OF sig_reader IS
26 FILE input_file : TEXT OPEN read_mode IS FNAME;
27 SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
28 SIGNAL end_of_simu_reg : std_logic:='0';
29 BEGIN
30 out_signal <= out_signal_reg;
31 end_of_simu <= end_of_simu_reg;
32 PROCESS
33 VARIABLE line_var : LINE;
34 VARIABLE value : INTEGER;
35 VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
36 BEGIN
37 WAIT UNTIL clk = '1';
38 IF endfile(input_file) THEN
39 end_of_simu_reg <= '1';
40 ELSE
41 end_of_simu_reg <= '0';
42 readline(input_file,line_var);
43 FOR COL IN 0 TO WIDTH-1 LOOP
44 read(line_var, value);
45 cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
46 FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
47 out_signal_reg(COL,bit_idx) <= cell(bit_idx);
48 END LOOP;
49 END LOOP;
50 END IF;
51 END PROCESS;
52
53 END beh;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=testbench
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
16 VHDLSIMFILES= tb.vhd sig_reader.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = axcelerator
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
29 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./dsp/lpp_fft_rtax \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
37 ./lfr_management \
38 ./lpp_sim \
39 ./lpp_sim/CY7C1061DV33 \
40 ./lpp_cna \
41 ./lpp_uart \
42 ./lpp_usb \
43 ./dsp/lpp_fft \
44 ./lpp_leon3_soc \
45 ./lpp_debug_lfr
46
47 FILESKIP = i2cmst.vhd \
48 APB_MULTI_DIODE.vhd \
49 APB_MULTI_DIODE.vhd \
50 Top_MatrixSpec.vhd \
51 APB_FFT.vhd \
52 lpp_lfr_ms_FFT.vhd \
53 lpp_lfr_apbreg.vhd \
54 CoreFFT.vhd \
55 lpp_lfr_ms.vhd
56
57 include $(GRLIB)/bin/Makefile
58 include $(GRLIB)/software/leon3/Makefile
59
60 ################## project specific targets ##########################
61
1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=testbench
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = axcelerator
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
29 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./dsp/lpp_fft_rtax \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
37 ./lfr_management \
38 ./lpp_sim/CY7C1061DV33 \
39 ./lpp_cna \
40 ./lpp_uart \
41 ./lpp_usb \
42 ./dsp/lpp_fft \
43 ./lpp_leon3_soc \
44 ./lpp_debug_lfr
45
46 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
50 APB_FFT.vhd \
51 lpp_lfr_ms_FFT.vhd \
52 lpp_lfr_apbreg.vhd \
53 CoreFFT.vhd \
54 lpp_lfr_ms.vhd \
55 lpp_lfr_sim_pkg.vhd
56
57 include $(GRLIB)/bin/Makefile
58 include $(GRLIB)/software/leon3/Makefile
59
60 ################## project specific targets ##########################
61
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1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 USE ieee.numeric_std.ALL;
5 5 USE IEEE.std_logic_signed.ALL;
6 6 USE IEEE.MATH_real.ALL;
7 7
8 8 LIBRARY techmap;
9 9 USE techmap.gencomp.ALL;
10 10
11 11 LIBRARY std;
12 12 USE std.textio.ALL;
13 13
14 14 LIBRARY lpp;
15 15 USE lpp.iir_filter.ALL;
16 16 USE lpp.lpp_ad_conv.ALL;
17 17 USE lpp.FILTERcfg.ALL;
18 18 USE lpp.lpp_lfr_filter_coeff.ALL;
19 19 USE lpp.general_purpose.ALL;
20 20 USE lpp.data_type_pkg.ALL;
21 21 USE lpp.lpp_lfr_pkg.ALL;
22 22 USE lpp.general_purpose.ALL;
23 USE lpp.lpp_sim_pkg.ALL;
23 24
24 25 ENTITY testbench IS
25 26 GENERIC(
26 27 tech : INTEGER := 0; --axcel,0
27 28 Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
28 29 );
29 30 END;
30 31
31 32 ARCHITECTURE behav OF testbench IS
32 33 CONSTANT ChanelCount : INTEGER := 8;
33 34 CONSTANT Coef_SZ : INTEGER := 9;
34 35 CONSTANT CoefCntPerCel : INTEGER := 6;
35 36 CONSTANT CoefPerCel : INTEGER := 5;
36 37 CONSTANT Cels_count : INTEGER := 5;
37 38
38 39 SIGNAL sample : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
39 40 SIGNAL sample_val : STD_LOGIC;
40 41
41 42 SIGNAL sample_fx : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
42 43 SIGNAL sample_fx_val : STD_LOGIC;
43 44
44 45
45 46
46 47
47 48
48 49
49 50 SIGNAL TSTAMP : INTEGER := 0;
50 51 SIGNAL clk : STD_LOGIC := '0';
51 52 SIGNAL clk_24k : STD_LOGIC := '0';
52 53 SIGNAL clk_24k_r : STD_LOGIC := '0';
53 54 SIGNAL rstn : STD_LOGIC;
54 55
55 56 SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
56 57
57 58 --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
58 59
59 60 SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
60 61
61 62
62 63 COMPONENT generator IS
63 64 GENERIC (
64 65 AMPLITUDE : INTEGER := 100;
65 66 NB_BITS : INTEGER := 16);
66 67
67 68 PORT (
68 69 clk : IN STD_LOGIC;
69 70 rstn : IN STD_LOGIC;
70 71 run : IN STD_LOGIC;
71 72
72 73 data_ack : IN STD_LOGIC;
73 74 offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
74 75 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
75 76 );
76 77 END COMPONENT;
77
78 COMPONENT sig_reader IS
79 GENERIC(
80 FNAME : STRING := "input.txt";
81 WIDTH : INTEGER := 1;
82 RESOLUTION : INTEGER := 8;
83 GAIN : REAL := 1.0
84 );
85 PORT(
86 clk : IN std_logic;
87 end_of_simu : out std_logic;
88 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
89 );
90 END COMPONENT;
78
79 -- COMPONENT sig_reader IS
80 -- GENERIC(
81 -- FNAME : STRING := "input.txt";
82 -- WIDTH : INTEGER := 1;
83 -- RESOLUTION : INTEGER := 8;
84 -- GAIN : REAL := 1.0
85 -- );
86 -- PORT(
87 -- clk : IN std_logic;
88 -- end_of_simu : out std_logic;
89 -- out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
90 -- );
91 -- END COMPONENT;
91 92
92 93
93 94 FILE input : TEXT OPEN read_mode IS "input.txt";
94 95 FILE output_fx : TEXT OPEN write_mode IS "output_fx.txt";
95 96
96 97 SIGNAL end_of_simu : STD_LOGIC := '0';
97 98
98 99 BEGIN
99 100
100 101 -----------------------------------------------------------------------------
101 102 -- CLOCK and RESET
102 103 -----------------------------------------------------------------------------
103 104 clk <= NOT clk AFTER 20 ns;
104 105 PROCESS
105 106 BEGIN -- PROCESS
106 107 WAIT UNTIL clk = '1';
107 108 rstn <= '0';
108 109 WAIT UNTIL clk = '1';
109 110 WAIT UNTIL clk = '1';
110 111 WAIT UNTIL clk = '1';
111 112 rstn <= '1';
112 113 WAIT UNTIL end_of_simu = '1';
113 WAIT UNTIL clk = '1';
114 WAIT UNTIL clk = '1';
114 115 REPORT "*** END simulation ***" SEVERITY failure;
115 116 WAIT;
116 117 END PROCESS;
117 118 -----------------------------------------------------------------------------
118 119
119 120
120 121 -----------------------------------------------------------------------------
121 122 -- COMMON TIMESTAMPS
122 123 -----------------------------------------------------------------------------
123 124
124 125 PROCESS(clk)
125 126 BEGIN
126 127 IF clk'EVENT AND clk = '1' THEN
127 128 TSTAMP <= TSTAMP+1;
128 129 END IF;
129 130 END PROCESS;
130 131 -----------------------------------------------------------------------------
131 132
132 133
133 134 -----------------------------------------------------------------------------
134 135 -- LPP_LFR_FILTER f0
135 136 -----------------------------------------------------------------------------
136 137
137 138 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
138 139 GENERIC MAP (
139 140 tech => tech,
140 141 Mem_use => use_RAM,
141 142 Sample_SZ => 18,
142 143 Coef_SZ => Coef_SZ,
143 144 Coef_Nb => 25,
144 145 Coef_sel_SZ => 5,
145 146 Cels_count => Cels_count,
146 147 ChanelsCount => ChanelCount,
147 148 FILENAME => "")
148 149 PORT MAP (
149 150 rstn => rstn,
150 151 clk => clk,
151 152 virg_pos => 7,
152 153 coefs => CoefsInitValCst_v2,
153 154
154 155 sample_in_val => sample_val,
155 156 sample_in => sample,
156 157 sample_out_val => sample_fx_val,
157 158 sample_out => sample_fx);
158 159 -----------------------------------------------------------------------------
159 160
160 161
161 162 -----------------------------------------------------------------------------
162 163 -- SAMPLE GENERATION
163 164 -----------------------------------------------------------------------------
164 165 clk_24k <= NOT clk_24k AFTER 20345 ns;
165 166
166 167 PROCESS (clk, rstn)
167 168 BEGIN -- PROCESS
168 169 IF rstn = '0' THEN -- asynchronous reset (active low)
169 170 sample_val <= '0';
170 171 clk_24k_r <= '0';
171 172 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
172 173 clk_24k_r <= clk_24k;
173 174 IF clk_24k = '1' AND clk_24k_r = '0' THEN
174 175 sample_val <= '1';
175 176 ELSE
176 177 sample_val <= '0';
177 178 END IF;
178 179 END IF;
179 180 END PROCESS;
180 181 -----------------------------------------------------------------------------
181 182
182 183 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
183 184 SampleLoop : FOR j IN 0 TO 15 GENERATE
184 185 sample_fx_wdata(i)(j) <= sample_fx(i,j);
185 186 sample(i,j) <= signal_gen(i,j);
186 187 END GENERATE;
187 188 sample(i,16) <= signal_gen(i,16);
188 189 sample(i,17) <= signal_gen(i,17);
189 190 END GENERATE;
190 191
191
192
192
193
193 194 -----------------------------------------------------------------------------
194 195 -- READ INPUT SIGNALS
195 196 -----------------------------------------------------------------------------
196 197
197 198 gen: sig_reader
198 199 GENERIC MAP(
199 200 FNAME => "input.txt",
200 201 WIDTH => ChanelCount,
201 202 RESOLUTION => 18,
202 203 GAIN => 1.0
203 204 )
204 205 PORT MAP(
205 206 clk => sample_val,
206 207 end_of_simu => end_of_simu,
207 208 out_signal => signal_gen
208 209 );
209
210
210
211
211 212 -----------------------------------------------------------------------------
212 213 -- RECORD OUTPUT SIGNALS
213 214 -----------------------------------------------------------------------------
214 215
215 216 PROCESS(sample_fx_val,end_of_simu)
216 217 VARIABLE line_var : LINE;
217 218 BEGIN
218 219 IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
219 220 write(line_var, INTEGER'IMAGE(TSTAMP));
220 221 FOR I IN 0 TO 5 LOOP
221 222 write(line_var, " " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
222 223 END LOOP;
223 224 writeline(output_fx, line_var);
224 225 END IF;
225 226 IF end_of_simu = '1' THEN
226 227 file_close(output_fx);
227 228 END IF;
228 229 END PROCESS;
229 230
230 231
231 232
232 233
233 234 END;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.libdcom.ALL;
30 30 USE gaisler.sim.ALL;
31 31 USE gaisler.jtagtst.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34
35 LIBRARY lpp;
36 USE lpp.data_type_pkg.ALL;
37
35 38 PACKAGE lpp_sim_pkg IS
36 39
37 40 PROCEDURE UART_INIT (
38 41 SIGNAL TX : OUT STD_LOGIC;
39 42 CONSTANT tx_period : IN TIME
40 43 );
41 44 PROCEDURE UART_WRITE_ADDR32 (
42 45 SIGNAL TX : OUT STD_LOGIC;
43 46 CONSTANT tx_period : IN TIME;
44 47 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
45 48 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
46 49 );
47 50 PROCEDURE UART_WRITE (
48 51 SIGNAL TX : OUT STD_LOGIC;
49 52 CONSTANT tx_period : IN TIME;
50 53 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
51 54 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
52 55 );
53 56 PROCEDURE UART_READ (
54 57 SIGNAL TX : OUT STD_LOGIC;
55 58 SIGNAL RX : IN STD_LOGIC;
56 59 CONSTANT tx_period : IN TIME;
57 60 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
58 61 DATA : OUT STD_LOGIC_VECTOR
59 62 );
60 63
61
64 COMPONENT sig_reader IS
65 GENERIC(
66 FNAME : STRING := "input.txt";
67 WIDTH : INTEGER := 1;
68 RESOLUTION : INTEGER := 8;
69 GAIN : REAL := 1.0
70 );
71 PORT(
72 clk : IN std_logic;
73 end_of_simu : out std_logic;
74 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
75 );
76 END COMPONENT;
62 77 END lpp_sim_pkg;
63 78
64 79 PACKAGE BODY lpp_sim_pkg IS
65 80
66 81 PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
67 82 BEGIN
68 83 txc(TX, 16#55#, tx_period);
69 84 END;
70 85
71 86 PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
72 87 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 88 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
74 89 BEGIN
75 90 txc(TX, 16#c0#, tx_period);
76 91 txa(TX,
77 92 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
78 93 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
79 94 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
80 95 to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
81 96 tx_period);
82 97 txa(TX,
83 98 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
84 99 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
85 100 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
86 101 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
87 102 tx_period);
88 103 END;
89 104
90 105 PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
91 106 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
92 107 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
93 108
94 109 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
95 110
96 111 BEGIN
97 112 txc(TX, 16#c0#, tx_period);
98 113 txa(TX,
99 114 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
100 115 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
101 116 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
102 117 to_integer(UNSIGNED(ADDR_last)),
103 118 tx_period);
104 119 txa(TX,
105 120 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
106 121 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
107 122 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
108 123 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
109 124 tx_period);
110 125 END;
111 126
112 127 PROCEDURE UART_READ (
113 128 SIGNAL TX : OUT STD_LOGIC;
114 129 SIGNAL RX : IN STD_LOGIC;
115 130 CONSTANT tx_period : IN TIME;
116 131 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
117 132 DATA : OUT STD_LOGIC_VECTOR )
118 133 IS
119 134 VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
120 135 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
121 136 BEGIN
122 137 txc(TX, 16#80#, tx_period);
123 138 txa(TX,
124 139 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
125 140 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
126 141 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
127 142 to_integer(UNSIGNED(ADDR_last)),
128 143 tx_period);
129 144 rxc(RX,V_DATA,tx_period);
130 145 DATA(31 DOWNTO 24) := V_DATA;
131 146 rxc(RX,V_DATA,tx_period);
132 147 DATA(23 DOWNTO 16) := V_DATA;
133 148 rxc(RX,V_DATA,tx_period);
134 149 DATA(15 DOWNTO 8) := V_DATA;
135 150 rxc(RX,V_DATA,tx_period);
136 151 DATA(7 DOWNTO 0) := V_DATA;
137 152 END;
138 153
139 154 END lpp_sim_pkg;
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@@ -1,3 +1,3
1 sig_reader.vhd
1 2 lpp_sim_pkg.vhd
2 3 lpp_lfr_sim_pkg.vhd
3
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