@@ -1,50 +1,50 | |||||
1 | #GRLIB=../.. |
|
1 | #GRLIB=../.. | |
2 | VHDLIB=../.. |
|
2 | VHDLIB=../.. | |
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=leon3mp |
|
5 | TOP=leon3mp | |
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 |
|
6 | BOARD=em-LeonLPP-A3PE3kL-v3-core1 | |
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc |
|
7 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf |
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf |
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |
11 | EFFORT=high |
|
11 | EFFORT=high | |
12 | XSTOPT= |
|
12 | XSTOPT= | |
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
15 | VHDLSYNFILES=config.vhd leon3mp.vhd |
|
15 | VHDLSYNFILES=config.vhd leon3mp.vhd | |
16 | VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd |
|
16 | VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd | |
17 | SIMTOP=testbench |
|
17 | SIMTOP=testbench | |
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc |
|
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc |
|
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc |
|
20 | PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc | |
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut |
|
21 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |
22 | CLEAN=soft-clean |
|
22 | CLEAN=soft-clean | |
23 |
|
23 | |||
24 | TECHLIBS = proasic3e |
|
24 | TECHLIBS = proasic3e | |
25 |
|
25 | |||
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
26 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |
27 | tmtc openchip hynix ihp gleichmann micron usbhc |
|
27 | tmtc openchip hynix ihp gleichmann micron usbhc | |
28 |
|
28 | |||
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
|
29 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
|
30 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |
31 | ./amba_lcd_16x2_ctrlr \ |
|
31 | ./amba_lcd_16x2_ctrlr \ | |
32 | ./general_purpose/lpp_AMR \ |
|
32 | ./general_purpose/lpp_AMR \ | |
33 | ./general_purpose/lpp_balise \ |
|
33 | ./general_purpose/lpp_balise \ | |
34 | ./general_purpose/lpp_delay \ |
|
34 | ./general_purpose/lpp_delay \ | |
35 | ./lpp_bootloader \ |
|
35 | ./lpp_bootloader \ | |
36 | ./lpp_cna \ |
|
36 | ./lpp_cna \ | |
37 | ./lpp_uart \ |
|
37 | ./lpp_uart \ | |
38 | ./lpp_usb \ |
|
38 | ./lpp_usb \ | |
39 |
|
39 | |||
40 | FILESKIP = i2cmst.vhd \ |
|
40 | FILESKIP = i2cmst.vhd \ | |
41 | APB_MULTI_DIODE.vhd \ |
|
41 | APB_MULTI_DIODE.vhd \ | |
42 | APB_MULTI_DIODE.vhd \ |
|
42 | APB_MULTI_DIODE.vhd \ | |
43 | Top_MatrixSpec.vhd \ |
|
43 | Top_MatrixSpec.vhd \ | |
44 | APB_FFT.vhd |
|
44 | APB_FFT.vhd | |
45 |
|
45 | |||
46 | include $(GRLIB)/bin/Makefile |
|
46 | include $(GRLIB)/bin/Makefile | |
47 | include $(GRLIB)/software/leon3/Makefile |
|
47 | include $(GRLIB)/software/leon3/Makefile | |
48 |
|
48 | |||
49 | ################## project specific targets ########################## |
|
49 | ################## project specific targets ########################## | |
50 |
|
50 |
@@ -1,21 +1,26 | |||||
1 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
|
1 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd | |
2 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
|
2 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd | |
3 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd |
|
3 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd | |
4 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd |
|
4 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd | |
5 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
|
5 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd | |
6 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
|
6 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |
7 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
|
7 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd | |
8 |
|
8 | |||
|
9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
10 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_test.vhd | |||
|
11 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd | |||
|
12 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |||
|
13 | ||||
9 | vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd |
|
14 | vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd | |
10 |
|
15 | |||
11 | vcom -quiet -93 -work lpp testbench_package.vhd |
|
16 | vcom -quiet -93 -work lpp testbench_package.vhd | |
12 |
|
17 | |||
13 | vcom -quiet -93 -work work tb_waveform.vhd |
|
18 | vcom -quiet -93 -work work tb_waveform.vhd | |
14 |
|
19 | |||
15 | vsim work.testbench |
|
20 | vsim work.testbench | |
16 |
|
21 | |||
17 | log -r * |
|
22 | log -r * | |
18 |
|
23 | |||
19 |
do |
|
24 | do wave_ms.do | |
20 |
|
25 | |||
21 | run -all |
|
26 | run -all |
@@ -1,445 +1,465 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- LEON3 Demonstration design test bench |
|
2 | -- LEON3 Demonstration design test bench | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | ------------------------------------------------------------------------------ |
|
4 | ------------------------------------------------------------------------------ | |
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
|
5 | -- This file is a part of the GRLIB VHDL IP LIBRARY | |
6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. |
|
6 | -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. | |
7 | -- |
|
7 | -- | |
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN |
|
8 | -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN | |
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED |
|
9 | -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED | |
10 | -- IN ADVANCE IN WRITING. |
|
10 | -- IN ADVANCE IN WRITING. | |
11 | ------------------------------------------------------------------------------ |
|
11 | ------------------------------------------------------------------------------ | |
12 |
|
12 | |||
13 | LIBRARY ieee; |
|
13 | LIBRARY ieee; | |
14 | USE ieee.std_logic_1164.ALL; |
|
14 | USE ieee.std_logic_1164.ALL; | |
15 |
|
15 | |||
16 | --LIBRARY std; |
|
16 | --LIBRARY std; | |
17 | --USE std.textio.ALL; |
|
17 | --USE std.textio.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | LIBRARY gaisler; |
|
22 | LIBRARY gaisler; | |
23 | USE gaisler.memctrl.ALL; |
|
23 | USE gaisler.memctrl.ALL; | |
24 | USE gaisler.leon3.ALL; |
|
24 | USE gaisler.leon3.ALL; | |
25 | USE gaisler.uart.ALL; |
|
25 | USE gaisler.uart.ALL; | |
26 | USE gaisler.misc.ALL; |
|
26 | USE gaisler.misc.ALL; | |
27 | USE gaisler.libdcom.ALL; |
|
27 | USE gaisler.libdcom.ALL; | |
28 | USE gaisler.sim.ALL; |
|
28 | USE gaisler.sim.ALL; | |
29 | USE gaisler.jtagtst.ALL; |
|
29 | USE gaisler.jtagtst.ALL; | |
30 | USE gaisler.misc.ALL; |
|
30 | USE gaisler.misc.ALL; | |
31 | LIBRARY techmap; |
|
31 | LIBRARY techmap; | |
32 | USE techmap.gencomp.ALL; |
|
32 | USE techmap.gencomp.ALL; | |
33 | LIBRARY esa; |
|
33 | LIBRARY esa; | |
34 | USE esa.memoryctrl.ALL; |
|
34 | USE esa.memoryctrl.ALL; | |
35 | --LIBRARY micron; |
|
35 | --LIBRARY micron; | |
36 | --USE micron.components.ALL; |
|
36 | --USE micron.components.ALL; | |
37 | LIBRARY lpp; |
|
37 | LIBRARY lpp; | |
38 | USE lpp.lpp_waveform_pkg.ALL; |
|
38 | USE lpp.lpp_waveform_pkg.ALL; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.testbench_package.ALL; |
|
41 | USE lpp.testbench_package.ALL; | |
42 | USE lpp.lpp_lfr_pkg.ALL; |
|
42 | USE lpp.lpp_lfr_pkg.ALL; | |
43 | USE lpp.iir_filter.ALL; |
|
43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
|
44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.CY7C1061DV33_pkg.ALL; |
|
45 | USE lpp.CY7C1061DV33_pkg.ALL; | |
46 |
|
46 | |||
47 |
ENTITY testbenc |
|
47 | ENTITY testbench IS | |
48 | END; |
|
48 | END; | |
49 |
|
49 | |||
50 | ARCHITECTURE behav OF testbench IS |
|
50 | ARCHITECTURE behav OF testbench IS | |
51 | -- REG ADDRESS |
|
51 | CONSTANT INDEX_LFR : INTEGER := 15; | |
52 |
CONSTANT |
|
52 | CONSTANT ADDR_LFR : INTEGER := 15; | |
53 | CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; |
|
53 | -- REG MS | |
|
54 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; | |||
|
55 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |||
|
56 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |||
|
57 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; | |||
|
58 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |||
|
59 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |||
|
60 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |||
|
61 | -- REG WAVEFORM | |||
54 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
|
62 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |
55 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
|
63 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |
56 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
|
64 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |
57 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; |
|
65 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; | |
58 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; |
|
66 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; | |
59 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; |
|
67 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; | |
60 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; |
|
68 | CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; | |
61 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; |
|
69 | CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; | |
62 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; |
|
70 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; | |
63 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; |
|
71 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; | |
64 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; |
|
72 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; | |
65 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; |
|
73 | CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; | |
66 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; |
|
74 | CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; | |
67 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; |
|
75 | CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; | |
68 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; |
|
76 | CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; | |
69 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; |
|
77 | CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; | |
70 | -- RAM ADDRESS |
|
78 | -- RAM ADDRESS | |
71 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; |
|
79 | CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; | |
72 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; |
|
80 | CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; | |
73 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; |
|
81 | CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; | |
74 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; |
|
82 | CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; | |
75 |
|
83 | |||
76 |
|
84 | |||
77 | -- Common signal |
|
85 | -- Common signal | |
78 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
|
86 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; | |
79 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
|
87 | SIGNAL clk25MHz : STD_LOGIC := '0'; | |
80 | SIGNAL rstn : STD_LOGIC := '0'; |
|
88 | SIGNAL rstn : STD_LOGIC := '0'; | |
81 |
|
89 | |||
82 | -- ADC interface |
|
90 | -- ADC interface | |
83 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT |
|
91 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT | |
84 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT |
|
92 | SIGNAL ADC_smpclk : STD_LOGIC; -- OUT | |
85 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN |
|
93 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN | |
86 |
|
94 | |||
87 | -- AD Converter RHF1401 |
|
95 | -- AD Converter RHF1401 | |
88 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
96 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
89 | SIGNAL sample_val : STD_LOGIC; |
|
97 | SIGNAL sample_val : STD_LOGIC; | |
90 |
|
98 | |||
91 | -- AHB/APB SIGNAL |
|
99 | -- AHB/APB SIGNAL | |
92 | SIGNAL apbi : apb_slv_in_type; |
|
100 | SIGNAL apbi : apb_slv_in_type; | |
93 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
101 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
94 | SIGNAL ahbsi : ahb_slv_in_type; |
|
102 | SIGNAL ahbsi : ahb_slv_in_type; | |
95 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
103 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
96 | SIGNAL ahbmi : ahb_mst_in_type; |
|
104 | SIGNAL ahbmi : ahb_mst_in_type; | |
97 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
105 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
98 |
|
106 | |||
99 | SIGNAL bias_fail_bw : STD_LOGIC; |
|
107 | SIGNAL bias_fail_bw : STD_LOGIC; | |
100 |
|
108 | |||
101 | ----------------------------------------------------------------------------- |
|
109 | ----------------------------------------------------------------------------- | |
102 | -- LPP_WAVEFORM |
|
110 | -- LPP_WAVEFORM | |
103 | ----------------------------------------------------------------------------- |
|
111 | ----------------------------------------------------------------------------- | |
104 | CONSTANT data_size : INTEGER := 96; |
|
112 | CONSTANT data_size : INTEGER := 96; | |
105 | CONSTANT nb_burst_available_size : INTEGER := 50; |
|
113 | CONSTANT nb_burst_available_size : INTEGER := 50; | |
106 | CONSTANT nb_snapshot_param_size : INTEGER := 2; |
|
114 | CONSTANT nb_snapshot_param_size : INTEGER := 2; | |
107 | CONSTANT delta_vector_size : INTEGER := 2; |
|
115 | CONSTANT delta_vector_size : INTEGER := 2; | |
108 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; |
|
116 | CONSTANT delta_vector_size_f0_2 : INTEGER := 2; | |
109 |
|
117 | |||
110 | SIGNAL reg_run : STD_LOGIC; |
|
118 | SIGNAL reg_run : STD_LOGIC; | |
111 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
119 | SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
112 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
120 | SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
113 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
121 | SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
114 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
122 | SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
115 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
123 | SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
116 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
124 | SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
117 | SIGNAL enable_f0 : STD_LOGIC; |
|
125 | SIGNAL enable_f0 : STD_LOGIC; | |
118 | SIGNAL enable_f1 : STD_LOGIC; |
|
126 | SIGNAL enable_f1 : STD_LOGIC; | |
119 | SIGNAL enable_f2 : STD_LOGIC; |
|
127 | SIGNAL enable_f2 : STD_LOGIC; | |
120 | SIGNAL enable_f3 : STD_LOGIC; |
|
128 | SIGNAL enable_f3 : STD_LOGIC; | |
121 | SIGNAL burst_f0 : STD_LOGIC; |
|
129 | SIGNAL burst_f0 : STD_LOGIC; | |
122 | SIGNAL burst_f1 : STD_LOGIC; |
|
130 | SIGNAL burst_f1 : STD_LOGIC; | |
123 | SIGNAL burst_f2 : STD_LOGIC; |
|
131 | SIGNAL burst_f2 : STD_LOGIC; | |
124 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
132 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
125 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
133 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
126 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
134 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
127 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
135 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
128 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
136 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
129 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
137 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
139 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
132 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
133 | SIGNAL data_f0_in_valid : STD_LOGIC; |
|
141 | SIGNAL data_f0_in_valid : STD_LOGIC; | |
134 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
142 | SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
135 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
136 | SIGNAL data_f1_in_valid : STD_LOGIC; |
|
144 | SIGNAL data_f1_in_valid : STD_LOGIC; | |
137 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
145 | SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
138 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
146 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
139 | SIGNAL data_f2_in_valid : STD_LOGIC; |
|
147 | SIGNAL data_f2_in_valid : STD_LOGIC; | |
140 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
148 | SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
141 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
149 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
142 | SIGNAL data_f3_in_valid : STD_LOGIC; |
|
150 | SIGNAL data_f3_in_valid : STD_LOGIC; | |
143 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
|
151 | SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
144 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
145 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
146 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
154 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
147 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
155 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
148 | SIGNAL data_f0_data_out_ack : STD_LOGIC; |
|
156 | SIGNAL data_f0_data_out_ack : STD_LOGIC; | |
149 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
157 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
150 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
158 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
159 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
152 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
160 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
153 | SIGNAL data_f1_data_out_ack : STD_LOGIC; |
|
161 | SIGNAL data_f1_data_out_ack : STD_LOGIC; | |
154 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
162 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
155 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
163 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
156 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
164 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
157 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
165 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
158 | SIGNAL data_f2_data_out_ack : STD_LOGIC; |
|
166 | SIGNAL data_f2_data_out_ack : STD_LOGIC; | |
159 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
160 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
161 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
169 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
162 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
170 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
163 | SIGNAL data_f3_data_out_ack : STD_LOGIC; |
|
171 | SIGNAL data_f3_data_out_ack : STD_LOGIC; | |
164 |
|
172 | |||
165 | --MEM CTRLR |
|
173 | --MEM CTRLR | |
166 | SIGNAL memi : memory_in_type; |
|
174 | SIGNAL memi : memory_in_type; | |
167 | SIGNAL memo : memory_out_type; |
|
175 | SIGNAL memo : memory_out_type; | |
168 | SIGNAL wpo : wprot_out_type; |
|
176 | SIGNAL wpo : wprot_out_type; | |
169 | SIGNAL sdo : sdram_out_type; |
|
177 | SIGNAL sdo : sdram_out_type; | |
170 |
|
178 | |||
171 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
179 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; | |
172 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
173 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
|
181 | SIGNAL nSRAM_BE0 : STD_LOGIC; | |
174 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
|
182 | SIGNAL nSRAM_BE1 : STD_LOGIC; | |
175 | SIGNAL nSRAM_BE2 : STD_LOGIC; |
|
183 | SIGNAL nSRAM_BE2 : STD_LOGIC; | |
176 | SIGNAL nSRAM_BE3 : STD_LOGIC; |
|
184 | SIGNAL nSRAM_BE3 : STD_LOGIC; | |
177 | SIGNAL nSRAM_WE : STD_LOGIC; |
|
185 | SIGNAL nSRAM_WE : STD_LOGIC; | |
178 | SIGNAL nSRAM_CE : STD_LOGIC; |
|
186 | SIGNAL nSRAM_CE : STD_LOGIC; | |
179 | SIGNAL nSRAM_OE : STD_LOGIC; |
|
187 | SIGNAL nSRAM_OE : STD_LOGIC; | |
180 |
|
188 | |||
181 | CONSTANT padtech : INTEGER := inferred; |
|
189 | CONSTANT padtech : INTEGER := inferred; | |
182 | SIGNAL not_ramsn_0 : STD_LOGIC; |
|
190 | SIGNAL not_ramsn_0 : STD_LOGIC; | |
183 |
|
191 | |||
184 |
|
192 | |||
185 | BEGIN |
|
193 | BEGIN | |
186 |
|
194 | |||
187 | ----------------------------------------------------------------------------- |
|
195 | ----------------------------------------------------------------------------- | |
188 |
|
196 | |||
189 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
197 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |
190 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz |
|
198 | clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz | |
191 |
|
199 | |||
192 | ----------------------------------------------------------------------------- |
|
200 | ----------------------------------------------------------------------------- | |
193 |
|
201 | |||
194 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
|
202 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE | |
195 | TestModule_RHF1401_1 : TestModule_RHF1401 |
|
203 | TestModule_RHF1401_1 : TestModule_RHF1401 | |
196 | GENERIC MAP ( |
|
204 | GENERIC MAP ( | |
197 | freq => 24*(I+1), |
|
205 | freq => 24*(I+1), | |
198 | amplitude => 8000/(I+1), |
|
206 | amplitude => 8000/(I+1), | |
199 | impulsion => 0) |
|
207 | impulsion => 0) | |
200 | PORT MAP ( |
|
208 | PORT MAP ( | |
201 | ADC_smpclk => ADC_smpclk, |
|
209 | ADC_smpclk => ADC_smpclk, | |
202 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
210 | ADC_OEB_bar => ADC_OEB_bar_CH(I), | |
203 | ADC_data => ADC_data); |
|
211 | ADC_data => ADC_data); | |
204 | END GENERATE MODULE_RHF1401; |
|
212 | END GENERATE MODULE_RHF1401; | |
205 |
|
213 | |||
206 | ----------------------------------------------------------------------------- |
|
214 | ----------------------------------------------------------------------------- | |
207 |
|
215 | |||
208 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
|
216 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 | |
209 | GENERIC MAP ( |
|
217 | GENERIC MAP ( | |
210 | ChanelCount => 8, |
|
218 | ChanelCount => 8, | |
211 | ncycle_cnv_high => 79, |
|
219 | ncycle_cnv_high => 79, | |
212 | ncycle_cnv => 500) |
|
220 | ncycle_cnv => 500) | |
213 | PORT MAP ( |
|
221 | PORT MAP ( | |
214 | cnv_clk => clk49_152MHz, |
|
222 | cnv_clk => clk49_152MHz, | |
215 | cnv_rstn => rstn, |
|
223 | cnv_rstn => rstn, | |
216 | cnv => ADC_smpclk, |
|
224 | cnv => ADC_smpclk, | |
217 | clk => clk25MHz, |
|
225 | clk => clk25MHz, | |
218 | rstn => rstn, |
|
226 | rstn => rstn, | |
219 | ADC_data => ADC_data, |
|
227 | ADC_data => ADC_data, | |
220 | ADC_nOE => ADC_OEB_bar_CH, |
|
228 | ADC_nOE => ADC_OEB_bar_CH, | |
221 | sample => sample, |
|
229 | sample => sample, | |
222 | sample_val => sample_val); |
|
230 | sample_val => sample_val); | |
223 |
|
231 | |||
224 | ----------------------------------------------------------------------------- |
|
232 | ----------------------------------------------------------------------------- | |
225 |
|
233 | |||
226 | lpp_lfr_1 : lpp_lfr |
|
234 | lpp_lfr_1 : lpp_lfr | |
227 | GENERIC MAP ( |
|
235 | GENERIC MAP ( | |
228 | Mem_use => use_CEL, -- use_RAM |
|
236 | Mem_use => use_CEL, -- use_RAM | |
229 | nb_data_by_buffer_size => 32, |
|
237 | nb_data_by_buffer_size => 32, | |
230 | nb_word_by_buffer_size => 30, |
|
238 | nb_word_by_buffer_size => 30, | |
231 | nb_snapshot_param_size => 32, |
|
239 | nb_snapshot_param_size => 32, | |
232 | delta_vector_size => 32, |
|
240 | delta_vector_size => 32, | |
233 | delta_vector_size_f0_2 => 32, |
|
241 | delta_vector_size_f0_2 => 32, | |
234 |
pindex => INDEX_ |
|
242 | pindex => INDEX_LFR, | |
235 |
paddr => ADDR_ |
|
243 | paddr => ADDR_LFR, | |
236 | pmask => 16#fff#, |
|
244 | pmask => 16#fff#, | |
237 | pirq_ms => 6, |
|
245 | pirq_ms => 6, | |
238 | pirq_wfp => 14, |
|
246 | pirq_wfp => 14, | |
239 | hindex => 0, |
|
247 | hindex => 0, | |
240 |
top_lfr_version => X"00000 |
|
248 | top_lfr_version => X"000001") | |
241 | PORT MAP ( |
|
249 | PORT MAP ( | |
242 | clk => clk25MHz, |
|
250 | clk => clk25MHz, | |
243 | rstn => rstn, |
|
251 | rstn => rstn, | |
244 | sample_B => sample(2 DOWNTO 0), |
|
252 | sample_B => sample(2 DOWNTO 0), | |
245 | sample_E => sample(7 DOWNTO 3), |
|
253 | sample_E => sample(7 DOWNTO 3), | |
246 | sample_val => sample_val, |
|
254 | sample_val => sample_val, | |
247 | apbi => apbi, |
|
255 | apbi => apbi, | |
248 | apbo => apbo(15), |
|
256 | apbo => apbo(15), | |
249 | ahbi => ahbmi, |
|
257 | ahbi => ahbmi, | |
250 | ahbo => ahbmo(0), |
|
258 | ahbo => ahbmo(0), | |
251 | coarse_time => coarse_time, |
|
259 | coarse_time => coarse_time, | |
252 | fine_time => fine_time, |
|
260 | fine_time => fine_time, | |
253 | data_shaping_BW => bias_fail_bw); |
|
261 | data_shaping_BW => bias_fail_bw); | |
254 |
|
262 | |||
255 | ----------------------------------------------------------------------------- |
|
263 | ----------------------------------------------------------------------------- | |
256 | --- AHB CONTROLLER ------------------------------------------------- |
|
264 | --- AHB CONTROLLER ------------------------------------------------- | |
257 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
265 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
258 | GENERIC MAP (defmast => 0, split => 0, |
|
266 | GENERIC MAP (defmast => 0, split => 0, | |
259 | rrobin => 1, ioaddr => 16#FFF#, |
|
267 | rrobin => 1, ioaddr => 16#FFF#, | |
260 | ioen => 0, nahbm => 1, nahbs => 1) |
|
268 | ioen => 0, nahbm => 1, nahbs => 1) | |
261 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
269 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
262 |
|
270 | |||
|
271 | ||||
|
272 | ||||
263 |
|
|
273 | --- AHB RAM ---------------------------------------------------------- | |
264 | --ahbram0 : ahbram |
|
274 | --ahbram0 : ahbram | |
265 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
275 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
266 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); |
|
276 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); | |
267 | --ahbram1 : ahbram |
|
277 | --ahbram1 : ahbram | |
268 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) |
|
278 | -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) | |
269 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); |
|
279 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); | |
270 | --ahbram2 : ahbram |
|
280 | --ahbram2 : ahbram | |
271 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) |
|
281 | -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) | |
272 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); |
|
282 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); | |
273 | --ahbram3 : ahbram |
|
283 | --ahbram3 : ahbram | |
274 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) |
|
284 | -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) | |
275 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); |
|
285 | -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); | |
276 |
|
286 | |||
277 | ----------------------------------------------------------------------------- |
|
287 | ----------------------------------------------------------------------------- | |
278 | ---------------------------------------------------------------------- |
|
288 | ---------------------------------------------------------------------- | |
279 | --- Memory controllers --------------------------------------------- |
|
289 | --- Memory controllers --------------------------------------------- | |
280 | ---------------------------------------------------------------------- |
|
290 | ---------------------------------------------------------------------- | |
281 | memctrlr : mctrl GENERIC MAP ( |
|
291 | --memctrlr : mctrl GENERIC MAP ( | |
282 |
|
|
292 | -- hindex => 0, | |
283 |
|
|
293 | -- pindex => 0, | |
284 | paddr => 0, |
|
294 | -- paddr => 0, | |
285 | srbanks => 1 |
|
295 | -- srbanks => 1 | |
286 | ) |
|
296 | -- ) | |
287 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
297 | -- PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
288 |
|
298 | |||
289 | memi.brdyn <= '1'; |
|
299 | --memi.brdyn <= '1'; | |
290 | memi.bexcn <= '1'; |
|
300 | --memi.bexcn <= '1'; | |
291 | memi.writen <= '1'; |
|
301 | --memi.writen <= '1'; | |
292 | memi.wrn <= "1111"; |
|
302 | --memi.wrn <= "1111"; | |
293 | memi.bwidth <= "10"; |
|
303 | --memi.bwidth <= "10"; | |
294 |
|
304 | |||
295 | bdr : FOR i IN 0 TO 3 GENERATE |
|
305 | --bdr : FOR i IN 0 TO 3 GENERATE | |
296 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
306 | -- data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
297 | PORT MAP ( |
|
307 | -- PORT MAP ( | |
298 | data(31-i*8 DOWNTO 24-i*8), |
|
308 | -- data(31-i*8 DOWNTO 24-i*8), | |
299 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
309 | -- memo.data(31-i*8 DOWNTO 24-i*8), | |
300 | memo.bdrive(i), |
|
310 | -- memo.bdrive(i), | |
301 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
311 | -- memi.data(31-i*8 DOWNTO 24-i*8)); | |
302 | END GENERATE; |
|
312 | --END GENERATE; | |
303 |
|
313 | |||
304 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
314 | --addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
305 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
315 | -- PORT MAP (address, memo.address(21 DOWNTO 2)); | |
306 |
|
316 | |||
307 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
317 | --not_ramsn_0 <= NOT(memo.ramsn(0)); | |
308 |
|
318 | |||
309 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
319 | --rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); | |
310 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
320 | --oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
311 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
321 | --nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
312 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
322 | --nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
313 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
323 | --nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
314 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
324 | --nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
315 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
325 | --nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
316 |
|
326 | |||
317 | async_1Mx16_0: CY7C1061DV33 |
|
327 | --async_1Mx16_0: CY7C1061DV33 | |
318 | GENERIC MAP ( |
|
328 | -- GENERIC MAP ( | |
319 | ADDR_BITS => 20, |
|
329 | -- ADDR_BITS => 20, | |
320 | DATA_BITS => 16, |
|
330 | -- DATA_BITS => 16, | |
321 | depth => 1048576, |
|
331 | -- depth => 1048576, | |
322 | TimingInfo => TRUE, |
|
332 | -- TimingInfo => TRUE, | |
323 | TimingChecks => '1') |
|
333 | -- TimingChecks => '1') | |
324 | PORT MAP ( |
|
334 | -- PORT MAP ( | |
325 | CE1_b => '0', |
|
335 | -- CE1_b => '0', | |
326 | CE2 => nSRAM_CE, |
|
336 | -- CE2 => nSRAM_CE, | |
327 |
|
|
337 | -- WE_b => nSRAM_WE, | |
328 |
|
|
338 | -- OE_b => nSRAM_OE, | |
329 | BHE_b => nSRAM_BE1, |
|
339 | -- BHE_b => nSRAM_BE1, | |
330 | BLE_b => nSRAM_BE0, |
|
340 | -- BLE_b => nSRAM_BE0, | |
331 | A => address, |
|
341 | -- A => address, | |
332 | DQ => data(15 DOWNTO 0)); |
|
342 | -- DQ => data(15 DOWNTO 0)); | |
333 |
|
343 | |||
334 | async_1Mx16_1: CY7C1061DV33 |
|
344 | --async_1Mx16_1: CY7C1061DV33 | |
335 | GENERIC MAP ( |
|
345 | -- GENERIC MAP ( | |
336 | ADDR_BITS => 20, |
|
346 | -- ADDR_BITS => 20, | |
337 | DATA_BITS => 16, |
|
347 | -- DATA_BITS => 16, | |
338 | depth => 1048576, |
|
348 | -- depth => 1048576, | |
339 | TimingInfo => TRUE, |
|
349 | -- TimingInfo => TRUE, | |
340 | TimingChecks => '1') |
|
350 | -- TimingChecks => '1') | |
341 | PORT MAP ( |
|
351 | -- PORT MAP ( | |
342 | CE1_b => '0', |
|
352 | -- CE1_b => '0', | |
343 | CE2 => nSRAM_CE, |
|
353 | -- CE2 => nSRAM_CE, | |
344 |
|
|
354 | -- WE_b => nSRAM_WE, | |
345 |
|
|
355 | -- OE_b => nSRAM_OE, | |
346 | BHE_b => nSRAM_BE3, |
|
356 | -- BHE_b => nSRAM_BE3, | |
347 | BLE_b => nSRAM_BE2, |
|
357 | -- BLE_b => nSRAM_BE2, | |
348 | A => address, |
|
358 | -- A => address, | |
349 | DQ => data(31 DOWNTO 16)); |
|
359 | -- DQ => data(31 DOWNTO 16)); | |
350 |
|
360 | |||
351 |
|
361 | |||
352 | ----------------------------------------------------------------------------- |
|
362 | ----------------------------------------------------------------------------- | |
353 |
|
363 | |||
354 | WaveGen_Proc : PROCESS |
|
364 | WaveGen_Proc : PROCESS | |
355 | BEGIN |
|
365 | BEGIN | |
356 |
|
366 | |||
357 | -- insert signal assignments here |
|
367 | -- insert signal assignments here | |
358 | WAIT UNTIL clk25MHz = '1'; |
|
368 | WAIT UNTIL clk25MHz = '1'; | |
359 | rstn <= '0'; |
|
369 | rstn <= '0'; | |
360 | apbi.psel(15) <= '0'; |
|
370 | apbi.psel(15) <= '0'; | |
361 | apbi.pwrite <= '0'; |
|
371 | apbi.pwrite <= '0'; | |
362 | apbi.penable <= '0'; |
|
372 | apbi.penable <= '0'; | |
363 | apbi.paddr <= (OTHERS => '0'); |
|
373 | apbi.paddr <= (OTHERS => '0'); | |
364 | apbi.pwdata <= (OTHERS => '0'); |
|
374 | apbi.pwdata <= (OTHERS => '0'); | |
365 | fine_time <= (OTHERS => '0'); |
|
375 | fine_time <= (OTHERS => '0'); | |
366 | coarse_time <= (OTHERS => '0'); |
|
376 | coarse_time <= (OTHERS => '0'); | |
367 | WAIT UNTIL clk25MHz = '1'; |
|
377 | WAIT UNTIL clk25MHz = '1'; | |
368 | -- ahbmi.HGRANT(2) <= '1'; |
|
378 | -- ahbmi.HGRANT(2) <= '1'; | |
369 | -- ahbmi.HREADY <= '1'; |
|
379 | -- ahbmi.HREADY <= '1'; | |
370 | -- ahbmi.HRESP <= HRESP_OKAY; |
|
380 | -- ahbmi.HRESP <= HRESP_OKAY; | |
371 |
|
381 | |||
372 | WAIT UNTIL clk25MHz = '1'; |
|
382 | WAIT UNTIL clk25MHz = '1'; | |
373 | WAIT UNTIL clk25MHz = '1'; |
|
383 | WAIT UNTIL clk25MHz = '1'; | |
374 | rstn <= '1'; |
|
384 | rstn <= '1'; | |
375 | WAIT UNTIL clk25MHz = '1'; |
|
385 | WAIT UNTIL clk25MHz = '1'; | |
|
386 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000"); | |||
|
387 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000"); | |||
|
388 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000"); | |||
|
389 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000"); | |||
|
390 | ||||
|
391 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); | |||
|
392 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); | |||
|
393 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); | |||
376 | WAIT UNTIL clk25MHz = '1'; |
|
394 | WAIT UNTIL clk25MHz = '1'; | |
377 | --------------------------------------------------------------------------- |
|
395 | --------------------------------------------------------------------------- | |
378 | -- CONFIGURATION STEP |
|
396 | -- CONFIGURATION STEP | |
379 |
APB_WRITE(clk25MHz, INDEX_ |
|
397 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); | |
380 |
APB_WRITE(clk25MHz, INDEX_ |
|
398 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); | |
381 |
APB_WRITE(clk25MHz, INDEX_ |
|
399 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); | |
382 |
APB_WRITE(clk25MHz, INDEX_ |
|
400 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); | |
383 |
|
401 | |||
384 |
APB_WRITE(clk25MHz, INDEX_ |
|
402 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" | |
385 |
APB_WRITE(clk25MHz, INDEX_ |
|
403 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" | |
386 |
APB_WRITE(clk25MHz, INDEX_ |
|
404 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
387 |
APB_WRITE(clk25MHz, INDEX_ |
|
405 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" | |
388 |
APB_WRITE(clk25MHz, INDEX_ |
|
406 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
389 |
|
407 | |||
390 |
APB_WRITE(clk25MHz, INDEX_ |
|
408 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" | |
391 | -- |
|
409 | -- | |
392 |
APB_WRITE(clk25MHz, INDEX_ |
|
410 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); | |
393 |
APB_WRITE(clk25MHz, INDEX_ |
|
411 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); | |
394 |
APB_WRITE(clk25MHz, INDEX_ |
|
412 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); | |
395 |
|
413 | |||
396 |
|
414 | |||
397 | WAIT UNTIL clk25MHz = '1'; |
|
415 | WAIT UNTIL clk25MHz = '1'; | |
398 | WAIT UNTIL clk25MHz = '1'; |
|
416 | WAIT UNTIL clk25MHz = '1'; | |
399 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); |
|
417 | ||
|
418 | ||||
|
419 | --APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); | |||
400 | WAIT UNTIL clk25MHz = '1'; |
|
420 | WAIT UNTIL clk25MHz = '1'; | |
401 | WAIT UNTIL clk25MHz = '1'; |
|
421 | WAIT UNTIL clk25MHz = '1'; | |
402 | WAIT UNTIL clk25MHz = '1'; |
|
422 | WAIT UNTIL clk25MHz = '1'; | |
403 | WAIT UNTIL clk25MHz = '1'; |
|
423 | WAIT UNTIL clk25MHz = '1'; | |
404 | WAIT UNTIL clk25MHz = '1'; |
|
424 | WAIT UNTIL clk25MHz = '1'; | |
405 | WAIT UNTIL clk25MHz = '1'; |
|
425 | WAIT UNTIL clk25MHz = '1'; | |
406 | WAIT FOR 1 us; |
|
426 | WAIT FOR 1 us; | |
407 | coarse_time <= X"00000001"; |
|
427 | coarse_time <= X"00000001"; | |
408 | --------------------------------------------------------------------------- |
|
428 | --------------------------------------------------------------------------- | |
409 | -- RUN STEP |
|
429 | -- RUN STEP | |
410 | WAIT FOR 200 ms; |
|
430 | WAIT FOR 200 ms; | |
411 |
APB_WRITE(clk25MHz, INDEX_ |
|
431 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
412 |
APB_WRITE(clk25MHz, INDEX_ |
|
432 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); | |
413 | WAIT FOR 10 us; |
|
433 | WAIT FOR 10 us; | |
414 | WAIT UNTIL clk25MHz = '1'; |
|
434 | WAIT UNTIL clk25MHz = '1'; | |
415 | WAIT UNTIL clk25MHz = '1'; |
|
435 | WAIT UNTIL clk25MHz = '1'; | |
416 |
APB_WRITE(clk25MHz, INDEX_ |
|
436 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); | |
417 | WAIT UNTIL clk25MHz = '1'; |
|
437 | WAIT UNTIL clk25MHz = '1'; | |
418 | coarse_time <= X"00000010"; |
|
438 | coarse_time <= X"00000010"; | |
419 | WAIT FOR 100 ms; |
|
439 | WAIT FOR 100 ms; | |
420 |
APB_WRITE(clk25MHz, INDEX_ |
|
440 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
421 | WAIT FOR 10 us; |
|
441 | WAIT FOR 10 us; | |
422 |
APB_WRITE(clk25MHz, INDEX_ |
|
442 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); | |
423 | WAIT FOR 200 ms; |
|
443 | WAIT FOR 200 ms; | |
424 | REPORT "*** END simulation ***" SEVERITY failure; |
|
444 | REPORT "*** END simulation ***" SEVERITY failure; | |
425 |
|
445 | |||
426 |
|
446 | |||
427 | WAIT; |
|
447 | WAIT; | |
428 |
|
448 | |||
429 | END PROCESS WaveGen_Proc; |
|
449 | END PROCESS WaveGen_Proc; | |
430 | ----------------------------------------------------------------------------- |
|
450 | ----------------------------------------------------------------------------- | |
431 |
|
451 | |||
432 | ----------------------------------------------------------------------------- |
|
452 | ----------------------------------------------------------------------------- | |
433 | -- IRQ |
|
453 | -- IRQ | |
434 | ----------------------------------------------------------------------------- |
|
454 | ----------------------------------------------------------------------------- | |
435 | PROCESS (clk25MHz, rstn) |
|
455 | PROCESS (clk25MHz, rstn) | |
436 | BEGIN -- PROCESS |
|
456 | BEGIN -- PROCESS | |
437 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
457 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
438 |
|
458 | |||
439 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
459 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge | |
440 |
|
460 | |||
441 | END IF; |
|
461 | END IF; | |
442 | END PROCESS; |
|
462 | END PROCESS; | |
443 | ----------------------------------------------------------------------------- |
|
463 | ----------------------------------------------------------------------------- | |
444 |
|
464 | |||
445 | END; |
|
465 | END; |
@@ -1,45 +1,45 | |||||
1 |
|
1 | |||
2 | --================================================================================= |
|
2 | --================================================================================= | |
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT |
|
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT | |
4 | -- |
|
4 | -- | |
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID |
|
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID | |
6 | --================================================================================= |
|
6 | --================================================================================= | |
7 |
|
7 | |||
8 |
|
8 | |||
9 | LIBRARY ieee; |
|
9 | LIBRARY ieee; | |
10 | USE ieee.std_logic_1164.ALL; |
|
10 | USE ieee.std_logic_1164.ALL; | |
11 | LIBRARY grlib; |
|
11 | LIBRARY grlib; | |
12 | USE grlib.amba.ALL; |
|
12 | USE grlib.amba.ALL; | |
13 | USE std.textio.ALL; |
|
13 | USE std.textio.ALL; | |
14 |
|
14 | |||
15 |
|
15 | |||
16 | PACKAGE apb_devices_list IS |
|
16 | PACKAGE apb_devices_list IS | |
17 |
|
17 | |||
18 |
|
18 | |||
19 | CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#; |
|
19 | CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#; | |
20 |
|
20 | |||
21 | CONSTANT ROCKET_TM : amba_device_type := 16#1#; |
|
21 | CONSTANT ROCKET_TM : amba_device_type := 16#1#; | |
22 | CONSTANT otherCore : amba_device_type := 16#2#; |
|
22 | CONSTANT otherCore : amba_device_type := 16#2#; | |
23 | CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#; |
|
23 | CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#; | |
24 | CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#; |
|
24 | CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#; | |
25 | CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#; |
|
25 | CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#; | |
26 | CONSTANT LPP_UART : amba_device_type := 16#6#; |
|
26 | CONSTANT LPP_UART : amba_device_type := 16#6#; | |
27 | CONSTANT LPP_CNA : amba_device_type := 16#7#; |
|
27 | CONSTANT LPP_CNA : amba_device_type := 16#7#; | |
28 | CONSTANT LPP_APB_ADC : amba_device_type := 16#8#; |
|
28 | CONSTANT LPP_APB_ADC : amba_device_type := 16#8#; | |
29 | CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#; |
|
29 | CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#; | |
30 | CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; |
|
30 | CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; | |
31 | CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#; |
|
31 | CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#; | |
32 | CONSTANT LPP_FFT : amba_device_type := 16#12#; |
|
32 | CONSTANT LPP_FFT : amba_device_type := 16#12#; | |
33 | CONSTANT LPP_MATRIX : amba_device_type := 16#13#; |
|
33 | CONSTANT LPP_MATRIX : amba_device_type := 16#13#; | |
34 | CONSTANT LPP_DELAY : amba_device_type := 16#14#; |
|
34 | CONSTANT LPP_DELAY : amba_device_type := 16#14#; | |
35 | CONSTANT LPP_USB : amba_device_type := 16#15#; |
|
35 | CONSTANT LPP_USB : amba_device_type := 16#15#; | |
36 | CONSTANT LPP_BALISE : amba_device_type := 16#16#; |
|
36 | CONSTANT LPP_BALISE : amba_device_type := 16#16#; | |
37 | CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#; |
|
37 | CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#; | |
38 | CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; |
|
38 | CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; | |
39 | CONSTANT LPP_LFR : amba_device_type := 16#19#; |
|
39 | CONSTANT LPP_LFR : amba_device_type := 16#19#; | |
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; |
|
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; | |
41 |
|
41 | |||
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; |
|
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; | |
43 | CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; |
|
43 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A1#; | |
44 |
|
44 | |||
45 | END; |
|
45 | END; |
This diff has been collapsed as it changes many lines, (850 lines changed) Show them Hide them | |||||
@@ -1,424 +1,426 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 |
|
20 | |||
21 | LIBRARY ieee; |
|
21 | LIBRARY ieee; | |
22 | USE ieee.std_logic_1164.ALL; |
|
22 | USE ieee.std_logic_1164.ALL; | |
23 | LIBRARY grlib; |
|
23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
|
24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
|
25 | USE grlib.stdlib.ALL; | |
26 | LIBRARY techmap; |
|
26 | LIBRARY techmap; | |
27 | USE techmap.gencomp.ALL; |
|
27 | USE techmap.gencomp.ALL; | |
28 | LIBRARY gaisler; |
|
28 | LIBRARY gaisler; | |
29 | USE gaisler.memctrl.ALL; |
|
29 | USE gaisler.memctrl.ALL; | |
30 | USE gaisler.leon3.ALL; |
|
30 | USE gaisler.leon3.ALL; | |
31 | USE gaisler.uart.ALL; |
|
31 | USE gaisler.uart.ALL; | |
32 | USE gaisler.misc.ALL; |
|
32 | USE gaisler.misc.ALL; | |
33 | USE gaisler.spacewire.ALL; -- PLE |
|
33 | USE gaisler.spacewire.ALL; -- PLE | |
34 | LIBRARY esa; |
|
34 | LIBRARY esa; | |
35 | USE esa.memoryctrl.ALL; |
|
35 | USE esa.memoryctrl.ALL; | |
36 | LIBRARY lpp; |
|
36 | LIBRARY lpp; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
38 | USE lpp.lpp_ad_conv.ALL; |
|
38 | USE lpp.lpp_ad_conv.ALL; | |
39 | USE lpp.lpp_lfr_pkg.ALL; |
|
39 | USE lpp.lpp_lfr_pkg.ALL; | |
40 | USE lpp.iir_filter.ALL; |
|
40 | USE lpp.iir_filter.ALL; | |
41 | USE lpp.general_purpose.ALL; |
|
41 | USE lpp.general_purpose.ALL; | |
42 | USE lpp.lpp_lfr_time_management.ALL; |
|
42 | USE lpp.lpp_lfr_time_management.ALL; | |
43 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
43 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
44 |
|
44 | |||
45 | ENTITY leon3_soc IS |
|
45 | ENTITY leon3_soc IS | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | fabtech : INTEGER := apa3e; |
|
47 | fabtech : INTEGER := apa3e; | |
48 | memtech : INTEGER := apa3e; |
|
48 | memtech : INTEGER := apa3e; | |
49 | padtech : INTEGER := inferred; |
|
49 | padtech : INTEGER := inferred; | |
50 | clktech : INTEGER := inferred; |
|
50 | clktech : INTEGER := inferred; | |
51 | disas : INTEGER := 0; -- Enable disassembly to console |
|
51 | disas : INTEGER := 0; -- Enable disassembly to console | |
52 | dbguart : INTEGER := 0; -- Print UART on console |
|
52 | dbguart : INTEGER := 0; -- Print UART on console | |
53 | pclow : INTEGER := 2; |
|
53 | pclow : INTEGER := 2; | |
54 | -- |
|
54 | -- | |
55 | clk_freq : INTEGER := 25000; --kHz |
|
55 | clk_freq : INTEGER := 25000; --kHz | |
56 | -- |
|
56 | -- | |
57 | NB_CPU : INTEGER := 1; |
|
57 | NB_CPU : INTEGER := 1; | |
58 | ENABLE_FPU : INTEGER := 1; |
|
58 | ENABLE_FPU : INTEGER := 1; | |
59 | FPU_NETLIST : INTEGER := 1; |
|
59 | FPU_NETLIST : INTEGER := 1; | |
60 | ENABLE_DSU : INTEGER := 1; |
|
60 | ENABLE_DSU : INTEGER := 1; | |
61 | ENABLE_AHB_UART : INTEGER := 1; |
|
61 | ENABLE_AHB_UART : INTEGER := 1; | |
62 | ENABLE_APB_UART : INTEGER := 1; |
|
62 | ENABLE_APB_UART : INTEGER := 1; | |
63 | ENABLE_IRQMP : INTEGER := 1; |
|
63 | ENABLE_IRQMP : INTEGER := 1; | |
64 | ENABLE_GPT : INTEGER := 1; |
|
64 | ENABLE_GPT : INTEGER := 1; | |
65 | -- |
|
65 | -- | |
66 | NB_AHB_MASTER : INTEGER := 0; |
|
66 | NB_AHB_MASTER : INTEGER := 0; | |
67 | NB_AHB_SLAVE : INTEGER := 0; |
|
67 | NB_AHB_SLAVE : INTEGER := 0; | |
68 | NB_APB_SLAVE : INTEGER := 0 |
|
68 | NB_APB_SLAVE : INTEGER := 0 | |
69 | ); |
|
69 | ); | |
70 | PORT ( |
|
70 | PORT ( | |
71 | clk : IN STD_ULOGIC; |
|
71 | clk : IN STD_ULOGIC; | |
72 | reset : IN STD_ULOGIC; |
|
72 | reset : IN STD_ULOGIC; | |
73 |
|
73 | |||
74 | errorn : OUT STD_ULOGIC; |
|
74 | errorn : OUT STD_ULOGIC; | |
75 |
|
75 | |||
76 | -- UART AHB --------------------------------------------------------------- |
|
76 | -- UART AHB --------------------------------------------------------------- | |
77 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
|
77 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
78 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
|
78 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
79 |
|
79 | |||
80 | -- UART APB --------------------------------------------------------------- |
|
80 | -- UART APB --------------------------------------------------------------- | |
81 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
|
81 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
82 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
|
82 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
83 |
|
83 | |||
84 | -- RAM -------------------------------------------------------------------- |
|
84 | -- RAM -------------------------------------------------------------------- | |
85 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
85 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
86 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 | nSRAM_BE0 : OUT STD_LOGIC; |
|
87 | nSRAM_BE0 : OUT STD_LOGIC; | |
88 | nSRAM_BE1 : OUT STD_LOGIC; |
|
88 | nSRAM_BE1 : OUT STD_LOGIC; | |
89 | nSRAM_BE2 : OUT STD_LOGIC; |
|
89 | nSRAM_BE2 : OUT STD_LOGIC; | |
90 | nSRAM_BE3 : OUT STD_LOGIC; |
|
90 | nSRAM_BE3 : OUT STD_LOGIC; | |
91 | nSRAM_WE : OUT STD_LOGIC; |
|
91 | nSRAM_WE : OUT STD_LOGIC; | |
92 | nSRAM_CE : OUT STD_LOGIC; |
|
92 | nSRAM_CE : OUT STD_LOGIC; | |
93 | nSRAM_OE : OUT STD_LOGIC; |
|
93 | nSRAM_OE : OUT STD_LOGIC; | |
94 |
|
94 | |||
95 | -- APB -------------------------------------------------------------------- |
|
95 | -- APB -------------------------------------------------------------------- | |
96 | apbi_ext : OUT apb_slv_in_type; |
|
96 | apbi_ext : OUT apb_slv_in_type; | |
97 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
|
97 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
98 | -- AHB_Slave -------------------------------------------------------------- |
|
98 | -- AHB_Slave -------------------------------------------------------------- | |
99 | ahbi_s_ext : OUT ahb_slv_in_type; |
|
99 | ahbi_s_ext : OUT ahb_slv_in_type; | |
100 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
|
100 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
101 | -- AHB_Master ------------------------------------------------------------- |
|
101 | -- AHB_Master ------------------------------------------------------------- | |
102 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
|
102 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
103 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) |
|
103 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) | |
104 |
|
104 | |||
105 | ); |
|
105 | ); | |
106 | END; |
|
106 | END; | |
107 |
|
107 | |||
108 | ARCHITECTURE Behavioral OF leon3_soc IS |
|
108 | ARCHITECTURE Behavioral OF leon3_soc IS | |
109 |
|
109 | |||
110 | ----------------------------------------------------------------------------- |
|
110 | ----------------------------------------------------------------------------- | |
111 | -- CONFIG ------------------------------------------------------------------- |
|
111 | -- CONFIG ------------------------------------------------------------------- | |
112 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
113 |
|
113 | |||
114 | -- Clock generator |
|
114 | -- Clock generator | |
115 | constant CFG_CLKMUL : integer := (1); |
|
115 | constant CFG_CLKMUL : integer := (1); | |
116 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz |
|
116 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz | |
117 | constant CFG_OCLKDIV : integer := (1); |
|
117 | constant CFG_OCLKDIV : integer := (1); | |
118 | constant CFG_CLK_NOFB : integer := 0; |
|
118 | constant CFG_CLK_NOFB : integer := 0; | |
119 | -- LEON3 processor core |
|
119 | -- LEON3 processor core | |
120 | constant CFG_LEON3 : integer := 1; |
|
120 | constant CFG_LEON3 : integer := 1; | |
121 | constant CFG_NCPU : integer := NB_CPU; |
|
121 | constant CFG_NCPU : integer := NB_CPU; | |
122 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC |
|
122 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC | |
123 | constant CFG_V8 : integer := 0; |
|
123 | constant CFG_V8 : integer := 0; | |
124 | constant CFG_MAC : integer := 0; |
|
124 | constant CFG_MAC : integer := 0; | |
125 | constant CFG_SVT : integer := 0; |
|
125 | constant CFG_SVT : integer := 0; | |
126 | constant CFG_RSTADDR : integer := 16#00000#; |
|
126 | constant CFG_RSTADDR : integer := 16#00000#; | |
127 | constant CFG_LDDEL : integer := (1); |
|
127 | constant CFG_LDDEL : integer := (1); | |
128 | constant CFG_NWP : integer := (0); |
|
128 | constant CFG_NWP : integer := (0); | |
129 | constant CFG_PWD : integer := 1*2; |
|
129 | constant CFG_PWD : integer := 1*2; | |
130 | constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); |
|
130 | constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); | |
131 | -- 1*(8 + 16 * 0) => grfpu-light |
|
131 | -- 1*(8 + 16 * 0) => grfpu-light | |
132 | -- 1*(8 + 16 * 1) => netlist |
|
132 | -- 1*(8 + 16 * 1) => netlist | |
133 | -- 0*(8 + 16 * 0) => No FPU |
|
133 | -- 0*(8 + 16 * 0) => No FPU | |
134 | -- 0*(8 + 16 * 1) => No FPU; |
|
134 | -- 0*(8 + 16 * 1) => No FPU; | |
135 | constant CFG_ICEN : integer := 1; |
|
135 | constant CFG_ICEN : integer := 1; | |
136 | constant CFG_ISETS : integer := 1; |
|
136 | constant CFG_ISETS : integer := 1; | |
137 | constant CFG_ISETSZ : integer := 4; |
|
137 | constant CFG_ISETSZ : integer := 4; | |
138 | constant CFG_ILINE : integer := 4; |
|
138 | constant CFG_ILINE : integer := 4; | |
139 | constant CFG_IREPL : integer := 0; |
|
139 | constant CFG_IREPL : integer := 0; | |
140 | constant CFG_ILOCK : integer := 0; |
|
140 | constant CFG_ILOCK : integer := 0; | |
141 | constant CFG_ILRAMEN : integer := 0; |
|
141 | constant CFG_ILRAMEN : integer := 0; | |
142 | constant CFG_ILRAMADDR: integer := 16#8E#; |
|
142 | constant CFG_ILRAMADDR: integer := 16#8E#; | |
143 | constant CFG_ILRAMSZ : integer := 1; |
|
143 | constant CFG_ILRAMSZ : integer := 1; | |
144 | constant CFG_DCEN : integer := 1; |
|
144 | constant CFG_DCEN : integer := 1; | |
145 | constant CFG_DSETS : integer := 1; |
|
145 | constant CFG_DSETS : integer := 1; | |
146 | constant CFG_DSETSZ : integer := 4; |
|
146 | constant CFG_DSETSZ : integer := 4; | |
147 | constant CFG_DLINE : integer := 4; |
|
147 | constant CFG_DLINE : integer := 4; | |
148 | constant CFG_DREPL : integer := 0; |
|
148 | constant CFG_DREPL : integer := 0; | |
149 | constant CFG_DLOCK : integer := 0; |
|
149 | constant CFG_DLOCK : integer := 0; | |
150 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; |
|
150 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; | |
151 | constant CFG_DLRAMEN : integer := 0; |
|
151 | constant CFG_DLRAMEN : integer := 0; | |
152 | constant CFG_DLRAMADDR: integer := 16#8F#; |
|
152 | constant CFG_DLRAMADDR: integer := 16#8F#; | |
153 | constant CFG_DLRAMSZ : integer := 1; |
|
153 | constant CFG_DLRAMSZ : integer := 1; | |
154 | constant CFG_MMUEN : integer := 0; |
|
154 | constant CFG_MMUEN : integer := 0; | |
155 | constant CFG_ITLBNUM : integer := 2; |
|
155 | constant CFG_ITLBNUM : integer := 2; | |
156 | constant CFG_DTLBNUM : integer := 2; |
|
156 | constant CFG_DTLBNUM : integer := 2; | |
157 | constant CFG_TLB_TYPE : integer := 1 + 0*2; |
|
157 | constant CFG_TLB_TYPE : integer := 1 + 0*2; | |
158 | constant CFG_TLB_REP : integer := 1; |
|
158 | constant CFG_TLB_REP : integer := 1; | |
159 |
|
159 | |||
160 | constant CFG_DSU : integer := ENABLE_DSU; |
|
160 | constant CFG_DSU : integer := ENABLE_DSU; | |
161 | constant CFG_ITBSZ : integer := 0; |
|
161 | constant CFG_ITBSZ : integer := 0; | |
162 | constant CFG_ATBSZ : integer := 0; |
|
162 | constant CFG_ATBSZ : integer := 0; | |
163 |
|
163 | |||
164 | -- AMBA settings |
|
164 | -- AMBA settings | |
165 | constant CFG_DEFMST : integer := (0); |
|
165 | constant CFG_DEFMST : integer := (0); | |
166 | constant CFG_RROBIN : integer := 1; |
|
166 | constant CFG_RROBIN : integer := 1; | |
167 | constant CFG_SPLIT : integer := 0; |
|
167 | constant CFG_SPLIT : integer := 0; | |
168 | constant CFG_AHBIO : integer := 16#FFF#; |
|
168 | constant CFG_AHBIO : integer := 16#FFF#; | |
169 | constant CFG_APBADDR : integer := 16#800#; |
|
169 | constant CFG_APBADDR : integer := 16#800#; | |
170 |
|
170 | |||
171 | -- DSU UART |
|
171 | -- DSU UART | |
172 | constant CFG_AHB_UART : integer := ENABLE_AHB_UART; |
|
172 | constant CFG_AHB_UART : integer := ENABLE_AHB_UART; | |
173 |
|
173 | |||
174 | -- LEON2 memory controller |
|
174 | -- LEON2 memory controller | |
175 | constant CFG_MCTRL_SDEN : integer := 0; |
|
175 | constant CFG_MCTRL_SDEN : integer := 0; | |
176 |
|
176 | |||
177 | -- UART 1 |
|
177 | -- UART 1 | |
178 | constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; |
|
178 | constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; | |
179 | constant CFG_UART1_FIFO : integer := 1; |
|
179 | constant CFG_UART1_FIFO : integer := 1; | |
180 |
|
180 | |||
181 | -- LEON3 interrupt controller |
|
181 | -- LEON3 interrupt controller | |
182 | constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; |
|
182 | constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; | |
183 |
|
183 | |||
184 | -- Modular timer |
|
184 | -- Modular timer | |
185 | constant CFG_GPT_ENABLE : integer := ENABLE_GPT; |
|
185 | constant CFG_GPT_ENABLE : integer := ENABLE_GPT; | |
186 | constant CFG_GPT_NTIM : integer := (2); |
|
186 | constant CFG_GPT_NTIM : integer := (2); | |
187 | constant CFG_GPT_SW : integer := (8); |
|
187 | constant CFG_GPT_SW : integer := (8); | |
188 | constant CFG_GPT_TW : integer := (32); |
|
188 | constant CFG_GPT_TW : integer := (32); | |
189 | constant CFG_GPT_IRQ : integer := (8); |
|
189 | constant CFG_GPT_IRQ : integer := (8); | |
190 | constant CFG_GPT_SEPIRQ : integer := 1; |
|
190 | constant CFG_GPT_SEPIRQ : integer := 1; | |
191 | constant CFG_GPT_WDOGEN : integer := 0; |
|
191 | constant CFG_GPT_WDOGEN : integer := 0; | |
192 | constant CFG_GPT_WDOG : integer := 16#0#; |
|
192 | constant CFG_GPT_WDOG : integer := 16#0#; | |
193 | ----------------------------------------------------------------------------- |
|
193 | ----------------------------------------------------------------------------- | |
194 |
|
194 | |||
195 | ----------------------------------------------------------------------------- |
|
195 | ----------------------------------------------------------------------------- | |
196 | -- SIGNALs |
|
196 | -- SIGNALs | |
197 | ----------------------------------------------------------------------------- |
|
197 | ----------------------------------------------------------------------------- | |
198 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; |
|
198 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; | |
199 | -- CLK & RST -- |
|
199 | -- CLK & RST -- | |
200 | SIGNAL clk2x : STD_ULOGIC; |
|
200 | SIGNAL clk2x : STD_ULOGIC; | |
201 | SIGNAL clkmn : STD_ULOGIC; |
|
201 | SIGNAL clkmn : STD_ULOGIC; | |
202 | SIGNAL clkm : STD_ULOGIC; |
|
202 | SIGNAL clkm : STD_ULOGIC; | |
203 | SIGNAL rstn : STD_ULOGIC; |
|
203 | SIGNAL rstn : STD_ULOGIC; | |
204 | SIGNAL rstraw : STD_ULOGIC; |
|
204 | SIGNAL rstraw : STD_ULOGIC; | |
205 | SIGNAL pciclk : STD_ULOGIC; |
|
205 | SIGNAL pciclk : STD_ULOGIC; | |
206 | SIGNAL sdclkl : STD_ULOGIC; |
|
206 | SIGNAL sdclkl : STD_ULOGIC; | |
207 | SIGNAL cgi : clkgen_in_type; |
|
207 | SIGNAL cgi : clkgen_in_type; | |
208 | SIGNAL cgo : clkgen_out_type; |
|
208 | SIGNAL cgo : clkgen_out_type; | |
209 | --- AHB / APB |
|
209 | --- AHB / APB | |
210 | SIGNAL apbi : apb_slv_in_type; |
|
210 | SIGNAL apbi : apb_slv_in_type; | |
211 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
211 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
212 | SIGNAL ahbsi : ahb_slv_in_type; |
|
212 | SIGNAL ahbsi : ahb_slv_in_type; | |
213 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
213 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
214 | SIGNAL ahbmi : ahb_mst_in_type; |
|
214 | SIGNAL ahbmi : ahb_mst_in_type; | |
215 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
215 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
216 | --UART |
|
216 | --UART | |
217 | SIGNAL ahbuarti : uart_in_type; |
|
217 | SIGNAL ahbuarti : uart_in_type; | |
218 | SIGNAL ahbuarto : uart_out_type; |
|
218 | SIGNAL ahbuarto : uart_out_type; | |
219 | SIGNAL apbuarti : uart_in_type; |
|
219 | SIGNAL apbuarti : uart_in_type; | |
220 | SIGNAL apbuarto : uart_out_type; |
|
220 | SIGNAL apbuarto : uart_out_type; | |
221 | --MEM CTRLR |
|
221 | --MEM CTRLR | |
222 | SIGNAL memi : memory_in_type; |
|
222 | SIGNAL memi : memory_in_type; | |
223 | SIGNAL memo : memory_out_type; |
|
223 | SIGNAL memo : memory_out_type; | |
224 | SIGNAL wpo : wprot_out_type; |
|
224 | SIGNAL wpo : wprot_out_type; | |
225 | SIGNAL sdo : sdram_out_type; |
|
225 | SIGNAL sdo : sdram_out_type; | |
226 | --IRQ |
|
226 | --IRQ | |
227 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
|
227 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
228 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
|
228 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
229 | --Timer |
|
229 | --Timer | |
230 | SIGNAL gpti : gptimer_in_type; |
|
230 | SIGNAL gpti : gptimer_in_type; | |
231 | SIGNAL gpto : gptimer_out_type; |
|
231 | SIGNAL gpto : gptimer_out_type; | |
232 | --DSU |
|
232 | --DSU | |
233 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
|
233 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
234 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
|
234 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
235 | SIGNAL dsui : dsu_in_type; |
|
235 | SIGNAL dsui : dsu_in_type; | |
236 | SIGNAL dsuo : dsu_out_type; |
|
236 | SIGNAL dsuo : dsu_out_type; | |
237 | ----------------------------------------------------------------------------- |
|
237 | ----------------------------------------------------------------------------- | |
238 | BEGIN |
|
238 | ||
239 |
|
239 | SIGNAL nSRAM_CE_s : STD_LOGIC; | ||
240 |
|
240 | BEGIN | ||
241 | ---------------------------------------------------------------------- |
|
241 | ||
242 | --- Reset and Clock generation ------------------------------------- |
|
242 | ||
243 | ---------------------------------------------------------------------- |
|
243 | ---------------------------------------------------------------------- | |
244 |
|
244 | --- Reset and Clock generation ------------------------------------- | ||
245 | cgi.pllctrl <= "00"; |
|
245 | ---------------------------------------------------------------------- | |
246 | cgi.pllrst <= rstraw; |
|
246 | ||
247 |
|
247 | cgi.pllctrl <= "00"; | ||
248 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); |
|
248 | cgi.pllrst <= rstraw; | |
249 |
|
249 | |||
250 | clkgen0 : clkgen -- clock generator |
|
250 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
251 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
251 | ||
252 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) |
|
252 | clkgen0 : clkgen -- clock generator | |
253 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
|
253 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
254 |
|
254 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) | ||
255 | ---------------------------------------------------------------------- |
|
255 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
256 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
256 | ||
257 | ---------------------------------------------------------------------- |
|
257 | ---------------------------------------------------------------------- | |
258 |
|
258 | --- LEON3 processor / DSU / IRQ ------------------------------------ | ||
259 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
259 | ---------------------------------------------------------------------- | |
260 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
260 | ||
261 | u0 : leon3s -- LEON3 processor |
|
261 | l3 : IF CFG_LEON3 = 1 GENERATE | |
262 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
262 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
263 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
263 | u0 : leon3s -- LEON3 processor | |
264 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
264 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
265 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
265 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
266 |
CFG_ |
|
266 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
267 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
267 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
268 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
268 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
269 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
269 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
270 | END GENERATE; |
|
270 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
271 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
271 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
272 |
|
272 | END GENERATE; | ||
273 | dsugen : IF CFG_DSU = 1 GENERATE |
|
273 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
274 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
274 | ||
275 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
275 | dsugen : IF CFG_DSU = 1 GENERATE | |
276 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
276 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
277 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
277 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
278 | dsui.enable <= '1'; |
|
278 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
279 | dsui.break <= '0'; |
|
279 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
280 | END GENERATE; |
|
280 | dsui.enable <= '1'; | |
281 | END GENERATE; |
|
281 | dsui.break <= '0'; | |
282 |
|
282 | END GENERATE; | ||
283 | nodsu : IF CFG_DSU = 0 GENERATE |
|
283 | END GENERATE; | |
284 | ahbso(2) <= ahbs_none; |
|
284 | ||
285 | dsuo.tstop <= '0'; |
|
285 | nodsu : IF CFG_DSU = 0 GENERATE | |
286 | dsuo.active <= '0'; |
|
286 | ahbso(2) <= ahbs_none; | |
287 | END GENERATE; |
|
287 | dsuo.tstop <= '0'; | |
288 |
|
288 | dsuo.active <= '0'; | ||
289 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
289 | END GENERATE; | |
290 | irqctrl0 : irqmp -- interrupt controller |
|
290 | ||
291 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
291 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
292 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
292 | irqctrl0 : irqmp -- interrupt controller | |
293 | END GENERATE; |
|
293 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
294 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
294 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
295 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
295 | END GENERATE; | |
296 | irqi(i).irl <= "0000"; |
|
296 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
297 | END GENERATE; |
|
297 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
298 | apbo(2) <= apb_none; |
|
298 | irqi(i).irl <= "0000"; | |
299 | END GENERATE; |
|
299 | END GENERATE; | |
300 |
|
300 | apbo(2) <= apb_none; | ||
301 | ---------------------------------------------------------------------- |
|
301 | END GENERATE; | |
302 | --- Memory controllers --------------------------------------------- |
|
302 | ||
303 | ---------------------------------------------------------------------- |
|
303 | ---------------------------------------------------------------------- | |
304 | memctrlr : mctrl GENERIC MAP ( |
|
304 | --- Memory controllers --------------------------------------------- | |
305 | hindex => 0, |
|
305 | ---------------------------------------------------------------------- | |
306 | pindex => 0, |
|
306 | memctrlr : mctrl GENERIC MAP ( | |
307 |
|
|
307 | hindex => 0, | |
308 | srbanks => 1 |
|
308 | pindex => 0, | |
309 | ) |
|
309 | paddr => 0, | |
310 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
310 | srbanks => 1 | |
311 |
|
311 | ) | ||
312 | memi.brdyn <= '1'; |
|
312 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
313 | memi.bexcn <= '1'; |
|
313 | ||
314 |
memi. |
|
314 | memi.brdyn <= '1'; | |
315 |
memi. |
|
315 | memi.bexcn <= '1'; | |
316 |
memi. |
|
316 | memi.writen <= '1'; | |
317 |
|
317 | memi.wrn <= "1111"; | ||
318 | bdr : FOR i IN 0 TO 3 GENERATE |
|
318 | memi.bwidth <= "10"; | |
319 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
319 | ||
320 | PORT MAP ( |
|
320 | bdr : FOR i IN 0 TO 3 GENERATE | |
321 | data(31-i*8 DOWNTO 24-i*8), |
|
321 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
322 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
322 | PORT MAP ( | |
323 | memo.bdrive(i), |
|
323 | data(31-i*8 DOWNTO 24-i*8), | |
324 |
mem |
|
324 | memo.data(31-i*8 DOWNTO 24-i*8), | |
325 | END GENERATE; |
|
325 | memo.bdrive(i), | |
326 |
|
326 | memi.data(31-i*8 DOWNTO 24-i*8)); | ||
327 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
327 | END GENERATE; | |
328 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
328 | ||
329 |
|
329 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | ||
330 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); |
|
330 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
331 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
331 | nSRAM_CE_s <= NOT(memo.ramsn(0)); | |
332 |
|
|
332 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
333 |
n |
|
333 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
334 |
nBW |
|
334 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
335 |
nBW |
|
335 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
336 |
nBW |
|
336 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
337 |
|
337 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | ||
338 | ---------------------------------------------------------------------- |
|
338 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
339 | --- AHB CONTROLLER ------------------------------------------------- |
|
339 | ||
340 | ---------------------------------------------------------------------- |
|
340 | ---------------------------------------------------------------------- | |
341 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
341 | --- AHB CONTROLLER ------------------------------------------------- | |
342 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
342 | ---------------------------------------------------------------------- | |
343 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
343 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
344 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) |
|
344 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
345 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
345 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
346 |
|
346 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) | ||
347 | ---------------------------------------------------------------------- |
|
347 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
348 | --- AHB UART ------------------------------------------------------- |
|
348 | ||
349 | ---------------------------------------------------------------------- |
|
349 | ---------------------------------------------------------------------- | |
350 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
350 | --- AHB UART ------------------------------------------------------- | |
351 | dcom0 : ahbuart |
|
351 | ---------------------------------------------------------------------- | |
352 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) |
|
352 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
353 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); |
|
353 | dcom0 : ahbuart | |
354 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
|
354 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) | |
355 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
|
355 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); | |
356 | END GENERATE; |
|
356 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
357 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
357 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
358 |
|
358 | END GENERATE; | ||
359 | ---------------------------------------------------------------------- |
|
359 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
360 | --- APB Bridge ----------------------------------------------------- |
|
360 | ||
361 | ---------------------------------------------------------------------- |
|
361 | ---------------------------------------------------------------------- | |
362 | apb0 : apbctrl -- AHB/APB bridge |
|
362 | --- APB Bridge ----------------------------------------------------- | |
363 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
363 | ---------------------------------------------------------------------- | |
364 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
364 | apb0 : apbctrl -- AHB/APB bridge | |
365 |
|
365 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | ||
366 | ---------------------------------------------------------------------- |
|
366 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
367 | --- GPT Timer ------------------------------------------------------ |
|
367 | ||
368 | ---------------------------------------------------------------------- |
|
368 | ---------------------------------------------------------------------- | |
369 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
369 | --- GPT Timer ------------------------------------------------------ | |
370 | timer0 : gptimer -- timer unit |
|
370 | ---------------------------------------------------------------------- | |
371 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
371 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
372 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
372 | timer0 : gptimer -- timer unit | |
373 | nbits => CFG_GPT_TW) |
|
373 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
374 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
374 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
375 | gpti.dhalt <= dsuo.tstop; |
|
375 | nbits => CFG_GPT_TW) | |
376 | gpti.extclk <= '0'; |
|
376 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
377 | END GENERATE; |
|
377 | gpti.dhalt <= dsuo.tstop; | |
378 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
378 | gpti.extclk <= '0'; | |
379 |
|
379 | END GENERATE; | ||
380 |
|
380 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | ||
381 | ---------------------------------------------------------------------- |
|
381 | ||
382 | --- APB UART ------------------------------------------------------- |
|
382 | ||
383 | ---------------------------------------------------------------------- |
|
383 | ---------------------------------------------------------------------- | |
384 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
384 | --- APB UART ------------------------------------------------------- | |
385 | uart1 : apbuart -- UART 1 |
|
385 | ---------------------------------------------------------------------- | |
386 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
386 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
387 | fifosize => CFG_UART1_FIFO) |
|
387 | uart1 : apbuart -- UART 1 | |
388 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
388 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
389 | apbuarti.rxd <= urxd1; |
|
389 | fifosize => CFG_UART1_FIFO) | |
390 | apbuarti.extclk <= '0'; |
|
390 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
391 | utxd1 <= apbuarto.txd; |
|
391 | apbuarti.rxd <= urxd1; | |
392 |
apbuarti. |
|
392 | apbuarti.extclk <= '0'; | |
393 | END GENERATE; |
|
393 | utxd1 <= apbuarto.txd; | |
394 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
394 | apbuarti.ctsn <= '0'; | |
395 |
|
395 | END GENERATE; | ||
396 | ------------------------------------------------------------------------------- |
|
396 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
397 | -- AMBA BUS ------------------------------------------------------------------- |
|
397 | ||
398 | ------------------------------------------------------------------------------- |
|
398 | ------------------------------------------------------------------------------- | |
399 |
|
399 | -- AMBA BUS ------------------------------------------------------------------- | ||
400 |
|
|
400 | ------------------------------------------------------------------------------- | |
401 | apbi_ext <= apbi; |
|
401 | ||
402 | all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE |
|
402 | -- APB -------------------------------------------------------------------- | |
403 | max_16_apb: IF I + 5 < 16 GENERATE |
|
403 | apbi_ext <= apbi; | |
404 | apbo(I+5)<= apbo_ext(I+5); |
|
404 | all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE | |
405 | END GENERATE max_16_apb; |
|
405 | max_16_apb: IF I + 5 < 16 GENERATE | |
406 | END GENERATE all_apb; |
|
406 | apbo(I+5)<= apbo_ext(I+5); | |
407 | -- AHB_Slave -------------------------------------------------------------- |
|
407 | END GENERATE max_16_apb; | |
408 | ahbi_s_ext <= ahbsi; |
|
408 | END GENERATE all_apb; | |
409 | all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE |
|
409 | -- AHB_Slave -------------------------------------------------------------- | |
410 | max_16_ahbs: IF I + 3 < 16 GENERATE |
|
410 | ahbi_s_ext <= ahbsi; | |
411 | ahbso(I+3) <= ahbo_s_ext(I+3); |
|
411 | all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE | |
412 | END GENERATE max_16_ahbs; |
|
412 | max_16_ahbs: IF I + 3 < 16 GENERATE | |
413 | END GENERATE all_ahbs; |
|
413 | ahbso(I+3) <= ahbo_s_ext(I+3); | |
414 | -- AHB_Master ------------------------------------------------------------- |
|
414 | END GENERATE max_16_ahbs; | |
415 | ahbi_m_ext <= ahbmi; |
|
415 | END GENERATE all_ahbs; | |
416 | all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE |
|
416 | -- AHB_Master ------------------------------------------------------------- | |
417 | max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE |
|
417 | ahbi_m_ext <= ahbmi; | |
418 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); |
|
418 | all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE | |
419 | END GENERATE max_16_ahbm; |
|
419 | max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE | |
420 | END GENERATE all_ahbm; |
|
420 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); | |
421 |
|
421 | END GENERATE max_16_ahbm; | ||
422 |
|
422 | END GENERATE all_ahbm; | ||
423 |
|
423 | |||
424 | END Behavioral; |
|
424 | ||
|
425 | ||||
|
426 | END Behavioral; |
@@ -1,714 +1,758 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 |
|
15 | |||
16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
18 |
|
18 | |||
19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
24 |
|
24 | |||
25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
26 | GENERIC ( |
|
26 | GENERIC ( | |
27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
29 | nb_word_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
33 |
|
33 | |||
34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
39 |
|
39 | |||
40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
41 |
|
41 | |||
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
43 |
|
43 | |||
44 | ); |
|
44 | ); | |
45 | PORT ( |
|
45 | PORT ( | |
46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
48 | -- SAMPLE |
|
48 | -- SAMPLE | |
49 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
49 | sample_B : IN Samples14v(2 DOWNTO 0); | |
50 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
50 | sample_E : IN Samples14v(4 DOWNTO 0); | |
51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
52 | -- APB |
|
52 | -- APB | |
53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
55 | -- AHB |
|
55 | -- AHB | |
56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
58 | -- TIME |
|
58 | -- TIME | |
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | data_shaping_BW : OUT STD_LOGIC--; | |
63 |
|
63 | |||
64 | --debug |
|
64 | --debug | |
65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
65 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
66 | debug_f0_data_valid : OUT STD_LOGIC; |
|
66 | --debug_f0_data_valid : OUT STD_LOGIC; | |
67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
68 | debug_f1_data_valid : OUT STD_LOGIC; |
|
68 | --debug_f1_data_valid : OUT STD_LOGIC; | |
69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
70 | debug_f2_data_valid : OUT STD_LOGIC; |
|
70 | --debug_f2_data_valid : OUT STD_LOGIC; | |
71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
72 | debug_f3_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f3_data_valid : OUT STD_LOGIC; | |
73 |
|
73 | |||
74 | -- debug FIFO_IN |
|
74 | ---- debug FIFO_IN | |
75 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
76 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
77 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
79 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
81 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
83 |
|
83 | |||
84 | --debug FIFO OUT |
|
84 | ----debug FIFO OUT | |
85 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
86 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
87 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
89 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
91 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
93 |
|
93 | |||
94 | --debug DMA IN |
|
94 | ----debug DMA IN | |
95 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
95 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
96 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
96 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
97 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
99 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
100 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
101 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
102 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
103 | ); |
|
103 | ); | |
104 | END lpp_lfr; |
|
104 | END lpp_lfr; | |
105 |
|
105 | |||
106 | ARCHITECTURE beh OF lpp_lfr IS |
|
106 | ARCHITECTURE beh OF lpp_lfr IS | |
107 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
107 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
108 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
108 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
109 | -- |
|
109 | -- | |
110 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
110 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
111 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
111 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
112 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
112 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
113 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
113 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
114 | -- |
|
114 | -- | |
115 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
115 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
116 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
116 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
117 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
117 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
118 | -- |
|
118 | -- | |
119 | SIGNAL sample_f0_val : STD_LOGIC; |
|
119 | SIGNAL sample_f0_val : STD_LOGIC; | |
120 | SIGNAL sample_f1_val : STD_LOGIC; |
|
120 | SIGNAL sample_f1_val : STD_LOGIC; | |
121 | SIGNAL sample_f2_val : STD_LOGIC; |
|
121 | SIGNAL sample_f2_val : STD_LOGIC; | |
122 | SIGNAL sample_f3_val : STD_LOGIC; |
|
122 | SIGNAL sample_f3_val : STD_LOGIC; | |
123 | -- |
|
123 | -- | |
124 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
124 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
125 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
125 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
126 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
126 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
127 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
128 | -- |
|
128 | -- | |
129 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
130 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
130 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
131 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
132 |
|
132 | |||
133 | -- SM |
|
133 | -- SM | |
134 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
134 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
135 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
135 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
136 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
136 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
137 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
138 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
138 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
139 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
139 | SIGNAL error_bad_component_error : STD_LOGIC; | |
140 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
141 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
141 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
142 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
142 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
143 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
143 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
144 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
145 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
145 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
146 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
146 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
147 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
147 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
148 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
148 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
149 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
149 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
150 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
150 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
152 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
153 |
|
153 | |||
154 | -- WFP |
|
154 | -- WFP | |
155 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
155 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
156 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
156 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
157 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
157 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
158 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
159 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
159 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
160 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
160 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
161 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
161 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
162 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
163 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
163 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
164 |
|
164 | |||
165 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
165 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
166 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
166 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
167 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
167 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
168 | SIGNAL enable_f0 : STD_LOGIC; |
|
168 | SIGNAL enable_f0 : STD_LOGIC; | |
169 | SIGNAL enable_f1 : STD_LOGIC; |
|
169 | SIGNAL enable_f1 : STD_LOGIC; | |
170 | SIGNAL enable_f2 : STD_LOGIC; |
|
170 | SIGNAL enable_f2 : STD_LOGIC; | |
171 | SIGNAL enable_f3 : STD_LOGIC; |
|
171 | SIGNAL enable_f3 : STD_LOGIC; | |
172 | SIGNAL burst_f0 : STD_LOGIC; |
|
172 | SIGNAL burst_f0 : STD_LOGIC; | |
173 | SIGNAL burst_f1 : STD_LOGIC; |
|
173 | SIGNAL burst_f1 : STD_LOGIC; | |
174 | SIGNAL burst_f2 : STD_LOGIC; |
|
174 | SIGNAL burst_f2 : STD_LOGIC; | |
175 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
176 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
176 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
177 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
178 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
179 |
|
179 | |||
180 | SIGNAL run : STD_LOGIC; |
|
180 | SIGNAL run : STD_LOGIC; | |
181 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
181 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
182 |
|
182 | |||
183 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
183 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
184 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
184 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
185 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
185 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
186 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
186 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
187 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
187 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
188 | --f1 |
|
188 | --f1 | |
189 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
189 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
190 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
190 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
191 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
191 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
192 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
192 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
193 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
193 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
194 | --f2 |
|
194 | --f2 | |
195 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
195 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
196 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
197 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
197 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
198 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
198 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
199 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
200 | --f3 |
|
200 | --f3 | |
201 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
201 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
202 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
202 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
203 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
203 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
204 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
204 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
205 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
205 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
206 |
|
206 | |||
207 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
208 | -- |
|
208 | -- | |
209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
210 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
210 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
211 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
211 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
212 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
212 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
213 | --f1 |
|
213 | --f1 | |
214 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
214 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
215 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
215 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
216 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
216 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
217 | --f2 |
|
217 | --f2 | |
218 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
218 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
219 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
219 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
220 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
220 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
221 | --f3 |
|
221 | --f3 | |
222 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
222 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
223 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
223 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
224 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
224 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
225 |
|
225 | |||
226 | ----------------------------------------------------------------------------- |
|
226 | ----------------------------------------------------------------------------- | |
227 | -- DMA RR |
|
227 | -- DMA RR | |
228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
229 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
229 | SIGNAL dma_sel_valid : STD_LOGIC; | |
230 |
SIGNAL dma_ |
|
230 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
231 |
SIGNAL dma_rr_ |
|
231 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
232 |
SIGNAL dma_rr_grant |
|
232 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
233 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
234 | ||||
|
235 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
236 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
233 |
|
237 | |||
234 | ----------------------------------------------------------------------------- |
|
238 | ----------------------------------------------------------------------------- | |
235 | -- DMA_REG |
|
239 | -- DMA_REG | |
236 | ----------------------------------------------------------------------------- |
|
240 | ----------------------------------------------------------------------------- | |
237 | SIGNAL ongoing_reg : STD_LOGIC; |
|
241 | SIGNAL ongoing_reg : STD_LOGIC; | |
238 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
242 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
239 | SIGNAL dma_send_reg : STD_LOGIC; |
|
243 | SIGNAL dma_send_reg : STD_LOGIC; | |
240 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
244 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
241 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
245 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
242 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
246 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
243 |
|
247 | |||
244 |
|
248 | |||
245 | ----------------------------------------------------------------------------- |
|
249 | ----------------------------------------------------------------------------- | |
246 | -- DMA |
|
250 | -- DMA | |
247 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
248 | SIGNAL dma_send : STD_LOGIC; |
|
252 | SIGNAL dma_send : STD_LOGIC; | |
249 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
253 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
250 | SIGNAL dma_done : STD_LOGIC; |
|
254 | SIGNAL dma_done : STD_LOGIC; | |
251 | SIGNAL dma_ren : STD_LOGIC; |
|
255 | SIGNAL dma_ren : STD_LOGIC; | |
252 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
256 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
253 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
257 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
254 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
258 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
255 |
|
259 | |||
256 | ----------------------------------------------------------------------------- |
|
260 | ----------------------------------------------------------------------------- | |
257 | -- DEBUG |
|
261 | -- DEBUG | |
258 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
259 | -- |
|
263 | -- | |
260 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
264 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
261 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
265 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
262 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
266 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
263 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
267 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
264 |
|
268 | |||
265 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
269 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
266 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
270 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
267 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
271 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
268 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
269 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
270 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
271 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
272 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
277 | ||||
|
278 | ----------------------------------------------------------------------------- | |||
|
279 | -- MS | |||
|
280 | ----------------------------------------------------------------------------- | |||
|
281 | ||||
|
282 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
283 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
284 | SIGNAL data_ms_valid : STD_LOGIC; | |||
|
285 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |||
|
286 | SIGNAL data_ms_ren : STD_LOGIC; | |||
|
287 | SIGNAL data_ms_done : STD_LOGIC; | |||
273 |
|
288 | |||
274 | BEGIN |
|
289 | BEGIN | |
275 |
|
290 | |||
276 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
291 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
277 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
292 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
278 |
|
293 | |||
279 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
294 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
280 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
295 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
281 | END GENERATE all_channel; |
|
296 | END GENERATE all_channel; | |
282 |
|
297 | |||
283 | ----------------------------------------------------------------------------- |
|
298 | ----------------------------------------------------------------------------- | |
284 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
299 | lpp_lfr_filter_1 : lpp_lfr_filter | |
285 | GENERIC MAP ( |
|
300 | GENERIC MAP ( | |
286 | Mem_use => Mem_use) |
|
301 | Mem_use => Mem_use) | |
287 | PORT MAP ( |
|
302 | PORT MAP ( | |
288 | sample => sample_s, |
|
303 | sample => sample_s, | |
289 | sample_val => sample_val, |
|
304 | sample_val => sample_val, | |
290 | clk => clk, |
|
305 | clk => clk, | |
291 | rstn => rstn, |
|
306 | rstn => rstn, | |
292 | data_shaping_SP0 => data_shaping_SP0, |
|
307 | data_shaping_SP0 => data_shaping_SP0, | |
293 | data_shaping_SP1 => data_shaping_SP1, |
|
308 | data_shaping_SP1 => data_shaping_SP1, | |
294 | data_shaping_R0 => data_shaping_R0, |
|
309 | data_shaping_R0 => data_shaping_R0, | |
295 | data_shaping_R1 => data_shaping_R1, |
|
310 | data_shaping_R1 => data_shaping_R1, | |
296 | sample_f0_val => sample_f0_val, |
|
311 | sample_f0_val => sample_f0_val, | |
297 | sample_f1_val => sample_f1_val, |
|
312 | sample_f1_val => sample_f1_val, | |
298 | sample_f2_val => sample_f2_val, |
|
313 | sample_f2_val => sample_f2_val, | |
299 | sample_f3_val => sample_f3_val, |
|
314 | sample_f3_val => sample_f3_val, | |
300 | sample_f0_wdata => sample_f0_data, |
|
315 | sample_f0_wdata => sample_f0_data, | |
301 | sample_f1_wdata => sample_f1_data, |
|
316 | sample_f1_wdata => sample_f1_data, | |
302 | sample_f2_wdata => sample_f2_data, |
|
317 | sample_f2_wdata => sample_f2_data, | |
303 | sample_f3_wdata => sample_f3_data); |
|
318 | sample_f3_wdata => sample_f3_data); | |
304 |
|
319 | |||
305 | ----------------------------------------------------------------------------- |
|
320 | ----------------------------------------------------------------------------- | |
306 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
321 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
307 | GENERIC MAP ( |
|
322 | GENERIC MAP ( | |
308 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
323 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
309 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
324 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
310 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
325 | nb_snapshot_param_size => nb_snapshot_param_size, | |
311 | delta_vector_size => delta_vector_size, |
|
326 | delta_vector_size => delta_vector_size, | |
312 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
327 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
313 | pindex => pindex, |
|
328 | pindex => pindex, | |
314 | paddr => paddr, |
|
329 | paddr => paddr, | |
315 | pmask => pmask, |
|
330 | pmask => pmask, | |
316 | pirq_ms => pirq_ms, |
|
331 | pirq_ms => pirq_ms, | |
317 | pirq_wfp => pirq_wfp, |
|
332 | pirq_wfp => pirq_wfp, | |
318 | top_lfr_version => top_lfr_version) |
|
333 | top_lfr_version => top_lfr_version) | |
319 | PORT MAP ( |
|
334 | PORT MAP ( | |
320 | HCLK => clk, |
|
335 | HCLK => clk, | |
321 | HRESETn => rstn, |
|
336 | HRESETn => rstn, | |
322 | apbi => apbi, |
|
337 | apbi => apbi, | |
323 | apbo => apbo, |
|
338 | apbo => apbo, | |
324 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
339 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
325 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
340 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
326 | ready_matrix_f1 => ready_matrix_f1, |
|
341 | ready_matrix_f1 => ready_matrix_f1, | |
327 | ready_matrix_f2 => ready_matrix_f2, |
|
342 | ready_matrix_f2 => ready_matrix_f2, | |
328 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
343 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
329 | error_bad_component_error => error_bad_component_error, |
|
344 | error_bad_component_error => error_bad_component_error, | |
330 | debug_reg => debug_reg, |
|
345 | debug_reg => debug_reg, | |
331 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
346 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
332 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
347 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
333 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
348 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
334 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
349 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
335 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
350 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
336 | status_error_bad_component_error => status_error_bad_component_error, |
|
351 | status_error_bad_component_error => status_error_bad_component_error, | |
337 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
352 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
338 | config_active_interruption_onError => config_active_interruption_onError, |
|
353 | config_active_interruption_onError => config_active_interruption_onError, | |
339 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
354 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
340 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
355 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
341 | addr_matrix_f1 => addr_matrix_f1, |
|
356 | addr_matrix_f1 => addr_matrix_f1, | |
342 | addr_matrix_f2 => addr_matrix_f2, |
|
357 | addr_matrix_f2 => addr_matrix_f2, | |
343 | status_full => status_full, |
|
358 | status_full => status_full, | |
344 | status_full_ack => status_full_ack, |
|
359 | status_full_ack => status_full_ack, | |
345 | status_full_err => status_full_err, |
|
360 | status_full_err => status_full_err, | |
346 | status_new_err => status_new_err, |
|
361 | status_new_err => status_new_err, | |
347 | data_shaping_BW => data_shaping_BW, |
|
362 | data_shaping_BW => data_shaping_BW, | |
348 | data_shaping_SP0 => data_shaping_SP0, |
|
363 | data_shaping_SP0 => data_shaping_SP0, | |
349 | data_shaping_SP1 => data_shaping_SP1, |
|
364 | data_shaping_SP1 => data_shaping_SP1, | |
350 | data_shaping_R0 => data_shaping_R0, |
|
365 | data_shaping_R0 => data_shaping_R0, | |
351 | data_shaping_R1 => data_shaping_R1, |
|
366 | data_shaping_R1 => data_shaping_R1, | |
352 | delta_snapshot => delta_snapshot, |
|
367 | delta_snapshot => delta_snapshot, | |
353 | delta_f0 => delta_f0, |
|
368 | delta_f0 => delta_f0, | |
354 | delta_f0_2 => delta_f0_2, |
|
369 | delta_f0_2 => delta_f0_2, | |
355 | delta_f1 => delta_f1, |
|
370 | delta_f1 => delta_f1, | |
356 | delta_f2 => delta_f2, |
|
371 | delta_f2 => delta_f2, | |
357 | nb_data_by_buffer => nb_data_by_buffer, |
|
372 | nb_data_by_buffer => nb_data_by_buffer, | |
358 | nb_word_by_buffer => nb_word_by_buffer, |
|
373 | nb_word_by_buffer => nb_word_by_buffer, | |
359 | nb_snapshot_param => nb_snapshot_param, |
|
374 | nb_snapshot_param => nb_snapshot_param, | |
360 | enable_f0 => enable_f0, |
|
375 | enable_f0 => enable_f0, | |
361 | enable_f1 => enable_f1, |
|
376 | enable_f1 => enable_f1, | |
362 | enable_f2 => enable_f2, |
|
377 | enable_f2 => enable_f2, | |
363 | enable_f3 => enable_f3, |
|
378 | enable_f3 => enable_f3, | |
364 | burst_f0 => burst_f0, |
|
379 | burst_f0 => burst_f0, | |
365 | burst_f1 => burst_f1, |
|
380 | burst_f1 => burst_f1, | |
366 | burst_f2 => burst_f2, |
|
381 | burst_f2 => burst_f2, | |
367 | run => run, |
|
382 | run => run, | |
368 | addr_data_f0 => addr_data_f0, |
|
383 | addr_data_f0 => addr_data_f0, | |
369 | addr_data_f1 => addr_data_f1, |
|
384 | addr_data_f1 => addr_data_f1, | |
370 | addr_data_f2 => addr_data_f2, |
|
385 | addr_data_f2 => addr_data_f2, | |
371 | addr_data_f3 => addr_data_f3, |
|
386 | addr_data_f3 => addr_data_f3, | |
372 | start_date => start_date, |
|
387 | start_date => start_date, | |
373 | --------------------------------------------------------------------------- |
|
388 | --------------------------------------------------------------------------- | |
374 | debug_reg0 => debug_reg0, |
|
389 | debug_reg0 => debug_reg0, | |
375 | debug_reg1 => debug_reg1, |
|
390 | debug_reg1 => debug_reg1, | |
376 | debug_reg2 => debug_reg2, |
|
391 | debug_reg2 => debug_reg2, | |
377 | debug_reg3 => debug_reg3, |
|
392 | debug_reg3 => debug_reg3, | |
378 | debug_reg4 => debug_reg4, |
|
393 | debug_reg4 => debug_reg4, | |
379 | debug_reg5 => debug_reg5, |
|
394 | debug_reg5 => debug_reg5, | |
380 | debug_reg6 => debug_reg6, |
|
395 | debug_reg6 => debug_reg6, | |
381 | debug_reg7 => debug_reg7); |
|
396 | debug_reg7 => debug_reg7); | |
382 |
|
397 | |||
383 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
398 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
384 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
399 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
385 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
400 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
386 | ----------------------------------------------------------------------------- |
|
401 | ----------------------------------------------------------------------------- | |
387 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
402 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
388 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
403 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
389 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
404 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
390 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
405 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
391 |
|
406 | |||
392 |
|
407 | |||
393 | ----------------------------------------------------------------------------- |
|
408 | ----------------------------------------------------------------------------- | |
394 | lpp_waveform_1 : lpp_waveform |
|
409 | lpp_waveform_1 : lpp_waveform | |
395 | GENERIC MAP ( |
|
410 | GENERIC MAP ( | |
396 | tech => inferred, |
|
411 | tech => inferred, | |
397 | data_size => 6*16, |
|
412 | data_size => 6*16, | |
398 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
413 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
399 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
414 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
400 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
415 | nb_snapshot_param_size => nb_snapshot_param_size, | |
401 | delta_vector_size => delta_vector_size, |
|
416 | delta_vector_size => delta_vector_size, | |
402 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
417 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
403 | ) |
|
418 | ) | |
404 | PORT MAP ( |
|
419 | PORT MAP ( | |
405 | clk => clk, |
|
420 | clk => clk, | |
406 | rstn => rstn, |
|
421 | rstn => rstn, | |
407 |
|
422 | |||
408 | reg_run => run, |
|
423 | reg_run => run, | |
409 | reg_start_date => start_date, |
|
424 | reg_start_date => start_date, | |
410 | reg_delta_snapshot => delta_snapshot, |
|
425 | reg_delta_snapshot => delta_snapshot, | |
411 | reg_delta_f0 => delta_f0, |
|
426 | reg_delta_f0 => delta_f0, | |
412 | reg_delta_f0_2 => delta_f0_2, |
|
427 | reg_delta_f0_2 => delta_f0_2, | |
413 | reg_delta_f1 => delta_f1, |
|
428 | reg_delta_f1 => delta_f1, | |
414 | reg_delta_f2 => delta_f2, |
|
429 | reg_delta_f2 => delta_f2, | |
415 |
|
430 | |||
416 | enable_f0 => enable_f0, |
|
431 | enable_f0 => enable_f0, | |
417 | enable_f1 => enable_f1, |
|
432 | enable_f1 => enable_f1, | |
418 | enable_f2 => enable_f2, |
|
433 | enable_f2 => enable_f2, | |
419 | enable_f3 => enable_f3, |
|
434 | enable_f3 => enable_f3, | |
420 | burst_f0 => burst_f0, |
|
435 | burst_f0 => burst_f0, | |
421 | burst_f1 => burst_f1, |
|
436 | burst_f1 => burst_f1, | |
422 | burst_f2 => burst_f2, |
|
437 | burst_f2 => burst_f2, | |
423 |
|
438 | |||
424 | nb_data_by_buffer => nb_data_by_buffer, |
|
439 | nb_data_by_buffer => nb_data_by_buffer, | |
425 | nb_word_by_buffer => nb_word_by_buffer, |
|
440 | nb_word_by_buffer => nb_word_by_buffer, | |
426 | nb_snapshot_param => nb_snapshot_param, |
|
441 | nb_snapshot_param => nb_snapshot_param, | |
427 | status_full => status_full, |
|
442 | status_full => status_full, | |
428 | status_full_ack => status_full_ack, |
|
443 | status_full_ack => status_full_ack, | |
429 | status_full_err => status_full_err, |
|
444 | status_full_err => status_full_err, | |
430 | status_new_err => status_new_err, |
|
445 | status_new_err => status_new_err, | |
431 |
|
446 | |||
432 | coarse_time => coarse_time, |
|
447 | coarse_time => coarse_time, | |
433 | fine_time => fine_time, |
|
448 | fine_time => fine_time, | |
434 |
|
449 | |||
435 | --f0 |
|
450 | --f0 | |
436 | addr_data_f0 => addr_data_f0, |
|
451 | addr_data_f0 => addr_data_f0, | |
437 | data_f0_in_valid => sample_f0_val, |
|
452 | data_f0_in_valid => sample_f0_val, | |
438 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
453 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
439 | --f1 |
|
454 | --f1 | |
440 | addr_data_f1 => addr_data_f1, |
|
455 | addr_data_f1 => addr_data_f1, | |
441 | data_f1_in_valid => sample_f1_val, |
|
456 | data_f1_in_valid => sample_f1_val, | |
442 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
457 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
443 | --f2 |
|
458 | --f2 | |
444 | addr_data_f2 => addr_data_f2, |
|
459 | addr_data_f2 => addr_data_f2, | |
445 | data_f2_in_valid => sample_f2_val, |
|
460 | data_f2_in_valid => sample_f2_val, | |
446 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
461 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
447 | --f3 |
|
462 | --f3 | |
448 | addr_data_f3 => addr_data_f3, |
|
463 | addr_data_f3 => addr_data_f3, | |
449 | data_f3_in_valid => sample_f3_val, |
|
464 | data_f3_in_valid => sample_f3_val, | |
450 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
465 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
451 | -- OUTPUT -- DMA interface |
|
466 | -- OUTPUT -- DMA interface | |
452 | --f0 |
|
467 | --f0 | |
453 | data_f0_addr_out => data_f0_addr_out_s, |
|
468 | data_f0_addr_out => data_f0_addr_out_s, | |
454 | data_f0_data_out => data_f0_data_out, |
|
469 | data_f0_data_out => data_f0_data_out, | |
455 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
470 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
456 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
471 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
457 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
472 | data_f0_data_out_ren => data_f0_data_out_ren, | |
458 | --f1 |
|
473 | --f1 | |
459 | data_f1_addr_out => data_f1_addr_out_s, |
|
474 | data_f1_addr_out => data_f1_addr_out_s, | |
460 | data_f1_data_out => data_f1_data_out, |
|
475 | data_f1_data_out => data_f1_data_out, | |
461 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
476 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
462 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
477 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
463 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
478 | data_f1_data_out_ren => data_f1_data_out_ren, | |
464 | --f2 |
|
479 | --f2 | |
465 | data_f2_addr_out => data_f2_addr_out_s, |
|
480 | data_f2_addr_out => data_f2_addr_out_s, | |
466 | data_f2_data_out => data_f2_data_out, |
|
481 | data_f2_data_out => data_f2_data_out, | |
467 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
482 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
468 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
483 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
469 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
484 | data_f2_data_out_ren => data_f2_data_out_ren, | |
470 | --f3 |
|
485 | --f3 | |
471 | data_f3_addr_out => data_f3_addr_out_s, |
|
486 | data_f3_addr_out => data_f3_addr_out_s, | |
472 | data_f3_data_out => data_f3_data_out, |
|
487 | data_f3_data_out => data_f3_data_out, | |
473 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
488 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
474 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
489 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
475 | data_f3_data_out_ren => data_f3_data_out_ren, |
|
490 | data_f3_data_out_ren => data_f3_data_out_ren --, | |
476 |
|
491 | |||
477 | -- debug SNAPSHOT_OUT |
|
492 | ---- debug SNAPSHOT_OUT | |
478 | debug_f0_data => debug_f0_data, |
|
493 | --debug_f0_data => debug_f0_data, | |
479 | debug_f0_data_valid => debug_f0_data_valid , |
|
494 | --debug_f0_data_valid => debug_f0_data_valid , | |
480 | debug_f1_data => debug_f1_data , |
|
495 | --debug_f1_data => debug_f1_data , | |
481 | debug_f1_data_valid => debug_f1_data_valid, |
|
496 | --debug_f1_data_valid => debug_f1_data_valid, | |
482 | debug_f2_data => debug_f2_data , |
|
497 | --debug_f2_data => debug_f2_data , | |
483 | debug_f2_data_valid => debug_f2_data_valid , |
|
498 | --debug_f2_data_valid => debug_f2_data_valid , | |
484 | debug_f3_data => debug_f3_data , |
|
499 | --debug_f3_data => debug_f3_data , | |
485 | debug_f3_data_valid => debug_f3_data_valid, |
|
500 | --debug_f3_data_valid => debug_f3_data_valid, | |
486 |
|
501 | |||
487 | -- debug FIFO_IN |
|
502 | ---- debug FIFO_IN | |
488 | debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
|
503 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , | |
489 | debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
|
504 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, | |
490 | debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
|
505 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , | |
491 | debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
|
506 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, | |
492 | debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
|
507 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , | |
493 | debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
|
508 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, | |
494 | debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
|
509 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , | |
495 | debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
|
510 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid | |
496 |
|
511 | |||
497 | ); |
|
512 | ); | |
498 |
|
513 | |||
499 |
|
514 | |||
500 | ----------------------------------------------------------------------------- |
|
515 | ----------------------------------------------------------------------------- | |
501 | -- DEBUG -- WFP OUT |
|
516 | -- DEBUG -- WFP OUT | |
502 | debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
|
517 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; | |
503 | debug_f0_data_fifo_out <= data_f0_data_out; |
|
518 | --debug_f0_data_fifo_out <= data_f0_data_out; | |
504 | debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
|
519 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; | |
505 | debug_f1_data_fifo_out <= data_f1_data_out; |
|
520 | --debug_f1_data_fifo_out <= data_f1_data_out; | |
506 | debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
|
521 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; | |
507 | debug_f2_data_fifo_out <= data_f2_data_out; |
|
522 | --debug_f2_data_fifo_out <= data_f2_data_out; | |
508 | debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
|
523 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; | |
509 | debug_f3_data_fifo_out <= data_f3_data_out; |
|
524 | --debug_f3_data_fifo_out <= data_f3_data_out; | |
510 | ----------------------------------------------------------------------------- |
|
525 | ----------------------------------------------------------------------------- | |
511 |
|
526 | |||
512 |
|
527 | |||
513 | ----------------------------------------------------------------------------- |
|
528 | ----------------------------------------------------------------------------- | |
514 | -- TEMP |
|
529 | -- TEMP | |
515 | ----------------------------------------------------------------------------- |
|
530 | ----------------------------------------------------------------------------- | |
516 |
|
531 | |||
517 | PROCESS (clk, rstn) |
|
532 | PROCESS (clk, rstn) | |
518 | BEGIN -- PROCESS |
|
533 | BEGIN -- PROCESS | |
519 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
534 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
520 | data_f0_data_out_valid <= '0'; |
|
535 | data_f0_data_out_valid <= '0'; | |
521 | data_f0_data_out_valid_burst <= '0'; |
|
536 | data_f0_data_out_valid_burst <= '0'; | |
522 | data_f1_data_out_valid <= '0'; |
|
537 | data_f1_data_out_valid <= '0'; | |
523 | data_f1_data_out_valid_burst <= '0'; |
|
538 | data_f1_data_out_valid_burst <= '0'; | |
524 | data_f2_data_out_valid <= '0'; |
|
539 | data_f2_data_out_valid <= '0'; | |
525 | data_f2_data_out_valid_burst <= '0'; |
|
540 | data_f2_data_out_valid_burst <= '0'; | |
526 | data_f3_data_out_valid <= '0'; |
|
541 | data_f3_data_out_valid <= '0'; | |
527 | data_f3_data_out_valid_burst <= '0'; |
|
542 | data_f3_data_out_valid_burst <= '0'; | |
528 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
543 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
529 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
544 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
530 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
545 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
531 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
546 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
532 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
547 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
533 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
548 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
534 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
549 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
535 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
550 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
536 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
551 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
537 | END IF; |
|
552 | END IF; | |
538 | END PROCESS; |
|
553 | END PROCESS; | |
539 |
|
554 | |||
540 | data_f0_addr_out <= data_f0_addr_out_s; |
|
555 | data_f0_addr_out <= data_f0_addr_out_s; | |
541 | data_f1_addr_out <= data_f1_addr_out_s; |
|
556 | data_f1_addr_out <= data_f1_addr_out_s; | |
542 | data_f2_addr_out <= data_f2_addr_out_s; |
|
557 | data_f2_addr_out <= data_f2_addr_out_s; | |
543 | data_f3_addr_out <= data_f3_addr_out_s; |
|
558 | data_f3_addr_out <= data_f3_addr_out_s; | |
544 |
|
559 | |||
545 | ----------------------------------------------------------------------------- |
|
560 | ----------------------------------------------------------------------------- | |
546 | -- RoundRobin Selection For DMA |
|
561 | -- RoundRobin Selection For DMA | |
547 | ----------------------------------------------------------------------------- |
|
562 | ----------------------------------------------------------------------------- | |
548 |
|
563 | |||
549 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
564 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
550 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
565 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
551 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
566 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
552 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
567 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
553 |
|
568 | |||
554 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
569 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
555 | PORT MAP ( |
|
570 | PORT MAP ( | |
556 | clk => clk, |
|
571 | clk => clk, | |
557 | rstn => rstn, |
|
572 | rstn => rstn, | |
558 | in_valid => dma_rr_valid, |
|
573 | in_valid => dma_rr_valid, | |
559 | out_grant => dma_rr_grant); |
|
574 | out_grant => dma_rr_grant_s); | |
560 |
|
575 | |||
|
576 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |||
|
577 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |||
|
578 | dma_rr_valid_ms(2) <= '0'; | |||
|
579 | dma_rr_valid_ms(3) <= '0'; | |||
|
580 | ||||
|
581 | RR_Arbiter_4_2 : RR_Arbiter_4 | |||
|
582 | PORT MAP ( | |||
|
583 | clk => clk, | |||
|
584 | rstn => rstn, | |||
|
585 | in_valid => dma_rr_valid_ms, | |||
|
586 | out_grant => dma_rr_grant_ms); | |||
|
587 | ||||
|
588 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |||
|
589 | ||||
561 |
|
|
590 | ||
562 |
|
|
591 | ----------------------------------------------------------------------------- | |
563 | -- in : dma_rr_grant |
|
592 | -- in : dma_rr_grant | |
564 | -- send |
|
593 | -- send | |
565 | -- out : dma_sel |
|
594 | -- out : dma_sel | |
566 | -- dma_valid_burst |
|
595 | -- dma_valid_burst | |
567 | -- dma_sel_valid |
|
596 | -- dma_sel_valid | |
568 | ----------------------------------------------------------------------------- |
|
597 | ----------------------------------------------------------------------------- | |
569 | PROCESS (clk, rstn) |
|
598 | PROCESS (clk, rstn) | |
570 | BEGIN -- PROCESS |
|
599 | BEGIN -- PROCESS | |
571 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
600 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
572 | dma_sel <= (OTHERS => '0'); |
|
601 | dma_sel <= (OTHERS => '0'); | |
573 | dma_send <= '0'; |
|
602 | dma_send <= '0'; | |
574 | dma_valid_burst <= '0'; |
|
603 | dma_valid_burst <= '0'; | |
575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
604 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
576 | IF run = '1' THEN |
|
605 | IF run = '1' THEN | |
577 |
|
|
606 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
578 | IF dma_sel = "0000" OR dma_done = '1' THEN |
|
|||
579 | dma_sel <= dma_rr_grant; |
|
607 | dma_sel <= dma_rr_grant; | |
580 | IF dma_rr_grant(0) = '1' THEN |
|
608 | IF dma_rr_grant(0) = '1' THEN | |
581 | dma_send <= '1'; |
|
609 | dma_send <= '1'; | |
582 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
610 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
583 | dma_sel_valid <= data_f0_data_out_valid; |
|
611 | dma_sel_valid <= data_f0_data_out_valid; | |
584 | ELSIF dma_rr_grant(1) = '1' THEN |
|
612 | ELSIF dma_rr_grant(1) = '1' THEN | |
585 | dma_send <= '1'; |
|
613 | dma_send <= '1'; | |
586 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
614 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
587 | dma_sel_valid <= data_f1_data_out_valid; |
|
615 | dma_sel_valid <= data_f1_data_out_valid; | |
588 | ELSIF dma_rr_grant(2) = '1' THEN |
|
616 | ELSIF dma_rr_grant(2) = '1' THEN | |
589 | dma_send <= '1'; |
|
617 | dma_send <= '1'; | |
590 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
618 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
591 | dma_sel_valid <= data_f2_data_out_valid; |
|
619 | dma_sel_valid <= data_f2_data_out_valid; | |
592 | ELSIF dma_rr_grant(3) = '1' THEN |
|
620 | ELSIF dma_rr_grant(3) = '1' THEN | |
593 | dma_send <= '1'; |
|
621 | dma_send <= '1'; | |
594 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
622 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
595 | dma_sel_valid <= data_f3_data_out_valid; |
|
623 | dma_sel_valid <= data_f3_data_out_valid; | |
|
624 | ELSIF dma_rr_grant(4) = '1' THEN | |||
|
625 | dma_send <= '1'; | |||
|
626 | dma_valid_burst <= data_ms_valid_burst; | |||
|
627 | dma_sel_valid <= data_ms_valid; | |||
|
628 | END IF; | |||
|
629 | ||||
|
630 | IF dma_sel(4) = '1' THEN | |||
|
631 | data_ms_done <= '1'; | |||
596 | END IF; |
|
632 | END IF; | |
597 | ELSE |
|
633 | ELSE | |
598 | dma_sel <= dma_sel; |
|
634 | dma_sel <= dma_sel; | |
599 | dma_send <= '0'; |
|
635 | dma_send <= '0'; | |
600 | END IF; |
|
636 | END IF; | |
601 | ELSE |
|
637 | ELSE | |
602 | dma_sel <= (OTHERS => '0'); |
|
638 | dma_sel <= (OTHERS => '0'); | |
603 | dma_send <= '0'; |
|
639 | dma_send <= '0'; | |
604 | dma_valid_burst <= '0'; |
|
640 | dma_valid_burst <= '0'; | |
605 | END IF; |
|
641 | END IF; | |
606 | END IF; |
|
642 | END IF; | |
607 | END PROCESS; |
|
643 | END PROCESS; | |
608 |
|
644 | |||
609 |
|
645 | |||
610 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
646 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
611 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
647 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
612 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
648 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
613 |
data_f3_addr_out |
|
649 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
|
650 | data_ms_addr; | |||
614 |
|
651 | |||
615 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
652 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
616 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
653 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
617 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
654 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
618 |
data_f3_data_out |
|
655 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
|
656 | data_ms_data; | |||
619 |
|
657 | |||
620 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
658 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
621 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
659 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
622 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
660 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
623 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
661 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
|
662 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |||
624 |
|
663 | |||
625 | dma_data_2 <= dma_data; |
|
664 | dma_data_2 <= dma_data; | |
626 |
|
665 | |||
627 |
|
666 | |||
628 |
|
667 | |||
629 |
|
668 | |||
630 |
|
669 | |||
631 | ----------------------------------------------------------------------------- |
|
670 | ----------------------------------------------------------------------------- | |
632 | -- DEBUG -- DMA IN |
|
671 | -- DEBUG -- DMA IN | |
633 | debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
672 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
634 | debug_f0_data_dma_in <= dma_data; |
|
673 | --debug_f0_data_dma_in <= dma_data; | |
635 | debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
674 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
636 | debug_f1_data_dma_in <= dma_data; |
|
675 | --debug_f1_data_dma_in <= dma_data; | |
637 | debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
676 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
638 | debug_f2_data_dma_in <= dma_data; |
|
677 | --debug_f2_data_dma_in <= dma_data; | |
639 | debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
678 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
640 | debug_f3_data_dma_in <= dma_data; |
|
679 | --debug_f3_data_dma_in <= dma_data; | |
641 | ----------------------------------------------------------------------------- |
|
680 | ----------------------------------------------------------------------------- | |
642 |
|
681 | |||
643 | ----------------------------------------------------------------------------- |
|
682 | ----------------------------------------------------------------------------- | |
644 | -- DMA |
|
683 | -- DMA | |
645 | ----------------------------------------------------------------------------- |
|
684 | ----------------------------------------------------------------------------- | |
646 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
685 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
647 | GENERIC MAP ( |
|
686 | GENERIC MAP ( | |
648 | tech => inferred, |
|
687 | tech => inferred, | |
649 | hindex => hindex) |
|
688 | hindex => hindex) | |
650 | PORT MAP ( |
|
689 | PORT MAP ( | |
651 | HCLK => clk, |
|
690 | HCLK => clk, | |
652 | HRESETn => rstn, |
|
691 | HRESETn => rstn, | |
653 | run => run, |
|
692 | run => run, | |
654 | AHB_Master_In => ahbi, |
|
693 | AHB_Master_In => ahbi, | |
655 | AHB_Master_Out => ahbo, |
|
694 | AHB_Master_Out => ahbo, | |
656 |
|
695 | |||
657 | send => dma_send, |
|
696 | send => dma_send, | |
658 | valid_burst => dma_valid_burst, |
|
697 | valid_burst => dma_valid_burst, | |
659 | done => dma_done, |
|
698 | done => dma_done, | |
660 | ren => dma_ren, |
|
699 | ren => dma_ren, | |
661 | address => dma_address, |
|
700 | address => dma_address, | |
662 | data => dma_data_2); |
|
701 | data => dma_data_2); | |
663 |
|
702 | |||
664 | ----------------------------------------------------------------------------- |
|
703 | ----------------------------------------------------------------------------- | |
665 |
-- Matrix Spectral |
|
704 | -- Matrix Spectral | |
666 | ----------------------------------------------------------------------------- |
|
|||
667 | ----------------------------------------------------------------------------- |
|
705 | ----------------------------------------------------------------------------- | |
668 |
|
|
706 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
669 |
|
|
707 | NOT(sample_f0_val) & NOT(sample_f0_val) ; | |
670 |
|
|
708 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
671 |
|
|
709 | NOT(sample_f1_val) & NOT(sample_f1_val) ; | |
672 |
|
|
710 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
673 |
|
|
711 | NOT(sample_f3_val) & NOT(sample_f3_val) ; | |
674 |
|
712 | |||
675 |
|
|
713 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
676 |
|
|
714 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
677 |
|
|
715 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
678 | ------------------------------------------------------------------------------- |
|
716 | ------------------------------------------------------------------------------- | |
679 |
|
|
717 | lpp_lfr_ms_1: lpp_lfr_ms | |
680 |
|
|
718 | GENERIC MAP ( | |
681 | -- hindex => hindex_ms) |
|
719 | Mem_use => Mem_use ) | |
682 |
|
|
720 | PORT MAP ( | |
683 |
|
|
721 | clk => clk, | |
684 |
|
|
722 | rstn => rstn, | |
685 | -- sample_f0_wen => sample_f0_wen, |
|
723 | ||
686 |
|
|
724 | sample_f0_wen => sample_f0_wen, | |
687 |
|
|
725 | sample_f0_wdata => sample_f0_wdata, | |
688 |
|
|
726 | sample_f1_wen => sample_f1_wen, | |
689 |
|
|
727 | sample_f1_wdata => sample_f1_wdata, | |
690 |
|
|
728 | sample_f3_wen => sample_f3_wen, | |
691 | -- AHB_Master_In => ahbi_ms, |
|
729 | sample_f3_wdata => sample_f3_wdata, | |
692 | -- AHB_Master_Out => ahbo_ms, |
|
|||
693 |
|
730 | |||
694 | -- ready_matrix_f0_0 => ready_matrix_f0_0, |
|
731 | dma_addr => data_ms_addr, -- | |
695 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
732 | dma_data => data_ms_data, -- | |
696 | -- ready_matrix_f1 => ready_matrix_f1, |
|
733 | dma_valid => data_ms_valid, -- | |
697 | -- ready_matrix_f2 => ready_matrix_f2, |
|
734 | dma_valid_burst => data_ms_valid_burst, -- | |
698 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
735 | dma_ren => data_ms_ren, -- | |
699 | -- error_bad_component_error => error_bad_component_error, |
|
736 | dma_done => data_ms_done, -- | |
700 | -- debug_reg => debug_reg, |
|
737 | ||
701 |
|
|
738 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
702 |
|
|
739 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
703 |
|
|
740 | ready_matrix_f1 => ready_matrix_f1, | |
704 |
|
|
741 | ready_matrix_f2 => ready_matrix_f2, | |
705 |
|
|
742 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
706 |
|
|
743 | error_bad_component_error => error_bad_component_error, | |
707 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
744 | debug_reg => debug_reg, | |
708 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
745 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
709 |
|
|
746 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
710 |
|
|
747 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
711 |
|
|
748 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
712 | -- addr_matrix_f2 => addr_matrix_f2); |
|
749 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
750 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
751 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
752 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
753 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
754 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
755 | addr_matrix_f1 => addr_matrix_f1, | |||
|
756 | addr_matrix_f2 => addr_matrix_f2); | |||
713 |
|
757 | |||
714 | END beh; |
|
758 | END beh; |
@@ -1,346 +1,393 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY lpp; |
|
4 | LIBRARY lpp; | |
5 | USE lpp.lpp_amba.ALL; |
|
5 | USE lpp.lpp_amba.ALL; | |
6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
7 | --USE lpp.lpp_uart.ALL; |
|
7 | --USE lpp.lpp_uart.ALL; | |
8 | USE lpp.lpp_matrix.ALL; |
|
8 | USE lpp.lpp_matrix.ALL; | |
9 | --USE lpp.lpp_delay.ALL; |
|
9 | --USE lpp.lpp_delay.ALL; | |
10 | USE lpp.lpp_fft.ALL; |
|
10 | USE lpp.lpp_fft.ALL; | |
11 | USE lpp.fft_components.ALL; |
|
11 | USE lpp.fft_components.ALL; | |
12 | USE lpp.lpp_ad_conv.ALL; |
|
12 | USE lpp.lpp_ad_conv.ALL; | |
13 | USE lpp.iir_filter.ALL; |
|
13 | USE lpp.iir_filter.ALL; | |
14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
15 | USE lpp.Filtercfg.ALL; |
|
15 | USE lpp.Filtercfg.ALL; | |
16 | USE lpp.lpp_demux.ALL; |
|
16 | USE lpp.lpp_demux.ALL; | |
17 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
18 | USE lpp.lpp_dma_pkg.ALL; |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
19 | USE lpp.lpp_Header.ALL; |
|
19 | USE lpp.lpp_Header.ALL; | |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |||
20 |
|
21 | |||
21 | LIBRARY grlib; |
|
22 | LIBRARY grlib; | |
22 | USE grlib.amba.ALL; |
|
23 | USE grlib.amba.ALL; | |
23 | USE grlib.stdlib.ALL; |
|
24 | USE grlib.stdlib.ALL; | |
24 | USE grlib.devices.ALL; |
|
25 | USE grlib.devices.ALL; | |
25 | USE GRLIB.DMA2AHB_Package.ALL; |
|
26 | USE GRLIB.DMA2AHB_Package.ALL; | |
26 |
|
27 | |||
27 |
|
28 | |||
28 | ENTITY lpp_lfr_ms IS |
|
29 | ENTITY lpp_lfr_ms IS | |
29 | GENERIC ( |
|
30 | GENERIC ( | |
30 |
|
|
31 | Mem_use : INTEGER | |
31 | ); |
|
32 | ); | |
32 | PORT ( |
|
33 | PORT ( | |
33 | clk : IN STD_LOGIC; |
|
34 | clk : IN STD_LOGIC; | |
34 | rstn : IN STD_LOGIC; |
|
35 | rstn : IN STD_LOGIC; | |
35 |
|
36 | |||
36 | --------------------------------------------------------------------------- |
|
37 | --------------------------------------------------------------------------- | |
37 | -- DATA INPUT |
|
38 | -- DATA INPUT | |
38 | --------------------------------------------------------------------------- |
|
39 | --------------------------------------------------------------------------- | |
39 | -- |
|
40 | -- | |
40 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
41 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
41 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
42 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
42 | -- |
|
43 | -- | |
43 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
44 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
44 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
45 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
45 | -- |
|
46 | -- | |
46 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
47 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
48 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
48 |
|
49 | |||
49 | --------------------------------------------------------------------------- |
|
50 | --------------------------------------------------------------------------- | |
50 | -- DMA |
|
51 | -- DMA | |
51 | --------------------------------------------------------------------------- |
|
52 | --------------------------------------------------------------------------- | |
52 |
|
53 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
53 | -- AMBA AHB Master Interface |
|
54 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
55 | dma_valid : OUT STD_LOGIC; | |
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
56 | dma_valid_burst : OUT STD_LOGIC; | |
|
57 | dma_ren : IN STD_LOGIC; | |||
|
58 | dma_done : IN STD_LOGIC; | |||
56 |
|
59 | |||
57 | -- Reg out |
|
60 | -- Reg out | |
58 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
61 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
59 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
62 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
60 | ready_matrix_f1 : OUT STD_LOGIC; |
|
63 | ready_matrix_f1 : OUT STD_LOGIC; | |
61 | ready_matrix_f2 : OUT STD_LOGIC; |
|
64 | ready_matrix_f2 : OUT STD_LOGIC; | |
62 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
65 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
63 | error_bad_component_error : OUT STD_LOGIC; |
|
66 | error_bad_component_error : OUT STD_LOGIC; | |
64 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
67 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
65 |
|
68 | |||
66 | -- Reg In |
|
69 | -- Reg In | |
67 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
|
70 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
68 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
|
71 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
69 | status_ready_matrix_f1 :IN STD_LOGIC; |
|
72 | status_ready_matrix_f1 :IN STD_LOGIC; | |
70 | status_ready_matrix_f2 :IN STD_LOGIC; |
|
73 | status_ready_matrix_f2 :IN STD_LOGIC; | |
71 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
|
74 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
72 | status_error_bad_component_error :IN STD_LOGIC; |
|
75 | status_error_bad_component_error :IN STD_LOGIC; | |
73 |
|
76 | |||
74 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
77 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
75 | config_active_interruption_onError : IN STD_LOGIC; |
|
78 | config_active_interruption_onError : IN STD_LOGIC; | |
76 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
79 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
82 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
80 | ); |
|
83 | ); | |
81 | END; |
|
84 | END; | |
82 |
|
85 | |||
83 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
86 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
84 | ----------------------------------------------------------------------------- |
|
87 | ----------------------------------------------------------------------------- | |
85 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
86 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
89 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
87 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
90 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
88 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
91 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
89 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
92 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
90 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
93 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
91 |
|
94 | |||
92 | ----------------------------------------------------------------------------- |
|
95 | ----------------------------------------------------------------------------- | |
93 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); |
|
96 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |
94 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
95 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
98 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
96 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
99 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
97 |
|
100 | |||
98 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
99 | SIGNAL FFT_Load : STD_LOGIC; |
|
102 | SIGNAL FFT_Load : STD_LOGIC; | |
100 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
103 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
101 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
104 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
102 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
105 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
103 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
106 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
104 |
|
107 | |||
105 | ----------------------------------------------------------------------------- |
|
108 | ----------------------------------------------------------------------------- | |
106 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
107 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
|
110 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |
108 |
|
111 | |||
109 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
110 | SIGNAL SM_FlagError : STD_LOGIC; |
|
113 | SIGNAL SM_FlagError : STD_LOGIC; | |
111 | SIGNAL SM_Pong : STD_LOGIC; |
|
114 | -- SIGNAL SM_Pong : STD_LOGIC; | |
112 | SIGNAL SM_Wen : STD_LOGIC; |
|
115 | SIGNAL SM_Wen : STD_LOGIC; | |
113 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
116 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
114 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
117 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
115 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
116 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
119 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
117 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
120 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
118 |
|
121 | |||
119 | ----------------------------------------------------------------------------- |
|
122 | ----------------------------------------------------------------------------- | |
120 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
123 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
121 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
124 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
122 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
125 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
123 |
|
126 | |||
124 | ----------------------------------------------------------------------------- |
|
127 | ----------------------------------------------------------------------------- | |
125 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
128 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
126 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
127 | SIGNAL Head_Empty : STD_LOGIC; |
|
130 | SIGNAL Head_Empty : STD_LOGIC; | |
128 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
131 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
129 | SIGNAL Head_Valid : STD_LOGIC; |
|
132 | SIGNAL Head_Valid : STD_LOGIC; | |
130 | SIGNAL Head_Val : STD_LOGIC; |
|
133 | SIGNAL Head_Val : STD_LOGIC; | |
131 |
|
134 | |||
132 | ----------------------------------------------------------------------------- |
|
135 | ----------------------------------------------------------------------------- | |
133 | SIGNAL DMA_Read : STD_LOGIC; |
|
136 | SIGNAL DMA_Read : STD_LOGIC; | |
134 | SIGNAL DMA_ack : STD_LOGIC; |
|
137 | SIGNAL DMA_ack : STD_LOGIC; | |
135 |
|
138 | |||
136 | BEGIN |
|
139 | BEGIN | |
137 |
|
140 | |||
138 | ----------------------------------------------------------------------------- |
|
141 | ----------------------------------------------------------------------------- | |
139 | Memf0: lppFIFOxN |
|
142 | Memf0: lppFIFOxN | |
140 | GENERIC MAP ( |
|
143 | GENERIC MAP ( | |
141 |
tech => 0, Mem_use => use |
|
144 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
142 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') |
|
145 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
143 | PORT MAP ( |
|
146 | PORT MAP ( | |
144 | rst => rstn, wclk => clk, rclk => clk, |
|
147 | rstn => rstn, wclk => clk, rclk => clk, | |
145 | ReUse => (OTHERS => '0'), |
|
148 | ReUse => (OTHERS => '0'), | |
146 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), |
|
149 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
147 | wdata => sample_f0_wdata, rdata => FifoF0_Data, |
|
150 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
148 | full => OPEN, empty => FifoF0_Empty); |
|
151 | full => OPEN, empty => FifoF0_Empty); | |
149 |
|
152 | |||
150 | Memf1: lppFIFOxN |
|
153 | Memf1: lppFIFOxN | |
151 | GENERIC MAP ( |
|
154 | GENERIC MAP ( | |
152 |
tech => 0, Mem_use => use |
|
155 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
153 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
156 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
154 | PORT MAP ( |
|
157 | PORT MAP ( | |
155 | rst => rstn, wclk => clk, rclk => clk, |
|
158 | rstn => rstn, wclk => clk, rclk => clk, | |
156 | ReUse => (OTHERS => '0'), |
|
159 | ReUse => (OTHERS => '0'), | |
157 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), |
|
160 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
158 | wdata => sample_f1_wdata, rdata => FifoF1_Data, |
|
161 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
159 | full => OPEN, empty => FifoF1_Empty); |
|
162 | full => OPEN, empty => FifoF1_Empty); | |
160 |
|
163 | |||
161 |
|
164 | |||
162 | Memf2: lppFIFOxN |
|
165 | Memf2: lppFIFOxN | |
163 | GENERIC MAP ( |
|
166 | GENERIC MAP ( | |
164 |
tech => 0, Mem_use => use |
|
167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
165 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
166 | PORT MAP ( |
|
169 | PORT MAP ( | |
167 | rst => rstn, wclk => clk, rclk => clk, |
|
170 | rstn => rstn, wclk => clk, rclk => clk, | |
168 | ReUse => (OTHERS => '0'), |
|
171 | ReUse => (OTHERS => '0'), | |
169 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), |
|
172 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
170 | wdata => sample_f3_wdata, rdata => FifoF3_Data, |
|
173 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
171 | full => OPEN, empty => FifoF3_Empty); |
|
174 | full => OPEN, empty => FifoF3_Empty); | |
172 | ----------------------------------------------------------------------------- |
|
175 | ----------------------------------------------------------------------------- | |
173 |
|
176 | |||
174 |
|
177 | |||
175 | ----------------------------------------------------------------------------- |
|
178 | ----------------------------------------------------------------------------- | |
176 | DMUX0 : DEMUX |
|
179 | DMUX0 : DEMUX | |
177 | GENERIC MAP ( |
|
180 | GENERIC MAP ( | |
178 | Data_sz => 16) |
|
181 | Data_sz => 16) | |
179 | PORT MAP ( |
|
182 | PORT MAP ( | |
180 | clk => clk, |
|
183 | clk => clk, | |
181 | rstn => rstn, |
|
184 | rstn => rstn, | |
182 | Read => FFT_Read, |
|
185 | Read => FFT_Read, | |
183 | Load => FFT_Load, |
|
186 | Load => FFT_Load, | |
184 | EmptyF0 => FifoF0_Empty, |
|
187 | EmptyF0 => FifoF0_Empty, | |
185 | EmptyF1 => FifoF1_Empty, |
|
188 | EmptyF1 => FifoF1_Empty, | |
186 | EmptyF2 => FifoF3_Empty, |
|
189 | EmptyF2 => FifoF3_Empty, | |
187 | DataF0 => FifoF0_Data, |
|
190 | DataF0 => FifoF0_Data, | |
188 | DataF1 => FifoF1_Data, |
|
191 | DataF1 => FifoF1_Data, | |
189 | DataF2 => FifoF3_Data, |
|
192 | DataF2 => FifoF3_Data, | |
190 | WorkFreq => DMUX_WorkFreq, |
|
193 | WorkFreq => DMUX_WorkFreq, | |
191 | Read_DEMUX => DMUX_Read, |
|
194 | Read_DEMUX => DMUX_Read, | |
192 | Empty => DMUX_Empty, |
|
195 | Empty => DMUX_Empty, | |
193 | Data => DMUX_Data); |
|
196 | Data => DMUX_Data); | |
194 | ----------------------------------------------------------------------------- |
|
197 | ----------------------------------------------------------------------------- | |
195 |
|
198 | |||
196 |
|
199 | |||
197 | ----------------------------------------------------------------------------- |
|
200 | ----------------------------------------------------------------------------- | |
198 | FFT0: FFT |
|
201 | FFT0: FFT | |
199 | GENERIC MAP ( |
|
202 | GENERIC MAP ( | |
200 | Data_sz => 16, |
|
203 | Data_sz => 16, | |
201 | NbData => 256) |
|
204 | NbData => 256) | |
202 | PORT MAP ( |
|
205 | PORT MAP ( | |
203 | clkm => clk, |
|
206 | clkm => clk, | |
204 | rstn => rstn, |
|
207 | rstn => rstn, | |
205 | FifoIN_Empty => DMUX_Empty, |
|
208 | FifoIN_Empty => DMUX_Empty, | |
206 | FifoIN_Data => DMUX_Data, |
|
209 | FifoIN_Data => DMUX_Data, | |
207 | FifoOUT_Full => FifoINT_Full, |
|
210 | FifoOUT_Full => FifoINT_Full, | |
208 | Load => FFT_Load, |
|
211 | Load => FFT_Load, | |
209 | Read => FFT_Read, |
|
212 | Read => FFT_Read, | |
210 | Write => FFT_Write, |
|
213 | Write => FFT_Write, | |
211 | ReUse => FFT_ReUse, |
|
214 | ReUse => FFT_ReUse, | |
212 | Data => FFT_Data); |
|
215 | Data => FFT_Data); | |
213 | ----------------------------------------------------------------------------- |
|
216 | ----------------------------------------------------------------------------- | |
214 |
|
217 | |||
215 |
|
218 | |||
216 | ----------------------------------------------------------------------------- |
|
219 | ----------------------------------------------------------------------------- | |
217 | MemInt : lppFIFOxN |
|
220 | MemInt : lppFIFOxN | |
218 | GENERIC MAP ( |
|
221 | GENERIC MAP ( | |
219 | tech => 0, |
|
222 | tech => 0, | |
220 |
Mem_use => use |
|
223 | Mem_use => Mem_use, | |
221 | Data_sz => 16, |
|
224 | Data_sz => 16, | |
222 | Addr_sz => 8, |
|
225 | Addr_sz => 8, | |
223 | FifoCnt => 5, |
|
226 | FifoCnt => 5, | |
224 | Enable_ReUse => '1') |
|
227 | Enable_ReUse => '1') | |
225 | PORT MAP ( |
|
228 | PORT MAP ( | |
226 | rst => rstn, |
|
229 | rstn => rstn, | |
227 | wclk => clk, |
|
230 | wclk => clk, | |
228 | rclk => clk, |
|
231 | rclk => clk, | |
229 | ReUse => SM_ReUse, |
|
232 | ReUse => SM_ReUse, | |
230 | wen => FFT_Write, |
|
233 | wen => FFT_Write, | |
231 | ren => SM_Read, |
|
234 | ren => SM_Read, | |
232 | wdata => FFT_Data, |
|
235 | wdata => FFT_Data, | |
233 | rdata => FifoINT_Data, |
|
236 | rdata => FifoINT_Data, | |
234 | full => FifoINT_Full, |
|
237 | full => FifoINT_Full, | |
235 | empty => OPEN); |
|
238 | empty => OPEN); | |
236 | ----------------------------------------------------------------------------- |
|
239 | ----------------------------------------------------------------------------- | |
237 |
|
240 | |||
238 | ----------------------------------------------------------------------------- |
|
241 | ----------------------------------------------------------------------------- | |
239 | SM0 : MatriceSpectrale |
|
242 | SM0 : MatriceSpectrale | |
240 | GENERIC MAP ( |
|
243 | GENERIC MAP ( | |
241 | Input_SZ => 16, |
|
244 | Input_SZ => 16, | |
242 | Result_SZ => 32) |
|
245 | Result_SZ => 32) | |
243 | PORT MAP ( |
|
246 | PORT MAP ( | |
244 | clkm => clk, |
|
247 | clkm => clk, | |
245 | rstn => rstn, |
|
248 | rstn => rstn, | |
246 | FifoIN_Full => FifoINT_Full, |
|
249 | FifoIN_Full => FifoINT_Full, | |
247 | SetReUse => FFT_ReUse, |
|
250 | SetReUse => FFT_ReUse, | |
248 | Valid => Head_Valid, |
|
251 | Valid => Head_Valid, | |
249 | Data_IN => FifoINT_Data, |
|
252 | Data_IN => FifoINT_Data, | |
250 |
AC |
|
253 | ACK => DMA_ack, | |
251 | SM_Write => SM_Wen, |
|
254 | SM_Write => SM_Wen, | |
252 | FlagError => SM_FlagError, |
|
255 | FlagError => SM_FlagError, | |
253 | Pong => SM_Pong, |
|
256 | -- Pong => SM_Pong, | |
254 | Statu => SM_Param, |
|
257 | Statu => SM_Param, | |
255 | Write => SM_Write, |
|
258 | Write => SM_Write, | |
256 | Read => SM_Read, |
|
259 | Read => SM_Read, | |
257 | ReUse => SM_ReUse, |
|
260 | ReUse => SM_ReUse, | |
258 | Data_OUT => SM_Data); |
|
261 | Data_OUT => SM_Data); | |
259 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
260 |
|
263 | |||
261 | ----------------------------------------------------------------------------- |
|
264 | ----------------------------------------------------------------------------- | |
262 | MemOut : lppFIFOxN |
|
265 | MemOut : lppFIFOxN | |
263 | GENERIC MAP ( |
|
266 | GENERIC MAP ( | |
264 | tech => 0, |
|
267 | tech => 0, | |
265 |
Mem_use => use |
|
268 | Mem_use => Mem_use, | |
266 | Data_sz => 32, |
|
269 | Data_sz => 32, | |
267 | Addr_sz => 8, |
|
270 | Addr_sz => 8, | |
268 | FifoCnt => 2, |
|
271 | FifoCnt => 2, | |
269 | Enable_ReUse => '0') |
|
272 | Enable_ReUse => '0') | |
270 | PORT MAP ( |
|
273 | PORT MAP ( | |
271 | rst => rstn, |
|
274 | rstn => rstn, | |
272 | wclk => clk, |
|
275 | wclk => clk, | |
273 | rclk => clk, |
|
276 | rclk => clk, | |
274 | ReUse => (OTHERS => '0'), |
|
277 | ReUse => (OTHERS => '0'), | |
275 | wen => SM_Write, |
|
278 | wen => SM_Write, | |
276 | ren => Head_Read, |
|
279 | ren => Head_Read, | |
277 | wdata => SM_Data, |
|
280 | wdata => SM_Data, | |
278 | rdata => FifoOUT_Data, |
|
281 | rdata => FifoOUT_Data, | |
279 | full => FifoOUT_Full, |
|
282 | full => FifoOUT_Full, | |
280 | empty => FifoOUT_Empty); |
|
283 | empty => FifoOUT_Empty); | |
281 | ----------------------------------------------------------------------------- |
|
284 | ----------------------------------------------------------------------------- | |
282 |
|
285 | |||
283 | ----------------------------------------------------------------------------- |
|
286 | ----------------------------------------------------------------------------- | |
284 | Head0 : HeaderBuilder |
|
287 | Head0 : HeaderBuilder | |
285 | GENERIC MAP ( |
|
288 | GENERIC MAP ( | |
286 | Data_sz => 32) |
|
289 | Data_sz => 32) | |
287 | PORT MAP ( |
|
290 | PORT MAP ( | |
288 | clkm => clk, |
|
291 | clkm => clk, | |
289 | rstn => rstn, |
|
292 | rstn => rstn, | |
290 | pong => SM_Pong, |
|
293 | -- pong => SM_Pong, | |
291 | Statu => SM_Param, |
|
294 | Statu => SM_Param, | |
292 | Matrix_Type => DMUX_WorkFreq, |
|
295 | Matrix_Type => DMUX_WorkFreq, | |
293 | Matrix_Write => SM_Wen, |
|
296 | Matrix_Write => SM_Wen, | |
294 | Valid => Head_Valid, |
|
297 | Valid => Head_Valid, | |
295 | dataIN => FifoOUT_Data, |
|
298 | dataIN => FifoOUT_Data, | |
296 | emptyIN => FifoOUT_Empty, |
|
299 | emptyIN => FifoOUT_Empty, | |
297 | RenOUT => Head_Read, |
|
300 | RenOUT => Head_Read, | |
298 | dataOUT => Head_Data, |
|
301 | dataOUT => Head_Data, | |
299 | emptyOUT => Head_Empty, |
|
302 | emptyOUT => Head_Empty, | |
300 | RenIN => DMA_Read, |
|
303 | RenIN => DMA_Read, | |
301 | header => Head_Header, |
|
304 | header => Head_Header, | |
302 |
header_val => |
|
305 | header_val => Head_Val, | |
303 | header_ack => DMA_ack ); |
|
306 | header_ack => DMA_ack ); | |
304 | ----------------------------------------------------------------------------- |
|
307 | ----------------------------------------------------------------------------- | |
305 |
|
308 | |||
306 | ----------------------------------------------------------------------------- |
|
309 | ||
307 |
lpp_dma |
|
310 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
308 | GENERIC MAP ( |
|
|||
309 | tech => 0, |
|
|||
310 | hindex => hindex) |
|
|||
311 | PORT MAP ( |
|
311 | PORT MAP ( | |
312 | HCLK => clk, |
|
312 | HCLK => clk, | |
313 | HRESETn => rstn, |
|
313 | HRESETn => rstn, | |
314 | AHB_Master_In => AHB_Master_In, |
|
|||
315 | AHB_Master_Out => AHB_Master_Out, |
|
|||
316 |
|
314 | |||
317 | fifo_data => Head_Data, |
|
315 | fifo_data => Head_Data, | |
318 | fifo_empty => Head_Empty, |
|
316 | fifo_empty => Head_Empty, | |
319 | fifo_ren => DMA_Read, |
|
317 | fifo_ren => DMA_Read, | |
320 |
|
318 | |||
321 | header => Head_Header, |
|
319 | header => Head_Header, | |
322 |
|
|
320 | header_val => Head_Val, | |
323 |
|
|
321 | header_ack => DMA_ack, | |
|
322 | ||||
|
323 | dma_addr => dma_addr, | |||
|
324 | dma_data => dma_data, | |||
|
325 | dma_valid => dma_valid, | |||
|
326 | dma_valid_burst => dma_valid_burst, | |||
|
327 | dma_ren => dma_ren, | |||
|
328 | dma_done => dma_done, | |||
324 |
|
329 | |||
325 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
330 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
326 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
331 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
327 | ready_matrix_f1 => ready_matrix_f1, |
|
332 | ready_matrix_f1 => ready_matrix_f1, | |
328 | ready_matrix_f2 => ready_matrix_f2, |
|
333 | ready_matrix_f2 => ready_matrix_f2, | |
329 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
334 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
330 | error_bad_component_error => error_bad_component_error, |
|
335 | error_bad_component_error => error_bad_component_error, | |
331 | debug_reg => debug_reg, |
|
336 | debug_reg => debug_reg, | |
332 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
337 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
333 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
338 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
334 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
339 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
335 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
340 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
336 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
341 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
337 | status_error_bad_component_error => status_error_bad_component_error, |
|
342 | status_error_bad_component_error => status_error_bad_component_error, | |
338 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
343 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
339 | config_active_interruption_onError => config_active_interruption_onError, |
|
344 | config_active_interruption_onError => config_active_interruption_onError, | |
340 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
345 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
341 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
346 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
342 | addr_matrix_f1 => addr_matrix_f1, |
|
347 | addr_matrix_f1 => addr_matrix_f1, | |
343 | addr_matrix_f2 => addr_matrix_f2); |
|
348 | addr_matrix_f2 => addr_matrix_f2); | |
344 | ----------------------------------------------------------------------------- |
|
349 | ||
|
350 | ||||
345 |
|
|
351 | ||
346 | END Behavioral; No newline at end of file |
|
352 | ||
|
353 | ----------------------------------------------------------------------------- | |||
|
354 | --lpp_dma_ip_1: lpp_dma_ip | |||
|
355 | -- GENERIC MAP ( | |||
|
356 | -- tech => 0, | |||
|
357 | -- hindex => hindex) | |||
|
358 | -- PORT MAP ( | |||
|
359 | -- HCLK => clk, | |||
|
360 | -- HRESETn => rstn, | |||
|
361 | -- AHB_Master_In => AHB_Master_In, | |||
|
362 | -- AHB_Master_Out => AHB_Master_Out, | |||
|
363 | ||||
|
364 | -- fifo_data => Head_Data, | |||
|
365 | -- fifo_empty => Head_Empty, | |||
|
366 | -- fifo_ren => DMA_Read, | |||
|
367 | ||||
|
368 | -- header => Head_Header, | |||
|
369 | -- header_val => Head_Val, | |||
|
370 | -- header_ack => DMA_ack, | |||
|
371 | ||||
|
372 | -- ready_matrix_f0_0 => ready_matrix_f0_0, | |||
|
373 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
374 | -- ready_matrix_f1 => ready_matrix_f1, | |||
|
375 | -- ready_matrix_f2 => ready_matrix_f2, | |||
|
376 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
|
377 | -- error_bad_component_error => error_bad_component_error, | |||
|
378 | -- debug_reg => debug_reg, | |||
|
379 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
|
380 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
|
381 | -- status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
382 | -- status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
383 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
|
384 | -- status_error_bad_component_error => status_error_bad_component_error, | |||
|
385 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
386 | -- config_active_interruption_onError => config_active_interruption_onError, | |||
|
387 | -- addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
388 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
389 | -- addr_matrix_f1 => addr_matrix_f1, | |||
|
390 | -- addr_matrix_f2 => addr_matrix_f2); | |||
|
391 | ------------------------------------------------------------------------------- | |||
|
392 | ||||
|
393 | END Behavioral; |
@@ -1,252 +1,257 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
16 |
|
16 | |||
17 | COMPONENT lpp_lfr_ms |
|
17 | COMPONENT lpp_lfr_ms | |
18 | GENERIC ( |
|
18 | GENERIC ( | |
19 |
|
|
19 | Mem_use : INTEGER | |
|
20 | ); | |||
20 | PORT ( |
|
21 | PORT ( | |
21 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
22 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
23 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
24 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
24 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
25 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
25 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
26 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
26 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
27 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
27 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
28 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
28 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
29 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
29 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
30 | ||
30 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
31 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
32 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
33 | dma_valid : OUT STD_LOGIC; | |||
|
34 | dma_valid_burst : OUT STD_LOGIC; | |||
|
35 | dma_ren : IN STD_LOGIC; | |||
|
36 | dma_done : IN STD_LOGIC; | |||
|
37 | ||||
31 |
|
|
38 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
32 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
39 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
33 | ready_matrix_f1 : OUT STD_LOGIC; |
|
40 | ready_matrix_f1 : OUT STD_LOGIC; | |
34 | ready_matrix_f2 : OUT STD_LOGIC; |
|
41 | ready_matrix_f2 : OUT STD_LOGIC; | |
35 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
42 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
36 | error_bad_component_error : OUT STD_LOGIC; |
|
43 | error_bad_component_error : OUT STD_LOGIC; | |
37 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
44 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
38 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
45 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |
39 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
46 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |
40 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
47 | status_ready_matrix_f1 : IN STD_LOGIC; | |
41 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
48 | status_ready_matrix_f2 : IN STD_LOGIC; | |
42 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
49 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
43 | status_error_bad_component_error : IN STD_LOGIC; |
|
50 | status_error_bad_component_error : IN STD_LOGIC; | |
44 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
51 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
45 | config_active_interruption_onError : IN STD_LOGIC; |
|
52 | config_active_interruption_onError : IN STD_LOGIC; | |
46 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
53 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
47 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
54 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
48 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
55 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
49 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
56 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
50 | END COMPONENT; |
|
57 | END COMPONENT; | |
51 |
|
58 | |||
|
59 | COMPONENT lpp_lfr_ms_fsmdma | |||
|
60 | PORT ( | |||
|
61 | HCLK : IN STD_ULOGIC; | |||
|
62 | HRESETn : IN STD_ULOGIC; | |||
|
63 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
64 | fifo_empty : IN STD_LOGIC; | |||
|
65 | fifo_ren : OUT STD_LOGIC; | |||
|
66 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
67 | header_val : IN STD_LOGIC; | |||
|
68 | header_ack : OUT STD_LOGIC; | |||
|
69 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
70 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
71 | dma_valid : OUT STD_LOGIC; | |||
|
72 | dma_valid_burst : OUT STD_LOGIC; | |||
|
73 | dma_ren : IN STD_LOGIC; | |||
|
74 | dma_done : IN STD_LOGIC; | |||
|
75 | ready_matrix_f0_0 : OUT STD_LOGIC; | |||
|
76 | ready_matrix_f0_1 : OUT STD_LOGIC; | |||
|
77 | ready_matrix_f1 : OUT STD_LOGIC; | |||
|
78 | ready_matrix_f2 : OUT STD_LOGIC; | |||
|
79 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
|
80 | error_bad_component_error : OUT STD_LOGIC; | |||
|
81 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
82 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |||
|
83 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |||
|
84 | status_ready_matrix_f1 : IN STD_LOGIC; | |||
|
85 | status_ready_matrix_f2 : IN STD_LOGIC; | |||
|
86 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |||
|
87 | status_error_bad_component_error : IN STD_LOGIC; | |||
|
88 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |||
|
89 | config_active_interruption_onError : IN STD_LOGIC; | |||
|
90 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
91 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
92 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
93 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
94 | END COMPONENT; | |||
|
95 | ||||
|
96 | ||||
52 |
|
|
97 | COMPONENT lpp_lfr_filter | |
53 | GENERIC ( |
|
98 | GENERIC ( | |
54 | Mem_use : INTEGER); |
|
99 | Mem_use : INTEGER); | |
55 | PORT ( |
|
100 | PORT ( | |
56 | sample : IN Samples(7 DOWNTO 0); |
|
101 | sample : IN Samples(7 DOWNTO 0); | |
57 | sample_val : IN STD_LOGIC; |
|
102 | sample_val : IN STD_LOGIC; | |
58 | clk : IN STD_LOGIC; |
|
103 | clk : IN STD_LOGIC; | |
59 | rstn : IN STD_LOGIC; |
|
104 | rstn : IN STD_LOGIC; | |
60 | data_shaping_SP0 : IN STD_LOGIC; |
|
105 | data_shaping_SP0 : IN STD_LOGIC; | |
61 | data_shaping_SP1 : IN STD_LOGIC; |
|
106 | data_shaping_SP1 : IN STD_LOGIC; | |
62 | data_shaping_R0 : IN STD_LOGIC; |
|
107 | data_shaping_R0 : IN STD_LOGIC; | |
63 | data_shaping_R1 : IN STD_LOGIC; |
|
108 | data_shaping_R1 : IN STD_LOGIC; | |
64 | sample_f0_val : OUT STD_LOGIC; |
|
109 | sample_f0_val : OUT STD_LOGIC; | |
65 | sample_f1_val : OUT STD_LOGIC; |
|
110 | sample_f1_val : OUT STD_LOGIC; | |
66 | sample_f2_val : OUT STD_LOGIC; |
|
111 | sample_f2_val : OUT STD_LOGIC; | |
67 | sample_f3_val : OUT STD_LOGIC; |
|
112 | sample_f3_val : OUT STD_LOGIC; | |
68 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
113 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
69 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
114 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
70 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
115 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
71 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
116 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
72 | END COMPONENT; |
|
117 | END COMPONENT; | |
73 |
|
118 | |||
74 | COMPONENT lpp_lfr |
|
119 | COMPONENT lpp_lfr | |
75 | GENERIC ( |
|
120 | GENERIC ( | |
76 | Mem_use : INTEGER; |
|
121 | Mem_use : INTEGER; | |
77 | nb_data_by_buffer_size : INTEGER; |
|
122 | nb_data_by_buffer_size : INTEGER; | |
78 | nb_word_by_buffer_size : INTEGER; |
|
123 | nb_word_by_buffer_size : INTEGER; | |
79 | nb_snapshot_param_size : INTEGER; |
|
124 | nb_snapshot_param_size : INTEGER; | |
80 | delta_vector_size : INTEGER; |
|
125 | delta_vector_size : INTEGER; | |
81 | delta_vector_size_f0_2 : INTEGER; |
|
126 | delta_vector_size_f0_2 : INTEGER; | |
82 | pindex : INTEGER; |
|
127 | pindex : INTEGER; | |
83 | paddr : INTEGER; |
|
128 | paddr : INTEGER; | |
84 | pmask : INTEGER; |
|
129 | pmask : INTEGER; | |
85 | pirq_ms : INTEGER; |
|
130 | pirq_ms : INTEGER; | |
86 | pirq_wfp : INTEGER; |
|
131 | pirq_wfp : INTEGER; | |
87 | hindex : INTEGER; |
|
132 | hindex : INTEGER; | |
88 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
133 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
89 | ); |
|
134 | ); | |
90 | PORT ( |
|
135 | PORT ( | |
91 | clk : IN STD_LOGIC; |
|
136 | clk : IN STD_LOGIC; | |
92 | rstn : IN STD_LOGIC; |
|
137 | rstn : IN STD_LOGIC; | |
93 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
138 | sample_B : IN Samples14v(2 DOWNTO 0); | |
94 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
139 | sample_E : IN Samples14v(4 DOWNTO 0); | |
95 | sample_val : IN STD_LOGIC; |
|
140 | sample_val : IN STD_LOGIC; | |
96 | apbi : IN apb_slv_in_type; |
|
141 | apbi : IN apb_slv_in_type; | |
97 | apbo : OUT apb_slv_out_type; |
|
142 | apbo : OUT apb_slv_out_type; | |
98 | ahbi : IN AHB_Mst_In_Type; |
|
143 | ahbi : IN AHB_Mst_In_Type; | |
99 | ahbo : OUT AHB_Mst_Out_Type; |
|
144 | ahbo : OUT AHB_Mst_Out_Type; | |
100 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
145 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
101 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
146 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
102 |
data_shaping_BW : OUT STD_LOGIC |
|
147 | data_shaping_BW : OUT STD_LOGIC | |
103 |
|
||||
104 | --debug |
|
|||
105 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|||
106 | debug_f0_data_valid : OUT STD_LOGIC; |
|
|||
107 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|||
108 | debug_f1_data_valid : OUT STD_LOGIC; |
|
|||
109 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|||
110 | debug_f2_data_valid : OUT STD_LOGIC; |
|
|||
111 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|||
112 | debug_f3_data_valid : OUT STD_LOGIC; |
|
|||
113 |
|
||||
114 | -- debug FIFO_IN |
|
|||
115 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
116 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
117 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
118 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
119 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
120 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
121 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
122 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
|||
123 |
|
||||
124 | --debug FIFO OUT |
|
|||
125 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
126 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
|||
127 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
128 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
|||
129 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
130 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
|||
131 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
132 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
|||
133 |
|
||||
134 | --debug DMA IN |
|
|||
135 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
136 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
|||
137 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
138 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
|||
139 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
140 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
|||
141 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|||
142 | debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
|||
143 | ); |
|
148 | ); | |
144 | END COMPONENT; |
|
149 | END COMPONENT; | |
145 |
|
150 | |||
146 | COMPONENT lpp_lfr_apbreg |
|
151 | COMPONENT lpp_lfr_apbreg | |
147 | GENERIC ( |
|
152 | GENERIC ( | |
148 | nb_data_by_buffer_size : INTEGER; |
|
153 | nb_data_by_buffer_size : INTEGER; | |
149 | nb_word_by_buffer_size : INTEGER; |
|
154 | nb_word_by_buffer_size : INTEGER; | |
150 | nb_snapshot_param_size : INTEGER; |
|
155 | nb_snapshot_param_size : INTEGER; | |
151 | delta_vector_size : INTEGER; |
|
156 | delta_vector_size : INTEGER; | |
152 | delta_vector_size_f0_2 : INTEGER; |
|
157 | delta_vector_size_f0_2 : INTEGER; | |
153 | pindex : INTEGER; |
|
158 | pindex : INTEGER; | |
154 | paddr : INTEGER; |
|
159 | paddr : INTEGER; | |
155 | pmask : INTEGER; |
|
160 | pmask : INTEGER; | |
156 | pirq_ms : INTEGER; |
|
161 | pirq_ms : INTEGER; | |
157 | pirq_wfp : INTEGER; |
|
162 | pirq_wfp : INTEGER; | |
158 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
163 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
159 | PORT ( |
|
164 | PORT ( | |
160 | HCLK : IN STD_ULOGIC; |
|
165 | HCLK : IN STD_ULOGIC; | |
161 | HRESETn : IN STD_ULOGIC; |
|
166 | HRESETn : IN STD_ULOGIC; | |
162 | apbi : IN apb_slv_in_type; |
|
167 | apbi : IN apb_slv_in_type; | |
163 | apbo : OUT apb_slv_out_type; |
|
168 | apbo : OUT apb_slv_out_type; | |
164 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
169 | ready_matrix_f0_0 : IN STD_LOGIC; | |
165 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
170 | ready_matrix_f0_1 : IN STD_LOGIC; | |
166 | ready_matrix_f1 : IN STD_LOGIC; |
|
171 | ready_matrix_f1 : IN STD_LOGIC; | |
167 | ready_matrix_f2 : IN STD_LOGIC; |
|
172 | ready_matrix_f2 : IN STD_LOGIC; | |
168 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
173 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
169 | error_bad_component_error : IN STD_LOGIC; |
|
174 | error_bad_component_error : IN STD_LOGIC; | |
170 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
171 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
176 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
172 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
177 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
173 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
178 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
174 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
179 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
175 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
180 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
176 | status_error_bad_component_error : OUT STD_LOGIC; |
|
181 | status_error_bad_component_error : OUT STD_LOGIC; | |
177 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
182 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
178 | config_active_interruption_onError : OUT STD_LOGIC; |
|
183 | config_active_interruption_onError : OUT STD_LOGIC; | |
179 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
184 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
180 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
181 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
182 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
187 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
183 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
188 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
184 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
189 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
185 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
190 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
186 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
191 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | data_shaping_BW : OUT STD_LOGIC; |
|
192 | data_shaping_BW : OUT STD_LOGIC; | |
188 | data_shaping_SP0 : OUT STD_LOGIC; |
|
193 | data_shaping_SP0 : OUT STD_LOGIC; | |
189 | data_shaping_SP1 : OUT STD_LOGIC; |
|
194 | data_shaping_SP1 : OUT STD_LOGIC; | |
190 | data_shaping_R0 : OUT STD_LOGIC; |
|
195 | data_shaping_R0 : OUT STD_LOGIC; | |
191 | data_shaping_R1 : OUT STD_LOGIC; |
|
196 | data_shaping_R1 : OUT STD_LOGIC; | |
192 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
197 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
193 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
198 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
194 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
199 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
195 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
200 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
196 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
201 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
197 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
202 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
198 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
203 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
199 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
204 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
200 | enable_f0 : OUT STD_LOGIC; |
|
205 | enable_f0 : OUT STD_LOGIC; | |
201 | enable_f1 : OUT STD_LOGIC; |
|
206 | enable_f1 : OUT STD_LOGIC; | |
202 | enable_f2 : OUT STD_LOGIC; |
|
207 | enable_f2 : OUT STD_LOGIC; | |
203 | enable_f3 : OUT STD_LOGIC; |
|
208 | enable_f3 : OUT STD_LOGIC; | |
204 | burst_f0 : OUT STD_LOGIC; |
|
209 | burst_f0 : OUT STD_LOGIC; | |
205 | burst_f1 : OUT STD_LOGIC; |
|
210 | burst_f1 : OUT STD_LOGIC; | |
206 | burst_f2 : OUT STD_LOGIC; |
|
211 | burst_f2 : OUT STD_LOGIC; | |
207 | run : OUT STD_LOGIC; |
|
212 | run : OUT STD_LOGIC; | |
208 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
213 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
209 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
214 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
210 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
215 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
211 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
212 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
217 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
213 | --------------------------------------------------------------------------- |
|
218 | --------------------------------------------------------------------------- | |
214 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
219 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
215 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
216 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
221 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
217 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
222 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
218 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
223 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
219 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
220 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
225 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
221 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
226 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
222 | END COMPONENT; |
|
227 | END COMPONENT; | |
223 |
|
228 | |||
224 | COMPONENT lpp_top_ms |
|
229 | COMPONENT lpp_top_ms | |
225 | GENERIC ( |
|
230 | GENERIC ( | |
226 | Mem_use : INTEGER; |
|
231 | Mem_use : INTEGER; | |
227 | nb_burst_available_size : INTEGER; |
|
232 | nb_burst_available_size : INTEGER; | |
228 | nb_snapshot_param_size : INTEGER; |
|
233 | nb_snapshot_param_size : INTEGER; | |
229 | delta_snapshot_size : INTEGER; |
|
234 | delta_snapshot_size : INTEGER; | |
230 | delta_f2_f0_size : INTEGER; |
|
235 | delta_f2_f0_size : INTEGER; | |
231 | delta_f2_f1_size : INTEGER; |
|
236 | delta_f2_f1_size : INTEGER; | |
232 | pindex : INTEGER; |
|
237 | pindex : INTEGER; | |
233 | paddr : INTEGER; |
|
238 | paddr : INTEGER; | |
234 | pmask : INTEGER; |
|
239 | pmask : INTEGER; | |
235 | pirq_ms : INTEGER; |
|
240 | pirq_ms : INTEGER; | |
236 | pirq_wfp : INTEGER; |
|
241 | pirq_wfp : INTEGER; | |
237 | hindex_wfp : INTEGER; |
|
242 | hindex_wfp : INTEGER; | |
238 | hindex_ms : INTEGER); |
|
243 | hindex_ms : INTEGER); | |
239 | PORT ( |
|
244 | PORT ( | |
240 | clk : IN STD_LOGIC; |
|
245 | clk : IN STD_LOGIC; | |
241 | rstn : IN STD_LOGIC; |
|
246 | rstn : IN STD_LOGIC; | |
242 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
247 | sample_B : IN Samples14v(2 DOWNTO 0); | |
243 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
248 | sample_E : IN Samples14v(4 DOWNTO 0); | |
244 | sample_val : IN STD_LOGIC; |
|
249 | sample_val : IN STD_LOGIC; | |
245 | apbi : IN apb_slv_in_type; |
|
250 | apbi : IN apb_slv_in_type; | |
246 | apbo : OUT apb_slv_out_type; |
|
251 | apbo : OUT apb_slv_out_type; | |
247 | ahbi_ms : IN AHB_Mst_In_Type; |
|
252 | ahbi_ms : IN AHB_Mst_In_Type; | |
248 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
253 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
249 | data_shaping_BW : OUT STD_LOGIC); |
|
254 | data_shaping_BW : OUT STD_LOGIC); | |
250 | END COMPONENT; |
|
255 | END COMPONENT; | |
251 |
|
256 | |||
252 | END lpp_lfr_pkg; |
|
257 | END lpp_lfr_pkg; |
General Comments 0
You need to be logged in to leave comments.
Login now