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(LFR-EM) WFP_MS-1-1-16
pellion -
r377:8f748b61300a (LFR-EM) WFP_MS_1-1-16 JC
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@@ -340,7 +340,7 BEGIN -- beh
340 340 -------------------------------------------------------------------------------
341 341 -- LFR ------------------------------------------------------------------------
342 342 -------------------------------------------------------------------------------
343 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 lpp_lfr_1 : lpp_lfr
344 344 GENERIC MAP (
345 345 Mem_use => use_RAM,
346 346 nb_data_by_buffer_size => 32,
@@ -354,7 +354,7 BEGIN -- beh
354 354 pirq_ms => 6,
355 355 pirq_wfp => 14,
356 356 hindex => 2,
357 top_lfr_version => X"00010B") -- aa.bb.cc version
357 top_lfr_version => X"010110") -- aa.bb.cc version
358 358 -- AA : BOARD NUMBER
359 359 -- 0 => MINI_LFR
360 360 -- 1 => EM
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@@ -426,7 +426,7 BEGIN -- beh
426 426 pirq_ms => 6,
427 427 pirq_wfp => 14,
428 428 hindex => 2,
429 top_lfr_version => X"00010F") -- aa.bb.cc version
429 top_lfr_version => X"000110") -- aa.bb.cc version
430 430 PORT MAP (
431 431 clk => clk_25,
432 432 rstn => reset,
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@@ -113,10 +113,21 ARCHITECTURE beh OF TB IS
113 113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
114 114 -----------------------------------------------------------------------------
115 115 SIGNAL apbi : apb_slv_in_type;
116 SIGNAL apbo : apb_slv_out_type;
116 117 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 118 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 119 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 120 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 --
122 SIGNAL ready_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
123 SIGNAL irq_ongoing : STD_LOGIC;
124 --
125 SIGNAL read_status : STD_LOGIC;
126 SIGNAL read_status_t : STD_LOGIC;
127
128
129 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
130 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
120 131
121 132 BEGIN -- beh
122 133
@@ -262,6 +273,11 BEGIN -- beh
262 273 error_input_fifo_write => error_input_fifo_write,
263 274
264 275 debug_reg => debug_reg,
276
277 --
278 observation_vector_0 => observation_vector_0,
279 observation_vector_1 => observation_vector_1,
280 --
265 281 status_ready_matrix_f0 => status_ready_matrix_f0,
266 282 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
267 283 status_ready_matrix_f1 => status_ready_matrix_f1,
@@ -281,7 +297,7 BEGIN -- beh
281 297
282 298
283 299
284 apbi.psel(4) <= '0';
300
285 301
286 302 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
287 303 GENERIC MAP (
@@ -301,7 +317,7 BEGIN -- beh
301 317 HCLK => clk25MHz,
302 318 HRESETn => rstn,
303 319 apbi => apbi,
304 apbo => OPEN,
320 apbo => apbo,
305 321
306 322 run_ms => OPEN,
307 323
@@ -359,8 +375,40 BEGIN -- beh
359 375
360 376
361 377
378 read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us;
362 379
380 PROCESS (clk25MHz, rstn)
381 BEGIN
382 IF rstn = '0' THEN
383 ready_reg <= (OTHERS => '0');
384 --read_status <= '0';
385 apbi.psel(4) <= '0';
386 apbi.pwrite <= '0';
387 apbi.penable <= '0';
388 apbi.paddr(7 DOWNTO 2) <= (OTHERS => '0');
389 ELSIF clk25MHz'event AND clk25MHz = '1' THEN
390 apbi.psel(4) <= '1';
391 apbi.paddr(7 DOWNTO 2) <= "000001";
392 apbi.penable <= '1';
393 read_status <= apbo.pirq(0);
363 394
395 IF read_status = '1' AND irq_ongoing = '0' THEN
396 ready_reg <= apbo.prdata(5 DOWNTO 0);
397 irq_ongoing <= '1';
398 END IF;
399
400 IF read_status_t = '0' THEN
401 apbi.pwrite <= '0';
402 ELSE
403 irq_ongoing <= '0';
404 apbi.pwrite <= '1';
405 apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0');
406 apbi.pwdata(5 DOWNTO 0) <= ready_reg;
407 ready_reg <= (OTHERS => '0');
408 END IF;
409
410 END IF;
411 END PROCESS;
364 412
365 413
366 414
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@@ -1,5 +1,23
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -expand -group debug -expand /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -expand -group debug -subitemconfig {/tb/lpp_lfr_apbreg_1/apbo.pirq {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -expand -group debug /tb/ready_reg
16 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -divider {New Divider}
3 21 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 22 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 23 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
@@ -192,7 +210,7 add wave -noupdate /tb/lpp_lfr_apbreg_1/
192 210 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
193 211 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
194 212 TreeUpdate [SetDefaultTree]
195 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {30152624373 ps} 0} {{Cursor 3} {10666401890 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {87243365384 ps} 0}
213 WaveRestoreCursors {{Cursor 1} {123239471127 ps} 0}
196 214 configure wave -namecolwidth 486
197 215 configure wave -valuecolwidth 112
198 216 configure wave -justifyvalue left
@@ -207,6 +225,6 configure wave -griddelta 40
207 225 configure wave -timeline 0
208 226 configure wave -timelineunits ps
209 227 update
210 WaveRestoreZoom {0 ps} {105000147 ns}
228 WaveRestoreZoom {124629370639 ps} {125891337681 ps}
211 229 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
212 230 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
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@@ -61,6 +61,10 ENTITY lpp_lfr IS
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63 --
64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
64 68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65 69
66 70 --debug
@@ -284,6 +288,7 ARCHITECTURE beh OF lpp_lfr IS
284 288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
285 289
286 290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
287 292
288 293 BEGIN
289 294
@@ -395,7 +400,8 BEGIN
395 400 addr_data_f1 => addr_data_f1,
396 401 addr_data_f2 => addr_data_f2,
397 402 addr_data_f3 => addr_data_f3,
398 start_date => start_date);
403 start_date => start_date,
404 debug_signal => debug_signal);
399 405
400 406 -----------------------------------------------------------------------------
401 407 -----------------------------------------------------------------------------
@@ -710,6 +716,8 BEGIN
710 716 error_input_fifo_write => error_input_fifo_write,
711 717
712 718 debug_reg => debug_ms,--observation_reg,
719 observation_vector_0 => observation_vector_0,
720 observation_vector_1 => observation_vector_1,
713 721
714 722 status_ready_matrix_f0 => status_ready_matrix_f0,
715 723 status_ready_matrix_f1 => status_ready_matrix_f1,
@@ -725,11 +733,16 BEGIN
725 733 matrix_time_f2 => matrix_time_f2);
726 734
727 735 -----------------------------------------------------------------------------
728 observation_reg(31 DOWNTO 0) <= debug_ms(31-9 DOWNTO 0) &
729 dma_ms_ongoing & -- 8
730 data_ms_done & -- 7
731 dma_done & -- 6
732 dma_sel & -- 5 .. 1
733 ms_softandhard_rstn; -- 0
736
737
738 observation_reg(31 DOWNTO 0) <=
739 dma_sel(4) & -- 31
740 dma_ms_ongoing & -- 30
741 data_ms_done & -- 29
742 dma_done & -- 28
743 ms_softandhard_rstn & --27
744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
734 747
735 748 END beh;
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@@ -127,7 +127,9 ENTITY lpp_lfr_apbreg IS
127 127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 ---------------------------------------------------------------------------
132 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
131 133 ---------------------------------------------------------------------------
132 134 );
133 135
@@ -242,6 +244,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS
242 244 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
243 245 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 246 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 SIGNAL apbo_irq_ms : STD_LOGIC;
248 SIGNAL apbo_irq_wfp : STD_LOGIC;
245 249
246 250 BEGIN -- beh
247 251
@@ -326,7 +330,10 BEGIN -- beh
326 330
327 331 prdata <= (OTHERS => '0');
328 332
329 apbo.pirq <= (OTHERS => '0');
333
334 apbo_irq_ms <= '0';
335 apbo_irq_wfp <= '0';
336
330 337
331 338 status_full_ack <= (OTHERS => '0');
332 339
@@ -502,17 +509,19 BEGIN -- beh
502 509 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
503 510 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
504 511 reg_sp.config_ms_run <= apbi.pwdata(2);
505 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
506 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
507 reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2);
508 reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3);
509 reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4);
510 reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5);
511 reg_sp.status_error_bad_component_error <= apbi.pwdata(6);
512 reg_sp.status_error_buffer_full <= apbi.pwdata(7);
513 reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8);
514 reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9);
515 reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10);
512
513 WHEN "000001" =>
514 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
515 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
516 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
517 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
518 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
519 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
520 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
521 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
522 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
523 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
524 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
516 525 --2
517 526 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
518 527 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
@@ -562,8 +571,8 BEGIN -- beh
562 571 END CASE;
563 572 END IF;
564 573 END IF;
565
566 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
574 --apbo.pirq(pirq_ms) <=
575 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
567 576 ready_matrix_f1 OR
568 577 ready_matrix_f2)
569 578 )
@@ -575,12 +584,15 BEGIN -- beh
575 584 OR error_input_fifo_write(1)
576 585 OR error_input_fifo_write(2))
577 586 ));
578
579 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
587 -- apbo.pirq(pirq_wfp)
588 apbo_irq_wfp<= ored_irq_wfp;
580 589
581 590 END IF;
582 591 END PROCESS lpp_lfr_apbreg;
583 592
593 apbo.pirq(pirq_ms) <= apbo_irq_ms;
594 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
595
584 596 apbo.pindex <= pindex;
585 597 apbo.pconfig <= pconfig;
586 598 apbo.prdata <= prdata;
@@ -671,5 +683,15 BEGIN -- beh
671 683 addr_matrix => addr_matrix_f2,
672 684 matrix_time => matrix_time_f2);
673 685
686 -----------------------------------------------------------------------------
687 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
688 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
689 reg_sp.status_error_input_fifo_write(2) &--10
690 reg_sp.status_error_input_fifo_write(1) &--9
691 reg_sp.status_error_input_fifo_write(0) &--8
692 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
693 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
694 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
695 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
674 696
675 697 END beh;
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@@ -57,6 +57,9 ENTITY lpp_lfr_ms IS
57 57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 58
59 59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
60 63
61 64 -- Reg In
62 65 status_ready_matrix_f0 : IN STD_LOGIC;
@@ -570,6 +573,14 BEGIN
570 573 fft_data_valid => fft_data_valid,
571 574 fft_ready => fft_ready);
572 575
576 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
577 fft_data_valid & --4
578 fft_pong & --3
579 sample_load & --2
580 fft_read & --1
581 sample_valid; --0
582
583
573 584 -----------------------------------------------------------------------------
574 585 PROCESS (clk, rstn)
575 586 BEGIN
@@ -638,6 +649,8 BEGIN
638 649 (fft_data_im & fft_data_re) &
639 650 (fft_data_im & fft_data_re) &
640 651 (fft_data_im & fft_data_re);
652 -----------------------------------------------------------------------------
653
641 654
642 655 -----------------------------------------------------------------------------
643 656 Mem_In_SpectralMatrix : lppFIFOxN
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@@ -234,6 +234,7 BEGIN
234 234 WHEN TRASH_FIFO =>
235 235 debug_reg_s(2 DOWNTO 0) <= "100";
236 236
237 error_buffer_full <= '0';
237 238 error_bad_component_error <= '0';
238 239 IF fifo_empty = '1' THEN
239 240 state <= IDLE;
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@@ -103,6 +103,10 PACKAGE lpp_lfr_pkg IS
103 103 error_buffer_full : OUT STD_LOGIC;
104 104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
105 105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
109 -------------------------------------------------------------------------
106 110 status_ready_matrix_f0 : IN STD_LOGIC;
107 111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
108 112 status_ready_matrix_f1 : IN STD_LOGIC;
@@ -239,6 +243,9 PACKAGE lpp_lfr_pkg IS
239 243 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
240 244 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
241 245 data_shaping_BW : OUT STD_LOGIC;
246 --
247 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
248 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
242 249 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
243 250 );
244 251 END COMPONENT;
@@ -345,7 +352,10 PACKAGE lpp_lfr_pkg IS
345 352 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
346 353 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
347 354 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
348 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
355 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
356
357 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
358
349 359 );
350 360 END COMPONENT;
351 361
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