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Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)
pellion -
r286:8b7f4967459c JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL;
42 42 USE lpp.iir_filter.ALL;
43 43 USE lpp.general_purpose.ALL;
44 44 USE lpp.lpp_lfr_time_management.ALL;
45 45 USE lpp.lpp_leon3_soc_pkg.ALL;
46 46 USE lpp.lpp_debug_lfr_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 121 --
122 SIGNAL errorn : STD_LOGIC;
122 SIGNAL errorn : STD_LOGIC;
123 123 -- UART AHB ---------------------------------------------------------------
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 126
127 127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
131 SIGNAL I00_s : STD_LOGIC;
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
131 SIGNAL I00_s : STD_LOGIC;
132 132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 1;
133 CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
134 134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 1;
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
143 --
144 SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0);
145
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
143
144 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153 -- SIGNAL clkmn : STD_ULOGIC;
154 -- SIGNAL txclk : STD_ULOGIC;
155
156 -- AD Converter RHF1401
157 SIGNAL sample : Samples14v(7 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
159 -- ADC --------------------------------------------------------------------
160 SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
161 SIGNAL ADC_smpclk_sig : STD_LOGIC;
162 SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
163
164 SIGNAL bias_fail_sw_sig : STD_LOGIC;
165 -----------------------------------------------------------------------------
166 SIGNAL sample_val_s : STD_LOGIC;
167 SIGNAL sample_val_s2 : STD_LOGIC;
146 168 BEGIN -- beh
147 169
148 170 -----------------------------------------------------------------------------
149 171 -- CLK
150 172 -----------------------------------------------------------------------------
151 173
152 174 PROCESS(clk_50)
153 175 BEGIN
154 176 IF clk_50'EVENT AND clk_50 = '1' THEN
155 177 clk_50_s <= NOT clk_50_s;
156 178 END IF;
157 179 END PROCESS;
158
180
159 181 PROCESS(clk_50_s)
160 182 BEGIN
161 183 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
162 184 clk_25 <= NOT clk_25;
163 185 END IF;
164 186 END PROCESS;
165 187
166 188 -----------------------------------------------------------------------------
167
189
168 190 PROCESS (clk_25, reset)
169 191 BEGIN -- PROCESS
170 192 IF reset = '0' THEN -- asynchronous reset (active low)
171 193 LED0 <= '0';
172 194 LED1 <= '0';
173 195 LED2 <= '0';
174 IO1 <= '0';
175 IO2 <= '1';
196 IO0 <= '0';
197 --IO1 <= '0';
198 IO2 <= '1';
176 199 IO3 <= '0';
177 200 IO4 <= '0';
178 201 IO5 <= '0';
179 202 IO6 <= '0';
180 203 IO7 <= '0';
181 204 IO8 <= '0';
182 205 IO9 <= '0';
183 206 IO10 <= '0';
184 207 IO11 <= '0';
185 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
208 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
186 209 LED0 <= '0';
187 210 LED1 <= '1';
188 211 LED2 <= BP0;
189 IO1 <= '1';
190 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
191 IO3 <= ADC_SDO(0) OR ADC_SDO(1);
192 IO4 <= ADC_SDO(2) OR ADC_SDO(1);
193 IO5 <= ADC_SDO(3) OR ADC_SDO(4);
194 IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
195 IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
196 IO8 <= IO_s(8);
197 IO9 <= IO_s(9);
198 IO10 <= IO_s(10);
199 IO11 <= IO_s(11);
212 IO0 <= '1';
213 --IO1 <= '1';
214 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
215 IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
216 IO4 <= sample_val;
217 IO5 <= ahbi_m_ext.HREADY;
218 IO6 <= ahbi_m_ext.HRESP(0);
219 IO7 <= ahbi_m_ext.HRESP(1);
220 IO8 <= ahbi_m_ext.HGRANT(2);
221 IO9 <= ahbo_m_ext(2).HLOCK;
222 IO10 <= ahbo_m_ext(2).HBUSREQ;
223 IO11 <= sample_val_s2;
200 224 END IF;
201 225 END PROCESS;
202
203 PROCESS (clk_49, reset)
204 BEGIN -- PROCESS
205 IF reset = '0' THEN -- asynchronous reset (active low)
206 I00_s <= '0';
207 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
208 I00_s <= NOT I00_s;
209 END IF;
210 END PROCESS;
211 IO0 <= I00_s;
226
227 --PROCESS (clk_49, reset)
228 --BEGIN -- PROCESS
229 -- IF reset = '0' THEN -- asynchronous reset (active low)
230 -- I00_s <= '0';
231 -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
232 -- I00_s <= NOT I00_s;
233 -- END IF;
234 --END PROCESS;
235 --IO0 <= I00_s;
212 236
213 237 --UARTs
214 nCTS1 <= '1';
215 nCTS2 <= '1';
216 nDCD2 <= '1';
238 nCTS1 <= '1';
239 nCTS2 <= '1';
240 nDCD2 <= '1';
241
242 --EXT CONNECTOR
217 243
218 244 --SPACE WIRE
219 SPW_EN <= '0'; -- 0 => off
220
221 SPW_NOM_DOUT <= '0';
222 SPW_NOM_SOUT <= '0';
223 SPW_RED_DOUT <= '0';
224 SPW_RED_SOUT <= '0';
225
226 ADC_nCS <= '0';
227 ADC_CLK <= '0';
228 245
229
230 -----------------------------------------------------------------------------
231 lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst
232 GENERIC MAP (
233 tech => apa3e,
234 hindex => 1,
235 pindex => 5,
236 paddr => 5,
237 pmask => 16#fff#)
238 PORT MAP (
239 HCLK => clk_25,
240 HRESETn => reset ,
241 ahbmi => ahbi_m_ext ,
242 ahbmo => ahbo_m_ext(1),
243 apbi => apbi_ext,
244 apbo => apbo_ext(5),
245 out_ren => IO_s(11),
246 out_send => IO_s(10),
247 out_done => IO_s(9),
248 out_dmaout_okay => IO_s(8)
249 );
250
251 -----------------------------------------------------------------------------
246 ADC_nCS <= '0';
247 ADC_CLK <= '0';
252 248
253 leon3_soc_1: leon3_soc
249
250 leon3_soc_1 : leon3_soc
254 251 GENERIC MAP (
255 252 fabtech => apa3e,
256 253 memtech => apa3e,
257 254 padtech => inferred,
258 255 clktech => inferred,
259 256 disas => 0,
260 257 dbguart => 0,
261 258 pclow => 2,
262 259 clk_freq => 25000,
263 260 NB_CPU => 1,
264 261 ENABLE_FPU => 0,
265 262 FPU_NETLIST => 0,
266 263 ENABLE_DSU => 1,
267 264 ENABLE_AHB_UART => 1,
268 265 ENABLE_APB_UART => 1,
269 266 ENABLE_IRQMP => 1,
270 267 ENABLE_GPT => 1,
271 268 NB_AHB_MASTER => NB_AHB_MASTER,
272 269 NB_AHB_SLAVE => NB_AHB_SLAVE,
273 NB_APB_SLAVE => NB_APB_SLAVE)
270 NB_APB_SLAVE => NB_APB_SLAVE)
274 271 PORT MAP (
275 clk => clk_25,
276 reset => reset,
277 errorn => errorn,
278 ahbrxd => TXD1,
279 ahbtxd => RXD1,
280 urxd1 => TXD2,
281 utxd1 => RXD2,
282 address => SRAM_A,
283 data => SRAM_DQ,
284 nSRAM_BE0 => SRAM_nBE(0),
285 nSRAM_BE1 => SRAM_nBE(1),
286 nSRAM_BE2 => SRAM_nBE(2),
287 nSRAM_BE3 => SRAM_nBE(3),
288 nSRAM_WE => SRAM_nWE,
289 nSRAM_CE => SRAM_CE,
290 nSRAM_OE => SRAM_nOE,
291
272 clk => clk_25,
273 reset => reset,
274 errorn => errorn,
275 ahbrxd => TXD1,
276 ahbtxd => RXD1,
277 urxd1 => TXD2,
278 utxd1 => RXD2,
279 address => SRAM_A,
280 data => SRAM_DQ,
281 nSRAM_BE0 => SRAM_nBE(0),
282 nSRAM_BE1 => SRAM_nBE(1),
283 nSRAM_BE2 => SRAM_nBE(2),
284 nSRAM_BE3 => SRAM_nBE(3),
285 nSRAM_WE => SRAM_nWE,
286 nSRAM_CE => SRAM_CE,
287 nSRAM_OE => SRAM_nOE,
288
292 289 apbi_ext => apbi_ext,
293 290 apbo_ext => apbo_ext,
294 291 ahbi_s_ext => ahbi_s_ext,
295 292 ahbo_s_ext => ahbo_s_ext,
296 293 ahbi_m_ext => ahbi_m_ext,
297 294 ahbo_m_ext => ahbo_m_ext);
295
296 -------------------------------------------------------------------------------
297 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
298 -------------------------------------------------------------------------------
299 apb_lfr_time_management_1 : apb_lfr_time_management
300 GENERIC MAP (
301 pindex => 7,
302 paddr => 7,
303 pmask => 16#fff#,
304 pirq => 12)
305 PORT MAP (
306 clk25MHz => clk_25,
307 clk49_152MHz => clk_49,
308 resetn => reset,
309 grspw_tick => swno.tickout,
310 apbi => apbi_ext,
311 apbo => apbo_ext(7),
312 coarse_time => coarse_time,
313 fine_time => fine_time);
314
315 -----------------------------------------------------------------------
316 --- SpaceWire --------------------------------------------------------
317 -----------------------------------------------------------------------
318
319 SPW_EN <= '1';
320
321 spw_clk <= clk_50_s;
322 spw_rxtxclk <= spw_clk;
323 spw_rxclkn <= NOT spw_rxtxclk;
324
325 -- PADS for SPW1
326 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
327 PORT MAP (SPW_NOM_DIN, dtmp(0));
328 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
329 PORT MAP (SPW_NOM_SIN, stmp(0));
330 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
331 PORT MAP (SPW_NOM_DOUT, swno.d(0));
332 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
333 PORT MAP (SPW_NOM_SOUT, swno.s(0));
334 -- PADS FOR SPW2
335 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 PORT MAP (SPW_RED_SIN, dtmp(1));
337 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
338 PORT MAP (SPW_RED_DIN, stmp(1));
339 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_RED_DOUT, swno.d(1));
341 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_RED_SOUT, swno.s(1));
343
344 -- GRSPW PHY
345 --spw1_input: if CFG_SPW_GRSPW = 1 generate
346 spw_inputloop : FOR j IN 0 TO 1 GENERATE
347 spw_phy0 : grspw_phy
348 GENERIC MAP(
349 tech => apa3e,
350 rxclkbuftype => 1,
351 scantest => 0)
352 PORT MAP(
353 rxrst => swno.rxrst,
354 di => dtmp(j),
355 si => stmp(j),
356 rxclko => spw_rxclk(j),
357 do => swni.d(j),
358 ndo => swni.nd(j*5+4 DOWNTO j*5),
359 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
360 END GENERATE spw_inputloop;
361
362 -- SPW core
363 sw0 : grspwm GENERIC MAP(
364 tech => apa3e,
365 hindex => 1,
366 pindex => 5,
367 paddr => 5,
368 pirq => 11,
369 sysfreq => 25000, -- CPU_FREQ
370 rmap => 1,
371 rmapcrc => 1,
372 fifosize1 => 16,
373 fifosize2 => 16,
374 rxclkbuftype => 1,
375 rxunaligned => 0,
376 rmapbufs => 4,
377 ft => 0,
378 netlist => 0,
379 ports => 2,
380 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
381 memtech => apa3e,
382 destkey => 2,
383 spwcore => 1
384 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
385 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
386 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
387 )
388 PORT MAP(reset, clk_25, spw_rxclk(0),
389 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
390 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
391 swni, swno);
392
393 swni.tickin <= '0';
394 swni.rmapen <= '1';
395 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
396 swni.tickinraw <= '0';
397 swni.timein <= (OTHERS => '0');
398 swni.dcrstval <= (OTHERS => '0');
399 swni.timerrstval <= (OTHERS => '0');
400
401 -------------------------------------------------------------------------------
402 -- LFR ------------------------------------------------------------------------
403 -------------------------------------------------------------------------------
404 lpp_lfr_1 : lpp_lfr
405 GENERIC MAP (
406 Mem_use => use_RAM,
407 nb_data_by_buffer_size => 32,
408 nb_word_by_buffer_size => 30,
409 nb_snapshot_param_size => 32,
410 delta_vector_size => 32,
411 delta_vector_size_f0_2 => 7, -- log2(96)
412 pindex => 6,
413 paddr => 6,
414 pmask => 16#fff#,
415 pirq_ms => 6,
416 pirq_wfp => 14,
417 hindex => 2,
418 top_lfr_version => X"00000009")
419 PORT MAP (
420 clk => clk_25,
421 rstn => reset,
422 sample_B => sample(2 DOWNTO 0),
423 sample_E => sample(7 DOWNTO 3),
424 sample_val => sample_val,
425 apbi => apbi_ext,
426 apbo => apbo_ext(6),
427 ahbi => ahbi_m_ext,
428 ahbo => ahbo_m_ext(2),
429 coarse_time => coarse_time,
430 fine_time => fine_time,
431 data_shaping_BW => bias_fail_sw_sig);
432
433 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
434 GENERIC MAP (
435 ChanelCount => 8,
436 ncycle_cnv_high => 79,
437 ncycle_cnv => 500)
438 PORT MAP (
439 cnv_clk => clk_49,
440 cnv_rstn => reset,
441 cnv => ADC_smpclk_sig,
442 clk => clk_25,
443 rstn => reset,
444 ADC_data => ADC_data_sig,
445 ADC_nOE => ADC_OEB_bar_CH_sig,
446 sample => OPEN,
447 sample_val => sample_val);--OPEN );--
448
449 ADC_data_sig <= (OTHERS => '1');
450
451 lpp_debug_lfr_1 : lpp_debug_lfr
452 GENERIC MAP (
453 pindex => 8,
454 paddr => 8,
455 pmask => 16#fff#)
456 PORT MAP (
457 HCLK => clk_25,
458 HRESETn => reset,
459 apbi => apbi_ext,
460 apbo => apbo_ext(8),
461 sample_B => sample(2 DOWNTO 0),
462 sample_E => sample(7 DOWNTO 3));
463
464 PROCESS (clk_25, reset)
465 BEGIN -- PROCESS
466 IF reset = '0' THEN -- asynchronous reset (active low)
467 sample_val_s2 <= '0';
468 sample_val_s <= '0';
469 --sample_val <= '0';
470 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
471 sample_val_s <= IO1;
472 sample_val_s2 <= sample_val_s;
473 --sample_val <= (NOT sample_val_s2) AND sample_val_s;
474 END IF;
475 END PROCESS;
476
477
298 478
299 479 END beh;
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@@ -1,50 +1,51
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14
15 15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 17 CLEAN=soft-clean
18 18
19 19 TECHLIBS = proasic3e
20 20
21 21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
22 tmtc openchip hynix ihp gleichmann micron usbhc
23 23
24 24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 26 ./amba_lcd_16x2_ctrlr \
27 27 ./general_purpose/lpp_AMR \
28 28 ./general_purpose/lpp_balise \
29 29 ./general_purpose/lpp_delay \
30 30 ./dsp/lpp_fft \
31 31 ./lpp_bootloader \
32 32 ./lpp_cna \
33 33 ./lpp_demux \
34 34 ./lpp_matrix \
35 35 ./lpp_uart \
36 36 ./lpp_usb \
37 37 ./lpp_Header \
38 ./lpp_sim/CY7C1061DV33 \
38 39
39 40 FILESKIP =lpp_lfr_ms.vhd \
40 41 i2cmst.vhd \
41 42 APB_MULTI_DIODE.vhd \
42 43 APB_SIMPLE_DIODE.vhd \
43 44 Top_MatrixSpec.vhd \
44 45 APB_FFT.vhd
45 46
46 47 include $(GRLIB)/bin/Makefile
47 48 include $(GRLIB)/software/leon3/Makefile
48 49
49 50 ################## project specific targets ##########################
50 51
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@@ -1,25 +1,26
1 1 ./amba_lcd_16x2_ctrlr
2 2 ./general_purpose
3 3 ./general_purpose/lpp_AMR
4 4 ./general_purpose/lpp_balise
5 5 ./general_purpose/lpp_delay
6 6 ./lpp_amba
7 7 ./dsp/iir_filter
8 8 ./dsp/lpp_downsampling
9 9 ./dsp/lpp_fft
10 10 ./lfr_time_management
11 11 ./lpp_ad_Conv
12 12 ./lpp_bootloader
13 13 ./lpp_cna
14 14 ./lpp_demux
15 15 ./lpp_Header
16 16 ./lpp_matrix
17 17 ./lpp_memory
18 18 ./lpp_dma
19 19 ./lpp_uart
20 20 ./lpp_usb
21 21 ./lpp_waveform
22 22 ./lpp_top_lfr
23 23 ./lpp_Header
24 24 ./lpp_leon3_soc
25 25 ./lpp_debug_lfr
26 ./lpp_sim/CY7C1061DV33
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@@ -1,84 +1,81
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 13:04:01 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lpp_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 LIBRARY grlib;
23 23 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 27 PACKAGE lpp_lfr_time_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_TIME_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_time_management IS
33
34 33 GENERIC(
35 34 pindex : INTEGER := 0; --! APB slave index
36 35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 37 pirq : INTEGER := 0
39 38 );
40
41 39 PORT (
42 40 clk25MHz : IN STD_LOGIC; --! Clock
43 41 clk49_152MHz : IN STD_LOGIC; --! secondary clock
44 42 resetn : IN STD_LOGIC; --! Reset
45 43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
46 44 apbi : IN apb_slv_in_type; --! APB slave input signals
47 45 apbo : OUT apb_slv_out_type; --! APB slave output signals
48 46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
49 47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
50 48 );
51
52 49 END COMPONENT;
53 50
54 51 COMPONENT lfr_time_management
55 52 GENERIC (
56 53 nb_time_code_missing_limit : INTEGER);
57 54 PORT (
58 55 clk : IN STD_LOGIC;
59 56 rstn : IN STD_LOGIC;
60 57 new_timecode : IN STD_LOGIC;
61 58 new_coarsetime : IN STD_LOGIC;
62 59 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 60 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
64 61 fine_time_new : OUT STD_LOGIC;
65 62 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 63 coarse_time_new : OUT STD_LOGIC
67 64 );
68 65 END COMPONENT;
69 66
70 67 COMPONENT lpp_counter
71 68 GENERIC (
72 69 nb_wait_period : INTEGER;
73 70 nb_bit_of_data : INTEGER);
74 71 PORT (
75 72 clk : IN STD_LOGIC;
76 73 rstn : IN STD_LOGIC;
77 74 clear : IN STD_LOGIC;
78 75 full : OUT STD_LOGIC;
79 76 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
80 77 new_data : OUT STD_LOGIC );
81 78 END COMPONENT;
82 79
83 80 END lpp_lfr_time_management;
84 81
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@@ -1,43 +1,44
1 1
2 2 --=================================================================================
3 3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 4 --
5 5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 6 --=================================================================================
7 7
8 8
9 9 LIBRARY ieee;
10 10 USE ieee.std_logic_1164.ALL;
11 11 LIBRARY grlib;
12 12 USE grlib.amba.ALL;
13 13 USE std.textio.ALL;
14 14
15 15
16 16 PACKAGE apb_devices_list IS
17 17
18 18
19 19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20 20
21 21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 22 CONSTANT otherCore : amba_device_type := 16#2#;
23 23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 40
41 41 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
42 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
42 43
43 44 END;
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@@ -1,51 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27
28 PACKAGE lpp_debug_lfr_pkg IS
29
30 COMPONENT lpp_debug_dma_singleOrBurst
31 GENERIC (
32 tech : INTEGER;
33 hindex : INTEGER;
34 pindex : INTEGER;
35 paddr : INTEGER;
36 pmask : INTEGER);
37 PORT (
38 HCLK : IN STD_ULOGIC;
39 HRESETn : IN STD_ULOGIC;
40 ahbmi : IN AHB_Mst_In_Type;
41 ahbmo : OUT AHB_Mst_Out_Type;
42 apbi : IN apb_slv_in_type;
43 apbo : OUT apb_slv_out_type;
44 out_ren : OUT STD_LOGIC;
45 out_send : OUT STD_LOGIC;
46 out_done : OUT STD_LOGIC;
47 out_dmaout_okay : OUT STD_LOGIC
48 );
49 END COMPONENT;
50
51 END;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_lfr_pkg.ALL;
29 USE lpp.lpp_ad_conv.ALL;
30
31 PACKAGE lpp_debug_lfr_pkg IS
32
33 COMPONENT lpp_debug_dma_singleOrBurst
34 GENERIC (
35 tech : INTEGER;
36 hindex : INTEGER;
37 pindex : INTEGER;
38 paddr : INTEGER;
39 pmask : INTEGER);
40 PORT (
41 HCLK : IN STD_ULOGIC;
42 HRESETn : IN STD_ULOGIC;
43 ahbmi : IN AHB_Mst_In_Type;
44 ahbmo : OUT AHB_Mst_Out_Type;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 out_ren : OUT STD_LOGIC;
48 out_send : OUT STD_LOGIC;
49 out_done : OUT STD_LOGIC;
50 out_dmaout_okay : OUT STD_LOGIC
51 );
52 END COMPONENT;
53
54 COMPONENT lpp_debug_lfr
55 GENERIC (
56 tech : INTEGER;
57 hindex : INTEGER;
58 pindex : INTEGER;
59 paddr : INTEGER;
60 pmask : INTEGER);
61 PORT (
62 HCLK : IN STD_ULOGIC;
63 HRESETn : IN STD_ULOGIC;
64 apbi : IN apb_slv_in_type;
65 apbo : OUT apb_slv_out_type;
66 sample_B : OUT Samples14v(2 DOWNTO 0);
67 sample_E : OUT Samples14v(4 DOWNTO 0));
68 END COMPONENT;
69
70
71 END; No newline at end of file
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@@ -1,2 +1,3
1 1 lpp_debug_lfr_pkg.vhd
2 2 lpp_debug_dma_singleOrBurst.vhd
3 lpp_debug_lfr.vhd
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@@ -1,190 +1,195
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_dma_send_16word IS
40 40 PORT (
41 41 -- AMBA AHB system signals
42 42 HCLK : IN STD_ULOGIC;
43 43 HRESETn : IN STD_ULOGIC;
44 44
45 45 -- DMA
46 46 DMAIn : OUT DMA_In_Type;
47 47 DMAOut : IN DMA_OUt_Type;
48 48
49 49 --
50 50 send : IN STD_LOGIC;
51 51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 ren : OUT STD_LOGIC;
54 54 --
55 55 send_ok : OUT STD_LOGIC;
56 56 send_ko : OUT STD_LOGIC
57 57
58 58 );
59 59 END lpp_dma_send_16word;
60 60
61 61 ARCHITECTURE beh OF lpp_dma_send_16word IS
62 62
63 63 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
64 64 SIGNAL state : state_fsm_send_16word;
65 65
66 66 SIGNAL data_counter : INTEGER;
67 67 SIGNAL grant_counter : INTEGER;
68 68
69 69 BEGIN -- beh
70 70
71 71 DMAIn.Beat <= HINCR16;
72 72 DMAIn.Size <= HSIZE32;
73 73
74 74 PROCESS (HCLK, HRESETn)
75 75 BEGIN -- PROCESS
76 76 IF HRESETn = '0' THEN -- asynchronous reset (active low)
77 77 state <= IDLE;
78 78 send_ok <= '0';
79 79 send_ko <= '0';
80 80
81 81 DMAIn.Reset <= '1';
82 82 DMAIn.Address <= (OTHERS => '0');
83 83 DMAIn.Request <= '0';
84 84 DMAIn.Store <= '0';
85 85 DMAIn.Burst <= '1';
86 86 DMAIn.Lock <= '0';
87 87 data_counter <= 0;
88 88 grant_counter <= 0;
89 89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
90 90
91 91 DMAIn.Reset <= '0';
92 92
93 93 CASE state IS
94 94 WHEN IDLE =>
95 95 DMAIn.Store <= '1';
96 96 DMAIn.Request <= '0';
97 97 send_ok <= '0';
98 98 send_ko <= '0';
99 99 DMAIn.Address <= address;
100 100 data_counter <= 0;
101 101 DMAIn.Lock <= '0'; -- FIX test
102 102 IF send = '1' THEN
103 103 state <= REQUEST_BUS;
104 104 DMAIn.Request <= '1';
105 105 DMAIn.Lock <= '1'; -- FIX test
106 106 DMAIn.Store <= '1';
107 107 END IF;
108 108 WHEN REQUEST_BUS =>
109 109 IF DMAOut.Grant = '1' THEN
110 110 data_counter <= 1;
111 111 grant_counter <= 1;
112 112 state <= SEND_DATA;
113 113 END IF;
114 114 WHEN SEND_DATA =>
115 115
116 116 IF DMAOut.Fault = '1' THEN
117 117 DMAIn.Reset <= '0';
118 118 DMAIn.Address <= (OTHERS => '0');
119 119 DMAIn.Request <= '0';
120 120 DMAIn.Store <= '0';
121 121 DMAIn.Burst <= '0';
122 122 state <= ERROR0;
123 123 ELSE
124 124
125 125 IF DMAOut.Grant = '1' THEN
126 126 IF grant_counter = 15 THEN
127 127 DMAIn.Reset <= '0';
128 128 DMAIn.Request <= '0';
129 129 DMAIn.Store <= '0';
130 130 DMAIn.Burst <= '0';
131 131 ELSE
132 132 grant_counter <= grant_counter+1;
133 133 END IF;
134 134 END IF;
135 135
136 136 IF DMAOut.OKAY = '1' THEN
137 137 IF data_counter = 15 THEN
138 138 DMAIn.Address <= (OTHERS => '0');
139 139 state <= WAIT_LAST_READY;
140 140 ELSE
141 141 data_counter <= data_counter + 1;
142 142 END IF;
143 143 END IF;
144 144 END IF;
145 145
146 146
147 147 WHEN WAIT_LAST_READY =>
148 148 IF DMAOut.Ready = '1' THEN
149 149 IF grant_counter = 15 THEN
150 150 state <= IDLE;
151 151 send_ok <= '1';
152 152 send_ko <= '0';
153 153 ELSE
154 154 state <= ERROR0;
155 155 END IF;
156 156 END IF;
157 157
158 158 WHEN ERROR0 =>
159 159 state <= ERROR1;
160 160 WHEN ERROR1 =>
161 161 send_ok <= '0';
162 162 send_ko <= '1';
163 163 state <= IDLE;
164 164 WHEN OTHERS => NULL;
165 165 END CASE;
166 166 END IF;
167 167 END PROCESS;
168 168
169 169 DMAIn.Data <= data;
170
171 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 '1';
170 173
171 ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
172 '1';
174 -- \/ JC - 20/01/2014 \/
175 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 -- '1';
177 -- /\ JC - 20/01/2014 /\
173 178
174 179 -- \/ JC - 11/12/2013 \/
175 180 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
176 181 -- '1';
177 182 -- /\ JC - 11/12/2013 /\
178 183
179 184 -- \/ JC - 10/12/2013 \/
180 185 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
181 186 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
182 187 -- '1';
183 188 -- /\ JC - 10/12/2013 /\
184 189
185 190 -- \/ JC - 09/12/2013 \/
186 191 --ren <= '0' WHEN state = SEND_DATA ELSE
187 192 -- '1';
188 193 -- /\ JC - 09/12/2013 /\
189 194
190 195 END beh;
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@@ -1,185 +1,191
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35 LIBRARY lpp;
36 36 USE lpp.lpp_amba.ALL;
37 37 USE lpp.apb_devices_list.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_waveform_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
44 44
45 45 ENTITY lpp_dma_singleOrBurst IS
46 46 GENERIC (
47 47 tech : INTEGER := inferred;
48 48 hindex : INTEGER := 2
49 49 );
50 50 PORT (
51 51 -- AMBA AHB system signals
52 52 HCLK : IN STD_ULOGIC;
53 53 HRESETn : IN STD_ULOGIC;
54 54 --
55 55 run : IN STD_LOGIC;
56 56 -- AMBA AHB Master Interface
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59 --
60 60 send : IN STD_LOGIC;
61 61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 62 done : OUT STD_LOGIC;
63 63 ren : OUT STD_LOGIC;
64 64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 66 --
67 67 debug_dmaout_okay : OUT STD_LOGIC
68 68
69 69 );
70 70 END;
71 71
72 72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
73 73 -----------------------------------------------------------------------------
74 74 SIGNAL DMAIn : DMA_In_Type;
75 75 SIGNAL DMAOut : DMA_OUt_Type;
76 76 -----------------------------------------------------------------------------
77 77 -----------------------------------------------------------------------------
78 78 -- CONTROL
79 79 SIGNAL single_send : STD_LOGIC;
80 80 SIGNAL burst_send : STD_LOGIC;
81 81
82 82 -----------------------------------------------------------------------------
83 83 -- SEND SINGLE MODULE
84 84 SIGNAL single_dmai : DMA_In_Type;
85 85
86 86 SIGNAL single_send_ok : STD_LOGIC;
87 87 SIGNAL single_send_ko : STD_LOGIC;
88 88 SIGNAL single_ren : STD_LOGIC;
89 89 -----------------------------------------------------------------------------
90 90 -- SEND SINGLE MODULE
91 91 SIGNAL burst_dmai : DMA_In_Type;
92 92
93 93 SIGNAL burst_send_ok : STD_LOGIC;
94 94 SIGNAL burst_send_ko : STD_LOGIC;
95 95 SIGNAL burst_ren : STD_LOGIC;
96 96 -----------------------------------------------------------------------------
97 97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 BEGIN
99 99
100 100 debug_dmaout_okay <= DMAOut.OKAY;
101 101
102 102
103 103 -----------------------------------------------------------------------------
104 104 -- DMA to AHB interface
105 105 DMA2AHB_1 : DMA2AHB
106 106 GENERIC MAP (
107 107 hindex => hindex,
108 108 vendorid => VENDOR_LPP,
109 109 deviceid => 10,
110 110 version => 0,
111 111 syncrst => 1,
112 112 boundary => 1) -- FIX 11/01/2013
113 113 PORT MAP (
114 114 HCLK => HCLK,
115 115 HRESETn => HRESETn,
116 116 DMAIn => DMAIn,
117 117 DMAOut => DMAOut,
118 118
119 119 AHBIn => AHB_Master_In,
120 120 AHBOut => AHB_Master_Out);
121 121 -----------------------------------------------------------------------------
122 122
123 123 -----------------------------------------------------------------------------
124 124 -----------------------------------------------------------------------------
125 125 -- LE PROBLEME EST LA !!!!!
126 126 -----------------------------------------------------------------------------
127 127 -----------------------------------------------------------------------------
128 128 -- C'est le signal valid_burst qui n'est pas assez long.
129 129 -----------------------------------------------------------------------------
130 130 single_send <= send WHEN valid_burst = '0' ELSE '0';
131 131 burst_send <= send WHEN valid_burst = '1' ELSE '0';
132 132 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
133 133
134 134 -- TODO : verifier
135 135 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
136 136 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
137 137 -- burst_send_ok OR burst_send_ko;
138 138
139 139 --ren <= burst_ren WHEN valid_burst = '1' ELSE
140 140 -- NOT single_send_ok;
141 141 --ren <= burst_ren AND single_ren;
142 142
143 ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
144 '1';
143 -- \/ JC - 20/01/2014 \/
144 ren <= burst_ren WHEN valid_burst = '1' ELSE
145 single_ren;
146
147
148 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
149 -- '1';
150 -- /\ JC - 20/01/2014 /\
145 151
146 152 -----------------------------------------------------------------------------
147 153 -- SEND 1 word by DMA
148 154 -----------------------------------------------------------------------------
149 155 lpp_dma_send_1word_1 : lpp_dma_send_1word
150 156 PORT MAP (
151 157 HCLK => HCLK,
152 158 HRESETn => HRESETn,
153 159 DMAIn => single_dmai,
154 160 DMAOut => DMAOut,
155 161
156 162 send => single_send,
157 163 address => address,
158 164 data => data_2_halfword,
159 165 ren => single_ren,
160 166
161 167 send_ok => single_send_ok, -- TODO
162 168 send_ko => single_send_ko -- TODO
163 169 );
164 170
165 171 -----------------------------------------------------------------------------
166 172 -- SEND 16 word by DMA (in burst mode)
167 173 -----------------------------------------------------------------------------
168 174 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
169 175
170 176 lpp_dma_send_16word_1 : lpp_dma_send_16word
171 177 PORT MAP (
172 178 HCLK => HCLK,
173 179 HRESETn => HRESETn,
174 180 DMAIn => burst_dmai,
175 181 DMAOut => DMAOut,
176 182
177 183 send => burst_send,
178 184 address => address,
179 185 data => data_2_halfword,
180 186 ren => burst_ren,
181 187
182 188 send_ok => burst_send_ok,
183 189 send_ko => burst_send_ko);
184 190
185 191 END Behavioral;
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@@ -1,424 +1,424
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_lfr_time_management.ALL;
43 43 USE lpp.lpp_leon3_soc_pkg.ALL;
44 44
45 45 ENTITY leon3_soc IS
46 46 GENERIC (
47 47 fabtech : INTEGER := apa3e;
48 48 memtech : INTEGER := apa3e;
49 49 padtech : INTEGER := inferred;
50 50 clktech : INTEGER := inferred;
51 51 disas : INTEGER := 0; -- Enable disassembly to console
52 52 dbguart : INTEGER := 0; -- Print UART on console
53 53 pclow : INTEGER := 2;
54 54 --
55 55 clk_freq : INTEGER := 25000; --kHz
56 56 --
57 57 NB_CPU : INTEGER := 1;
58 58 ENABLE_FPU : INTEGER := 1;
59 59 FPU_NETLIST : INTEGER := 1;
60 60 ENABLE_DSU : INTEGER := 1;
61 61 ENABLE_AHB_UART : INTEGER := 1;
62 62 ENABLE_APB_UART : INTEGER := 1;
63 63 ENABLE_IRQMP : INTEGER := 1;
64 64 ENABLE_GPT : INTEGER := 1;
65 65 --
66 66 NB_AHB_MASTER : INTEGER := 0;
67 67 NB_AHB_SLAVE : INTEGER := 0;
68 68 NB_APB_SLAVE : INTEGER := 0
69 69 );
70 70 PORT (
71 71 clk : IN STD_ULOGIC;
72 72 reset : IN STD_ULOGIC;
73 73
74 74 errorn : OUT STD_ULOGIC;
75 75
76 76 -- UART AHB ---------------------------------------------------------------
77 77 ahbrxd : IN STD_ULOGIC; -- DSU rx data
78 78 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
79 79
80 80 -- UART APB ---------------------------------------------------------------
81 81 urxd1 : IN STD_ULOGIC; -- UART1 rx data
82 82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83 83
84 84 -- RAM --------------------------------------------------------------------
85 85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
86 86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 nSRAM_BE0 : OUT STD_LOGIC;
88 88 nSRAM_BE1 : OUT STD_LOGIC;
89 89 nSRAM_BE2 : OUT STD_LOGIC;
90 90 nSRAM_BE3 : OUT STD_LOGIC;
91 91 nSRAM_WE : OUT STD_LOGIC;
92 92 nSRAM_CE : OUT STD_LOGIC;
93 93 nSRAM_OE : OUT STD_LOGIC;
94 94
95 95 -- APB --------------------------------------------------------------------
96 96 apbi_ext : OUT apb_slv_in_type;
97 97 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
98 98 -- AHB_Slave --------------------------------------------------------------
99 99 ahbi_s_ext : OUT ahb_slv_in_type;
100 100 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
101 101 -- AHB_Master -------------------------------------------------------------
102 102 ahbi_m_ext : OUT AHB_Mst_In_Type;
103 103 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
104 104
105 105 );
106 106 END;
107 107
108 108 ARCHITECTURE Behavioral OF leon3_soc IS
109 109
110 110 -----------------------------------------------------------------------------
111 111 -- CONFIG -------------------------------------------------------------------
112 112 -----------------------------------------------------------------------------
113 113
114 114 -- Clock generator
115 115 constant CFG_CLKMUL : integer := (1);
116 116 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
117 117 constant CFG_OCLKDIV : integer := (1);
118 118 constant CFG_CLK_NOFB : integer := 0;
119 119 -- LEON3 processor core
120 120 constant CFG_LEON3 : integer := 1;
121 121 constant CFG_NCPU : integer := NB_CPU;
122 122 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
123 123 constant CFG_V8 : integer := 0;
124 124 constant CFG_MAC : integer := 0;
125 125 constant CFG_SVT : integer := 0;
126 126 constant CFG_RSTADDR : integer := 16#00000#;
127 127 constant CFG_LDDEL : integer := (1);
128 128 constant CFG_NWP : integer := (0);
129 129 constant CFG_PWD : integer := 1*2;
130 130 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
131 131 -- 1*(8 + 16 * 0) => grfpu-light
132 132 -- 1*(8 + 16 * 1) => netlist
133 133 -- 0*(8 + 16 * 0) => No FPU
134 134 -- 0*(8 + 16 * 1) => No FPU;
135 135 constant CFG_ICEN : integer := 1;
136 136 constant CFG_ISETS : integer := 1;
137 137 constant CFG_ISETSZ : integer := 4;
138 138 constant CFG_ILINE : integer := 4;
139 139 constant CFG_IREPL : integer := 0;
140 140 constant CFG_ILOCK : integer := 0;
141 141 constant CFG_ILRAMEN : integer := 0;
142 142 constant CFG_ILRAMADDR: integer := 16#8E#;
143 143 constant CFG_ILRAMSZ : integer := 1;
144 144 constant CFG_DCEN : integer := 1;
145 145 constant CFG_DSETS : integer := 1;
146 146 constant CFG_DSETSZ : integer := 4;
147 147 constant CFG_DLINE : integer := 4;
148 148 constant CFG_DREPL : integer := 0;
149 149 constant CFG_DLOCK : integer := 0;
150 150 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
151 151 constant CFG_DLRAMEN : integer := 0;
152 152 constant CFG_DLRAMADDR: integer := 16#8F#;
153 153 constant CFG_DLRAMSZ : integer := 1;
154 154 constant CFG_MMUEN : integer := 0;
155 155 constant CFG_ITLBNUM : integer := 2;
156 156 constant CFG_DTLBNUM : integer := 2;
157 157 constant CFG_TLB_TYPE : integer := 1 + 0*2;
158 158 constant CFG_TLB_REP : integer := 1;
159 159
160 160 constant CFG_DSU : integer := ENABLE_DSU;
161 161 constant CFG_ITBSZ : integer := 0;
162 162 constant CFG_ATBSZ : integer := 0;
163 163
164 164 -- AMBA settings
165 165 constant CFG_DEFMST : integer := (0);
166 166 constant CFG_RROBIN : integer := 1;
167 167 constant CFG_SPLIT : integer := 0;
168 168 constant CFG_AHBIO : integer := 16#FFF#;
169 169 constant CFG_APBADDR : integer := 16#800#;
170 170
171 171 -- DSU UART
172 172 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
173 173
174 174 -- LEON2 memory controller
175 175 constant CFG_MCTRL_SDEN : integer := 0;
176 176
177 177 -- UART 1
178 178 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
179 179 constant CFG_UART1_FIFO : integer := 1;
180 180
181 181 -- LEON3 interrupt controller
182 182 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
183 183
184 184 -- Modular timer
185 185 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
186 186 constant CFG_GPT_NTIM : integer := (2);
187 187 constant CFG_GPT_SW : integer := (8);
188 188 constant CFG_GPT_TW : integer := (32);
189 189 constant CFG_GPT_IRQ : integer := (8);
190 190 constant CFG_GPT_SEPIRQ : integer := 1;
191 191 constant CFG_GPT_WDOGEN : integer := 0;
192 192 constant CFG_GPT_WDOG : integer := 16#0#;
193 193 -----------------------------------------------------------------------------
194 194
195 195 -----------------------------------------------------------------------------
196 196 -- SIGNALs
197 197 -----------------------------------------------------------------------------
198 198 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
199 199 -- CLK & RST --
200 200 SIGNAL clk2x : STD_ULOGIC;
201 201 SIGNAL clkmn : STD_ULOGIC;
202 202 SIGNAL clkm : STD_ULOGIC;
203 203 SIGNAL rstn : STD_ULOGIC;
204 204 SIGNAL rstraw : STD_ULOGIC;
205 205 SIGNAL pciclk : STD_ULOGIC;
206 206 SIGNAL sdclkl : STD_ULOGIC;
207 207 SIGNAL cgi : clkgen_in_type;
208 208 SIGNAL cgo : clkgen_out_type;
209 209 --- AHB / APB
210 210 SIGNAL apbi : apb_slv_in_type;
211 211 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
212 212 SIGNAL ahbsi : ahb_slv_in_type;
213 213 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
214 214 SIGNAL ahbmi : ahb_mst_in_type;
215 215 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
216 216 --UART
217 217 SIGNAL ahbuarti : uart_in_type;
218 218 SIGNAL ahbuarto : uart_out_type;
219 219 SIGNAL apbuarti : uart_in_type;
220 220 SIGNAL apbuarto : uart_out_type;
221 221 --MEM CTRLR
222 222 SIGNAL memi : memory_in_type;
223 223 SIGNAL memo : memory_out_type;
224 224 SIGNAL wpo : wprot_out_type;
225 225 SIGNAL sdo : sdram_out_type;
226 226 --IRQ
227 227 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
228 228 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
229 229 --Timer
230 230 SIGNAL gpti : gptimer_in_type;
231 231 SIGNAL gpto : gptimer_out_type;
232 232 --DSU
233 233 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
234 234 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
235 235 SIGNAL dsui : dsu_in_type;
236 236 SIGNAL dsuo : dsu_out_type;
237 237 -----------------------------------------------------------------------------
238 238 BEGIN
239 239
240 240
241 241 ----------------------------------------------------------------------
242 242 --- Reset and Clock generation -------------------------------------
243 243 ----------------------------------------------------------------------
244 244
245 245 cgi.pllctrl <= "00";
246 246 cgi.pllrst <= rstraw;
247 247
248 248 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
249 249
250 250 clkgen0 : clkgen -- clock generator
251 251 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
252 252 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
253 253 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
254 254
255 255 ----------------------------------------------------------------------
256 256 --- LEON3 processor / DSU / IRQ ------------------------------------
257 257 ----------------------------------------------------------------------
258 258
259 259 l3 : IF CFG_LEON3 = 1 GENERATE
260 260 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
261 261 u0 : leon3s -- LEON3 processor
262 262 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
263 263 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
264 264 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
265 265 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
266 266 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
267 267 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
268 268 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
269 269 irqi(i), irqo(i), dbgi(i), dbgo(i));
270 270 END GENERATE;
271 271 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
272 272
273 273 dsugen : IF CFG_DSU = 1 GENERATE
274 274 dsu0 : dsu3 -- LEON3 Debug Support Unit
275 275 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
276 276 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
277 277 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
278 278 dsui.enable <= '1';
279 279 dsui.break <= '0';
280 280 END GENERATE;
281 281 END GENERATE;
282 282
283 283 nodsu : IF CFG_DSU = 0 GENERATE
284 284 ahbso(2) <= ahbs_none;
285 285 dsuo.tstop <= '0';
286 286 dsuo.active <= '0';
287 287 END GENERATE;
288 288
289 289 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
290 290 irqctrl0 : irqmp -- interrupt controller
291 291 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
292 292 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
293 293 END GENERATE;
294 294 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
295 295 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
296 296 irqi(i).irl <= "0000";
297 297 END GENERATE;
298 298 apbo(2) <= apb_none;
299 299 END GENERATE;
300 300
301 301 ----------------------------------------------------------------------
302 302 --- Memory controllers ---------------------------------------------
303 303 ----------------------------------------------------------------------
304 304 memctrlr : mctrl GENERIC MAP (
305 305 hindex => 0,
306 306 pindex => 0,
307 307 paddr => 0,
308 308 srbanks => 1
309 309 )
310 310 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
311 311
312 312 memi.brdyn <= '1';
313 313 memi.bexcn <= '1';
314 314 memi.writen <= '1';
315 315 memi.wrn <= "1111";
316 316 memi.bwidth <= "10";
317 317
318 318 bdr : FOR i IN 0 TO 3 GENERATE
319 319 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
320 320 PORT MAP (
321 321 data(31-i*8 DOWNTO 24-i*8),
322 322 memo.data(31-i*8 DOWNTO 24-i*8),
323 323 memo.bdrive(i),
324 324 memi.data(31-i*8 DOWNTO 24-i*8));
325 325 END GENERATE;
326 326
327 327 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
328 328 PORT MAP (address, memo.address(21 DOWNTO 2));
329 329
330 330 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
331 331 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
332 332 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
333 333 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
334 334 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
335 335 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
336 336 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
337 337
338 338 ----------------------------------------------------------------------
339 339 --- AHB CONTROLLER -------------------------------------------------
340 340 ----------------------------------------------------------------------
341 341 ahb0 : ahbctrl -- AHB arbiter/multiplexer
342 342 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
343 343 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
344 344 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
345 345 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
346 346
347 347 ----------------------------------------------------------------------
348 348 --- AHB UART -------------------------------------------------------
349 349 ----------------------------------------------------------------------
350 350 dcomgen : IF CFG_AHB_UART = 1 GENERATE
351 351 dcom0 : ahbuart
352 352 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
353 353 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
354 354 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
355 355 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
356 356 END GENERATE;
357 357 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
358 358
359 359 ----------------------------------------------------------------------
360 360 --- APB Bridge -----------------------------------------------------
361 361 ----------------------------------------------------------------------
362 362 apb0 : apbctrl -- AHB/APB bridge
363 363 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
364 364 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
365 365
366 366 ----------------------------------------------------------------------
367 367 --- GPT Timer ------------------------------------------------------
368 368 ----------------------------------------------------------------------
369 369 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
370 370 timer0 : gptimer -- timer unit
371 371 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
372 372 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
373 373 nbits => CFG_GPT_TW)
374 374 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
375 375 gpti.dhalt <= dsuo.tstop;
376 376 gpti.extclk <= '0';
377 377 END GENERATE;
378 378 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
379 379
380 380
381 381 ----------------------------------------------------------------------
382 382 --- APB UART -------------------------------------------------------
383 383 ----------------------------------------------------------------------
384 384 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
385 385 uart1 : apbuart -- UART 1
386 386 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
387 387 fifosize => CFG_UART1_FIFO)
388 388 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
389 389 apbuarti.rxd <= urxd1;
390 390 apbuarti.extclk <= '0';
391 391 utxd1 <= apbuarto.txd;
392 392 apbuarti.ctsn <= '0';
393 393 END GENERATE;
394 394 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
395 395
396 396 -------------------------------------------------------------------------------
397 397 -- AMBA BUS -------------------------------------------------------------------
398 398 -------------------------------------------------------------------------------
399 399
400 400 -- APB --------------------------------------------------------------------
401 401 apbi_ext <= apbi;
402 402 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
403 403 max_16_apb: IF I + 5 < 16 GENERATE
404 404 apbo(I+5)<= apbo_ext(I+5);
405 405 END GENERATE max_16_apb;
406 406 END GENERATE all_apb;
407 407 -- AHB_Slave --------------------------------------------------------------
408 408 ahbi_s_ext <= ahbsi;
409 409 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
410 410 max_16_ahbs: IF I + 3 < 16 GENERATE
411 411 ahbso(I+3) <= ahbo_s_ext(I+3);
412 412 END GENERATE max_16_ahbs;
413 413 END GENERATE all_ahbs;
414 414 -- AHB_Master -------------------------------------------------------------
415 415 ahbi_m_ext <= ahbmi;
416 all_ahbm: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
416 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
417 417 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
418 418 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
419 419 END GENERATE max_16_ahbm;
420 420 END GENERATE all_ahbm;
421 421
422 422
423 423
424 424 END Behavioral;
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@@ -1,695 +1,708
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 49 sample_B : IN Samples14v(2 DOWNTO 0);
50 50 sample_E : IN Samples14v(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63
64 64 --debug
65 65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 66 debug_f0_data_valid : OUT STD_LOGIC;
67 67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 68 debug_f1_data_valid : OUT STD_LOGIC;
69 69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 debug_f2_data_valid : OUT STD_LOGIC;
71 71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC
72 debug_f3_data_valid : OUT STD_LOGIC;
73
74 -- debug FIFO_IN
75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
83
84 --debug FIFO OUT
85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
93
94 --debug DMA IN
95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
73 103 );
74 104 END lpp_lfr;
75 105
76 106 ARCHITECTURE beh OF lpp_lfr IS
77 107 SIGNAL sample : Samples14v(7 DOWNTO 0);
78 108 SIGNAL sample_s : Samples(7 DOWNTO 0);
79 109 --
80 110 SIGNAL data_shaping_SP0 : STD_LOGIC;
81 111 SIGNAL data_shaping_SP1 : STD_LOGIC;
82 112 SIGNAL data_shaping_R0 : STD_LOGIC;
83 113 SIGNAL data_shaping_R1 : STD_LOGIC;
84 114 --
85 115 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 118 --
89 119 SIGNAL sample_f0_val : STD_LOGIC;
90 120 SIGNAL sample_f1_val : STD_LOGIC;
91 121 SIGNAL sample_f2_val : STD_LOGIC;
92 122 SIGNAL sample_f3_val : STD_LOGIC;
93 123 --
94 124 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 125 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 126 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
97 127 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
98 128 --
99 129 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 130 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 131 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 132
103 133 -- SM
104 134 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
105 135 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
106 136 SIGNAL ready_matrix_f1 : STD_LOGIC;
107 137 SIGNAL ready_matrix_f2 : STD_LOGIC;
108 138 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
109 139 SIGNAL error_bad_component_error : STD_LOGIC;
110 140 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 141 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
112 142 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
113 143 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
114 144 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
115 145 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
116 146 SIGNAL status_error_bad_component_error : STD_LOGIC;
117 147 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
118 148 SIGNAL config_active_interruption_onError : STD_LOGIC;
119 149 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 150 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 151 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 152 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 153
124 154 -- WFP
125 155 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 156 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 157 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 158 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 159 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
130 160 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
131 161 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
132 162 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
133 163 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
134 164
135 165 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
136 166 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
137 167 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
138 168 SIGNAL enable_f0 : STD_LOGIC;
139 169 SIGNAL enable_f1 : STD_LOGIC;
140 170 SIGNAL enable_f2 : STD_LOGIC;
141 171 SIGNAL enable_f3 : STD_LOGIC;
142 172 SIGNAL burst_f0 : STD_LOGIC;
143 173 SIGNAL burst_f1 : STD_LOGIC;
144 174 SIGNAL burst_f2 : STD_LOGIC;
145 175 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 176 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 177 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 178 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 179
150 180 SIGNAL run : STD_LOGIC;
151 181 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
152 182
153 183 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 184 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 185 SIGNAL data_f0_data_out_valid : STD_LOGIC;
156 186 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
157 187 SIGNAL data_f0_data_out_ren : STD_LOGIC;
158 188 --f1
159 189 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 190 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 191 SIGNAL data_f1_data_out_valid : STD_LOGIC;
162 192 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
163 193 SIGNAL data_f1_data_out_ren : STD_LOGIC;
164 194 --f2
165 195 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 196 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 197 SIGNAL data_f2_data_out_valid : STD_LOGIC;
168 198 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
169 199 SIGNAL data_f2_data_out_ren : STD_LOGIC;
170 200 --f3
171 201 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 202 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 203 SIGNAL data_f3_data_out_valid : STD_LOGIC;
174 204 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
175 205 SIGNAL data_f3_data_out_ren : STD_LOGIC;
176 206
177 207 -----------------------------------------------------------------------------
178 208 --
179 209 -----------------------------------------------------------------------------
180 210 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 211 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
182 212 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
183 213 --f1
184 214 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 215 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
186 216 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
187 217 --f2
188 218 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 219 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
190 220 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
191 221 --f3
192 222 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 223 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
194 224 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
195 225
196 226 -----------------------------------------------------------------------------
197 227 -- DMA RR
198 228 -----------------------------------------------------------------------------
199 229 SIGNAL dma_sel_valid : STD_LOGIC;
200 230 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 231 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 232 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
203 233
204 234 -----------------------------------------------------------------------------
205 235 -- DMA_REG
206 236 -----------------------------------------------------------------------------
207 237 SIGNAL ongoing_reg : STD_LOGIC;
208 238 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 239 SIGNAL dma_send_reg : STD_LOGIC;
210 240 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
211 241 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 242 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 243
214 244
215 245 -----------------------------------------------------------------------------
216 246 -- DMA
217 247 -----------------------------------------------------------------------------
218 248 SIGNAL dma_send : STD_LOGIC;
219 249 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
220 250 SIGNAL dma_done : STD_LOGIC;
221 251 SIGNAL dma_ren : STD_LOGIC;
222 252 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 253 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 254 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 255
226 256 -----------------------------------------------------------------------------
227 257 -- DEBUG
228 258 -----------------------------------------------------------------------------
229 259 --
230 260 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
231 261 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
232 262 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
233 263 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
234 264
235 265 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 266 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 267 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 268 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 269 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 270 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 271 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 272 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 273
244 274 BEGIN
245 275
246 276 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
247 277 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
248 278
249 279 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
250 280 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
251 281 END GENERATE all_channel;
252 282
253 283 -----------------------------------------------------------------------------
254 284 lpp_lfr_filter_1 : lpp_lfr_filter
255 285 GENERIC MAP (
256 286 Mem_use => Mem_use)
257 287 PORT MAP (
258 288 sample => sample_s,
259 289 sample_val => sample_val,
260 290 clk => clk,
261 291 rstn => rstn,
262 292 data_shaping_SP0 => data_shaping_SP0,
263 293 data_shaping_SP1 => data_shaping_SP1,
264 294 data_shaping_R0 => data_shaping_R0,
265 295 data_shaping_R1 => data_shaping_R1,
266 296 sample_f0_val => sample_f0_val,
267 297 sample_f1_val => sample_f1_val,
268 298 sample_f2_val => sample_f2_val,
269 299 sample_f3_val => sample_f3_val,
270 300 sample_f0_wdata => sample_f0_data,
271 301 sample_f1_wdata => sample_f1_data,
272 302 sample_f2_wdata => sample_f2_data,
273 303 sample_f3_wdata => sample_f3_data);
274 304
275 305 -----------------------------------------------------------------------------
276 306 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
277 307 GENERIC MAP (
278 308 nb_data_by_buffer_size => nb_data_by_buffer_size,
279 309 nb_word_by_buffer_size => nb_word_by_buffer_size,
280 310 nb_snapshot_param_size => nb_snapshot_param_size,
281 311 delta_vector_size => delta_vector_size,
282 312 delta_vector_size_f0_2 => delta_vector_size_f0_2,
283 313 pindex => pindex,
284 314 paddr => paddr,
285 315 pmask => pmask,
286 316 pirq_ms => pirq_ms,
287 317 pirq_wfp => pirq_wfp,
288 318 top_lfr_version => top_lfr_version)
289 319 PORT MAP (
290 320 HCLK => clk,
291 321 HRESETn => rstn,
292 322 apbi => apbi,
293 323 apbo => apbo,
294 324 ready_matrix_f0_0 => ready_matrix_f0_0,
295 325 ready_matrix_f0_1 => ready_matrix_f0_1,
296 326 ready_matrix_f1 => ready_matrix_f1,
297 327 ready_matrix_f2 => ready_matrix_f2,
298 328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
299 329 error_bad_component_error => error_bad_component_error,
300 330 debug_reg => debug_reg,
301 331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
302 332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
303 333 status_ready_matrix_f1 => status_ready_matrix_f1,
304 334 status_ready_matrix_f2 => status_ready_matrix_f2,
305 335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
306 336 status_error_bad_component_error => status_error_bad_component_error,
307 337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
308 338 config_active_interruption_onError => config_active_interruption_onError,
309 339 addr_matrix_f0_0 => addr_matrix_f0_0,
310 340 addr_matrix_f0_1 => addr_matrix_f0_1,
311 341 addr_matrix_f1 => addr_matrix_f1,
312 342 addr_matrix_f2 => addr_matrix_f2,
313 343 status_full => status_full,
314 344 status_full_ack => status_full_ack,
315 345 status_full_err => status_full_err,
316 346 status_new_err => status_new_err,
317 347 data_shaping_BW => data_shaping_BW,
318 348 data_shaping_SP0 => data_shaping_SP0,
319 349 data_shaping_SP1 => data_shaping_SP1,
320 350 data_shaping_R0 => data_shaping_R0,
321 351 data_shaping_R1 => data_shaping_R1,
322 352 delta_snapshot => delta_snapshot,
323 353 delta_f0 => delta_f0,
324 354 delta_f0_2 => delta_f0_2,
325 355 delta_f1 => delta_f1,
326 356 delta_f2 => delta_f2,
327 357 nb_data_by_buffer => nb_data_by_buffer,
328 358 nb_word_by_buffer => nb_word_by_buffer,
329 359 nb_snapshot_param => nb_snapshot_param,
330 360 enable_f0 => enable_f0,
331 361 enable_f1 => enable_f1,
332 362 enable_f2 => enable_f2,
333 363 enable_f3 => enable_f3,
334 364 burst_f0 => burst_f0,
335 365 burst_f1 => burst_f1,
336 366 burst_f2 => burst_f2,
337 367 run => run,
338 368 addr_data_f0 => addr_data_f0,
339 369 addr_data_f1 => addr_data_f1,
340 370 addr_data_f2 => addr_data_f2,
341 371 addr_data_f3 => addr_data_f3,
342 372 start_date => start_date,
343 373 ---------------------------------------------------------------------------
344 374 debug_reg0 => debug_reg0,
345 375 debug_reg1 => debug_reg1,
346 376 debug_reg2 => debug_reg2,
347 377 debug_reg3 => debug_reg3,
348 378 debug_reg4 => debug_reg4,
349 379 debug_reg5 => debug_reg5,
350 380 debug_reg6 => debug_reg6,
351 381 debug_reg7 => debug_reg7);
352 382
353 383 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
354 384 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
355 385 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
356 386 -----------------------------------------------------------------------------
357 387 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
358 388 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
359 389 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
360 390 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
361 391
362 392
363 393 -----------------------------------------------------------------------------
364 394 lpp_waveform_1 : lpp_waveform
365 395 GENERIC MAP (
366 396 tech => inferred,
367 397 data_size => 6*16,
368 398 nb_data_by_buffer_size => nb_data_by_buffer_size,
369 399 nb_word_by_buffer_size => nb_word_by_buffer_size,
370 400 nb_snapshot_param_size => nb_snapshot_param_size,
371 401 delta_vector_size => delta_vector_size,
372 402 delta_vector_size_f0_2 => delta_vector_size_f0_2
373 403 )
374 404 PORT MAP (
375 405 clk => clk,
376 406 rstn => rstn,
377 407
378 408 reg_run => run,
379 409 reg_start_date => start_date,
380 410 reg_delta_snapshot => delta_snapshot,
381 411 reg_delta_f0 => delta_f0,
382 412 reg_delta_f0_2 => delta_f0_2,
383 413 reg_delta_f1 => delta_f1,
384 414 reg_delta_f2 => delta_f2,
385 415
386 416 enable_f0 => enable_f0,
387 417 enable_f1 => enable_f1,
388 418 enable_f2 => enable_f2,
389 419 enable_f3 => enable_f3,
390 420 burst_f0 => burst_f0,
391 421 burst_f1 => burst_f1,
392 422 burst_f2 => burst_f2,
393 423
394 424 nb_data_by_buffer => nb_data_by_buffer,
395 425 nb_word_by_buffer => nb_word_by_buffer,
396 426 nb_snapshot_param => nb_snapshot_param,
397 427 status_full => status_full,
398 428 status_full_ack => status_full_ack,
399 429 status_full_err => status_full_err,
400 430 status_new_err => status_new_err,
401 431
402 432 coarse_time => coarse_time,
403 433 fine_time => fine_time,
404 434
405 435 --f0
406 436 addr_data_f0 => addr_data_f0,
407 437 data_f0_in_valid => sample_f0_val,
408 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
438 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
409 439 --f1
410 440 addr_data_f1 => addr_data_f1,
411 441 data_f1_in_valid => sample_f1_val,
412 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
442 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
413 443 --f2
414 444 addr_data_f2 => addr_data_f2,
415 445 data_f2_in_valid => sample_f2_val,
416 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
446 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
417 447 --f3
418 448 addr_data_f3 => addr_data_f3,
419 449 data_f3_in_valid => sample_f3_val,
420 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
450 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
421 451 -- OUTPUT -- DMA interface
422 452 --f0
423 453 data_f0_addr_out => data_f0_addr_out_s,
424 454 data_f0_data_out => data_f0_data_out,
425 455 data_f0_data_out_valid => data_f0_data_out_valid_s,
426 456 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
427 457 data_f0_data_out_ren => data_f0_data_out_ren,
428 458 --f1
429 459 data_f1_addr_out => data_f1_addr_out_s,
430 460 data_f1_data_out => data_f1_data_out,
431 461 data_f1_data_out_valid => data_f1_data_out_valid_s,
432 462 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
433 463 data_f1_data_out_ren => data_f1_data_out_ren,
434 464 --f2
435 465 data_f2_addr_out => data_f2_addr_out_s,
436 466 data_f2_data_out => data_f2_data_out,
437 467 data_f2_data_out_valid => data_f2_data_out_valid_s,
438 468 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
439 469 data_f2_data_out_ren => data_f2_data_out_ren,
440 470 --f3
441 471 data_f3_addr_out => data_f3_addr_out_s,
442 472 data_f3_data_out => data_f3_data_out,
443 473 data_f3_data_out_valid => data_f3_data_out_valid_s,
444 474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
445 475 data_f3_data_out_ren => data_f3_data_out_ren,
446 476
447 --debug
477 -- debug SNAPSHOT_OUT
448 478 debug_f0_data => debug_f0_data,
449 479 debug_f0_data_valid => debug_f0_data_valid ,
450 480 debug_f1_data => debug_f1_data ,
451 481 debug_f1_data_valid => debug_f1_data_valid,
452 482 debug_f2_data => debug_f2_data ,
453 483 debug_f2_data_valid => debug_f2_data_valid ,
454 484 debug_f3_data => debug_f3_data ,
455 debug_f3_data_valid => debug_f3_data_valid
485 debug_f3_data_valid => debug_f3_data_valid,
486
487 -- debug FIFO_IN
488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
456 496
457 497 );
458 498
459 499
460 500 -----------------------------------------------------------------------------
501 -- DEBUG -- WFP OUT
502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
503 debug_f0_data_fifo_out <= data_f0_data_out;
504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
505 debug_f1_data_fifo_out <= data_f1_data_out;
506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
507 debug_f2_data_fifo_out <= data_f2_data_out;
508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
509 debug_f3_data_fifo_out <= data_f3_data_out;
510 -----------------------------------------------------------------------------
511
512
513 -----------------------------------------------------------------------------
461 514 -- TEMP
462 515 -----------------------------------------------------------------------------
463 516
464 517 PROCESS (clk, rstn)
465 518 BEGIN -- PROCESS
466 519 IF rstn = '0' THEN -- asynchronous reset (active low)
467 520 data_f0_data_out_valid <= '0';
468 521 data_f0_data_out_valid_burst <= '0';
469 522 data_f1_data_out_valid <= '0';
470 523 data_f1_data_out_valid_burst <= '0';
471 524 data_f2_data_out_valid <= '0';
472 525 data_f2_data_out_valid_burst <= '0';
473 526 data_f3_data_out_valid <= '0';
474 527 data_f3_data_out_valid_burst <= '0';
475 528 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
476 529 data_f0_data_out_valid <= data_f0_data_out_valid_s;
477 530 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
478 531 data_f1_data_out_valid <= data_f1_data_out_valid_s;
479 532 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
480 533 data_f2_data_out_valid <= data_f2_data_out_valid_s;
481 534 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
482 535 data_f3_data_out_valid <= data_f3_data_out_valid_s;
483 536 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
484 537 END IF;
485 538 END PROCESS;
486 539
487 540 data_f0_addr_out <= data_f0_addr_out_s;
488 541 data_f1_addr_out <= data_f1_addr_out_s;
489 542 data_f2_addr_out <= data_f2_addr_out_s;
490 543 data_f3_addr_out <= data_f3_addr_out_s;
491 544
492 545 -----------------------------------------------------------------------------
493 546 -- RoundRobin Selection For DMA
494 547 -----------------------------------------------------------------------------
495 548
496 549 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
497 550 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
498 551 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
499 552 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
500 553
501 554 RR_Arbiter_4_1 : RR_Arbiter_4
502 555 PORT MAP (
503 556 clk => clk,
504 557 rstn => rstn,
505 558 in_valid => dma_rr_valid,
506 559 out_grant => dma_rr_grant);
507 560
508 561
509 562 -----------------------------------------------------------------------------
510 563 -- in : dma_rr_grant
511 564 -- send
512 565 -- out : dma_sel
513 566 -- dma_valid_burst
514 567 -- dma_sel_valid
515 568 -----------------------------------------------------------------------------
516 569 PROCESS (clk, rstn)
517 570 BEGIN -- PROCESS
518 571 IF rstn = '0' THEN -- asynchronous reset (active low)
519 572 dma_sel <= (OTHERS => '0');
520 573 dma_send <= '0';
521 574 dma_valid_burst <= '0';
522 575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
523 576 -- IF dma_sel = "0000" OR dma_send = '1' THEN
524 577 IF dma_sel = "0000" OR dma_done = '1' THEN
525 578 dma_sel <= dma_rr_grant;
526 579 IF dma_rr_grant(0) = '1' THEN
527 580 dma_send <= '1';
528 581 dma_valid_burst <= data_f0_data_out_valid_burst;
529 582 dma_sel_valid <= data_f0_data_out_valid;
530 583 ELSIF dma_rr_grant(1) = '1' THEN
531 584 dma_send <= '1';
532 585 dma_valid_burst <= data_f1_data_out_valid_burst;
533 586 dma_sel_valid <= data_f1_data_out_valid;
534 587 ELSIF dma_rr_grant(2) = '1' THEN
535 588 dma_send <= '1';
536 589 dma_valid_burst <= data_f2_data_out_valid_burst;
537 590 dma_sel_valid <= data_f2_data_out_valid;
538 591 ELSIF dma_rr_grant(3) = '1' THEN
539 592 dma_send <= '1';
540 593 dma_valid_burst <= data_f3_data_out_valid_burst;
541 594 dma_sel_valid <= data_f3_data_out_valid;
542 595 END IF;
543 596 ELSE
544 597 dma_sel <= dma_sel;
545 598 dma_send <= '0';
546 599 END IF;
547 600 END IF;
548 601 END PROCESS;
549 602
550 603
551 604 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
552 605 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
553 606 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
554 607 data_f3_addr_out;
555 608
556 609 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
557 610 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
558 611 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
559 612 data_f3_data_out;
560
561 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
562 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
563 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
564 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
565 -- '0';
566
567 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
568 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
569 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
570 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
571 -- '0';
572
573 -- TODO
574 --dma_send <= dma_sel_valid OR dma_valid_burst;
575
576 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
577 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
578 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
579 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
580 613
581 614 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
582 615 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
583 616 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
584 617 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
585 618
619 dma_data_2 <= dma_data;
586 620
587 --PROCESS (clk, rstn)
588 --BEGIN -- PROCESS
589 -- IF rstn = '0' THEN -- asynchronous reset (active low)
590 -- ongoing_reg <= '0';
591 -- dma_sel_reg <= (OTHERS => '0');
592 -- dma_send_reg <= '0';
593 -- dma_valid_burst_reg <= '0';
594 -- dma_address_reg <= (OTHERS => '0');
595 -- dma_data_reg <= (OTHERS => '0');
596 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
597 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
598 -- ongoing_reg <= '1';
599 -- dma_valid_burst_reg <= dma_valid_burst;
600 -- dma_sel_reg <= dma_sel;
601 -- ELSE
602 -- IF dma_done = '1' THEN
603 -- ongoing_reg <= '0';
604 -- END IF;
605 -- END IF;
606 -- dma_send_reg <= dma_send;
607 -- dma_address_reg <= dma_address;
608 -- dma_data_reg <= dma_data;
609 -- END IF;
610 --END PROCESS;
611 621
612 dma_data_2 <= dma_data;
613 --PROCESS (clk, rstn)
614 --BEGIN -- PROCESS
615 -- IF rstn = '0' THEN -- asynchronous reset (active low)
616 -- dma_data_2 <= (OTHERS => '0');
617 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
618 -- dma_data_2 <= dma_data;
619
620 -- END IF;
621 --END PROCESS;
622
622 623
623 624
624 625 -----------------------------------------------------------------------------
626 -- DEBUG -- DMA IN
627 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
628 debug_f0_data_dma_in <= dma_data;
629 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
630 debug_f1_data_dma_in <= dma_data;
631 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
632 debug_f2_data_dma_in <= dma_data;
633 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
634 debug_f3_data_dma_in <= dma_data;
635 -----------------------------------------------------------------------------
636
637 -----------------------------------------------------------------------------
625 638 -- DMA
626 639 -----------------------------------------------------------------------------
627 640 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
628 641 GENERIC MAP (
629 642 tech => inferred,
630 643 hindex => hindex)
631 644 PORT MAP (
632 645 HCLK => clk,
633 646 HRESETn => rstn,
634 647 run => run,
635 648 AHB_Master_In => ahbi,
636 649 AHB_Master_Out => ahbo,
637 650
638 send => dma_send, --_reg,
639 valid_burst => dma_valid_burst, --_reg,
651 send => dma_send,
652 valid_burst => dma_valid_burst,
640 653 done => dma_done,
641 654 ren => dma_ren,
642 address => dma_address, --_reg,
643 data => dma_data_2); --_reg);
655 address => dma_address,
656 data => dma_data_2);
644 657
645 658 -----------------------------------------------------------------------------
646 659 -- Matrix Spectral - TODO
647 660 -----------------------------------------------------------------------------
648 661 -----------------------------------------------------------------------------
649 662 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
650 663 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
651 664 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
652 665 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
653 666 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
654 667 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
655 668
656 669 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
657 670 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
658 671 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
659 672 -------------------------------------------------------------------------------
660 673 --lpp_lfr_ms_1: lpp_lfr_ms
661 674 -- GENERIC MAP (
662 675 -- hindex => hindex_ms)
663 676 -- PORT MAP (
664 677 -- clk => clk,
665 678 -- rstn => rstn,
666 679 -- sample_f0_wen => sample_f0_wen,
667 680 -- sample_f0_wdata => sample_f0_wdata,
668 681 -- sample_f1_wen => sample_f1_wen,
669 682 -- sample_f1_wdata => sample_f1_wdata,
670 683 -- sample_f3_wen => sample_f3_wen,
671 684 -- sample_f3_wdata => sample_f3_wdata,
672 685 -- AHB_Master_In => ahbi_ms,
673 686 -- AHB_Master_Out => ahbo_ms,
674 687
675 688 -- ready_matrix_f0_0 => ready_matrix_f0_0,
676 689 -- ready_matrix_f0_1 => ready_matrix_f0_1,
677 690 -- ready_matrix_f1 => ready_matrix_f1,
678 691 -- ready_matrix_f2 => ready_matrix_f2,
679 692 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
680 693 -- error_bad_component_error => error_bad_component_error,
681 694 -- debug_reg => debug_reg,
682 695 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
683 696 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
684 697 -- status_ready_matrix_f1 => status_ready_matrix_f1,
685 698 -- status_ready_matrix_f2 => status_ready_matrix_f2,
686 699 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
687 700 -- status_error_bad_component_error => status_error_bad_component_error,
688 701 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
689 702 -- config_active_interruption_onError => config_active_interruption_onError,
690 703 -- addr_matrix_f0_0 => addr_matrix_f0_0,
691 704 -- addr_matrix_f0_1 => addr_matrix_f0_1,
692 705 -- addr_matrix_f1 => addr_matrix_f1,
693 706 -- addr_matrix_f2 => addr_matrix_f2);
694 707
695 708 END beh;
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@@ -1,493 +1,493
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_amba.ALL;
32 32 USE lpp.apb_devices_list.ALL;
33 33 USE lpp.lpp_memory.ALL;
34 34 LIBRARY techmap;
35 35 USE techmap.gencomp.ALL;
36 36
37 37 ENTITY lpp_lfr_apbreg IS
38 38 GENERIC (
39 39 nb_data_by_buffer_size : INTEGER := 11;
40 40 nb_word_by_buffer_size : INTEGER := 11;
41 41 nb_snapshot_param_size : INTEGER := 11;
42 42 delta_vector_size : INTEGER := 20;
43 43 delta_vector_size_f0_2 : INTEGER := 3;
44 44
45 45 pindex : INTEGER := 4;
46 46 paddr : INTEGER := 4;
47 47 pmask : INTEGER := 16#fff#;
48 48 pirq_ms : INTEGER := 0;
49 49 pirq_wfp : INTEGER := 1;
50 50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
51 51 PORT (
52 52 -- AMBA AHB system signals
53 53 HCLK : IN STD_ULOGIC;
54 54 HRESETn : IN STD_ULOGIC;
55 55
56 56 -- AMBA APB Slave Interface
57 57 apbi : IN apb_slv_in_type;
58 58 apbo : OUT apb_slv_out_type;
59 59
60 60 ---------------------------------------------------------------------------
61 61 -- Spectral Matrix Reg
62 62 -- IN
63 63 ready_matrix_f0_0 : IN STD_LOGIC;
64 64 ready_matrix_f0_1 : IN STD_LOGIC;
65 65 ready_matrix_f1 : IN STD_LOGIC;
66 66 ready_matrix_f2 : IN STD_LOGIC;
67 67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 68 error_bad_component_error : IN STD_LOGIC;
69 69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70
71 71 -- OUT
72 72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 77 status_error_bad_component_error : OUT STD_LOGIC;
78 78
79 79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 80 config_active_interruption_onError : OUT STD_LOGIC;
81 81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 ---------------------------------------------------------------------------
86 86 ---------------------------------------------------------------------------
87 87 -- WaveForm picker Reg
88 88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92 92
93 93 -- OUT
94 94 data_shaping_BW : OUT STD_LOGIC;
95 95 data_shaping_SP0 : OUT STD_LOGIC;
96 96 data_shaping_SP1 : OUT STD_LOGIC;
97 97 data_shaping_R0 : OUT STD_LOGIC;
98 98 data_shaping_R1 : OUT STD_LOGIC;
99 99
100 100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108 108
109 109 enable_f0 : OUT STD_LOGIC;
110 110 enable_f1 : OUT STD_LOGIC;
111 111 enable_f2 : OUT STD_LOGIC;
112 112 enable_f3 : OUT STD_LOGIC;
113 113
114 114 burst_f0 : OUT STD_LOGIC;
115 115 burst_f1 : OUT STD_LOGIC;
116 116 burst_f2 : OUT STD_LOGIC;
117 117
118 118 run : OUT STD_LOGIC;
119 119
120 120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
125 125 ---------------------------------------------------------------------------
126 126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
134 134
135 135 ---------------------------------------------------------------------------
136 136 );
137 137
138 138 END lpp_lfr_apbreg;
139 139
140 140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
141 141
142 142 CONSTANT REVISION : INTEGER := 1;
143 143
144 144 CONSTANT pconfig : apb_config_type := (
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
146 146 1 => apb_iobar(paddr, pmask));
147 147
148 148 TYPE lpp_SpectralMatrix_regs IS RECORD
149 149 config_active_interruption_onNewMatrix : STD_LOGIC;
150 150 config_active_interruption_onError : STD_LOGIC;
151 151 status_ready_matrix_f0_0 : STD_LOGIC;
152 152 status_ready_matrix_f0_1 : STD_LOGIC;
153 153 status_ready_matrix_f1 : STD_LOGIC;
154 154 status_ready_matrix_f2 : STD_LOGIC;
155 155 status_error_anticipating_empty_fifo : STD_LOGIC;
156 156 status_error_bad_component_error : STD_LOGIC;
157 157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 END RECORD;
162 162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
163 163
164 164 TYPE lpp_WaveformPicker_regs IS RECORD
165 165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 168 data_shaping_BW : STD_LOGIC;
169 169 data_shaping_SP0 : STD_LOGIC;
170 170 data_shaping_SP1 : STD_LOGIC;
171 171 data_shaping_R0 : STD_LOGIC;
172 172 data_shaping_R1 : STD_LOGIC;
173 173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
175 175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
176 176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
178 178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
179 179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
180 180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
181 181 enable_f0 : STD_LOGIC;
182 182 enable_f1 : STD_LOGIC;
183 183 enable_f2 : STD_LOGIC;
184 184 enable_f3 : STD_LOGIC;
185 185 burst_f0 : STD_LOGIC;
186 186 burst_f1 : STD_LOGIC;
187 187 burst_f2 : STD_LOGIC;
188 188 run : STD_LOGIC;
189 189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
194 194 END RECORD;
195 195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
196 196
197 197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198
199 199 -----------------------------------------------------------------------------
200 200 -- IRQ
201 201 -----------------------------------------------------------------------------
202 202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
203 203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
207 207 SIGNAL ored_irq_wfp : STD_LOGIC;
208 208
209 209 BEGIN -- beh
210 210
211 211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
212 212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
213 213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
214 214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
215 215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
216 216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
217 217
218 218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
219 219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
220 220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
221 221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
222 222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
223 223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
224 224
225 225
226 226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
227 227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
228 228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
229 229 data_shaping_R0 <= reg_wp.data_shaping_R0;
230 230 data_shaping_R1 <= reg_wp.data_shaping_R1;
231 231
232 232 delta_snapshot <= reg_wp.delta_snapshot;
233 233 delta_f0 <= reg_wp.delta_f0;
234 234 delta_f0_2 <= reg_wp.delta_f0_2;
235 235 delta_f1 <= reg_wp.delta_f1;
236 236 delta_f2 <= reg_wp.delta_f2;
237 237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
238 238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
239 239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
240 240
241 241 enable_f0 <= reg_wp.enable_f0;
242 242 enable_f1 <= reg_wp.enable_f1;
243 243 enable_f2 <= reg_wp.enable_f2;
244 244 enable_f3 <= reg_wp.enable_f3;
245 245
246 246 burst_f0 <= reg_wp.burst_f0;
247 247 burst_f1 <= reg_wp.burst_f1;
248 248 burst_f2 <= reg_wp.burst_f2;
249 249
250 250 run <= reg_wp.run;
251 251
252 252 addr_data_f0 <= reg_wp.addr_data_f0;
253 253 addr_data_f1 <= reg_wp.addr_data_f1;
254 254 addr_data_f2 <= reg_wp.addr_data_f2;
255 255 addr_data_f3 <= reg_wp.addr_data_f3;
256 256
257 257 start_date <= reg_wp.start_date;
258 258
259 259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
260 260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
261 261 BEGIN -- PROCESS lpp_dma_top
262 262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
263 263 reg_sp.config_active_interruption_onNewMatrix <= '0';
264 264 reg_sp.config_active_interruption_onError <= '0';
265 265 reg_sp.status_ready_matrix_f0_0 <= '0';
266 266 reg_sp.status_ready_matrix_f0_1 <= '0';
267 267 reg_sp.status_ready_matrix_f1 <= '0';
268 268 reg_sp.status_ready_matrix_f2 <= '0';
269 269 reg_sp.status_error_anticipating_empty_fifo <= '0';
270 270 reg_sp.status_error_bad_component_error <= '0';
271 271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
272 272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
273 273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
274 274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
275 275 prdata <= (OTHERS => '0');
276 276
277 277 apbo.pirq <= (OTHERS => '0');
278 278
279 279 status_full_ack <= (OTHERS => '0');
280 280
281 281 reg_wp.data_shaping_BW <= '0';
282 282 reg_wp.data_shaping_SP0 <= '0';
283 283 reg_wp.data_shaping_SP1 <= '0';
284 284 reg_wp.data_shaping_R0 <= '0';
285 285 reg_wp.data_shaping_R1 <= '0';
286 286 reg_wp.enable_f0 <= '0';
287 287 reg_wp.enable_f1 <= '0';
288 288 reg_wp.enable_f2 <= '0';
289 289 reg_wp.enable_f3 <= '0';
290 290 reg_wp.burst_f0 <= '0';
291 291 reg_wp.burst_f1 <= '0';
292 292 reg_wp.burst_f2 <= '0';
293 293 reg_wp.run <= '0';
294 294 reg_wp.addr_data_f0 <= (OTHERS => '0');
295 295 reg_wp.addr_data_f1 <= (OTHERS => '0');
296 296 reg_wp.addr_data_f2 <= (OTHERS => '0');
297 297 reg_wp.addr_data_f3 <= (OTHERS => '0');
298 298 reg_wp.status_full <= (OTHERS => '0');
299 299 reg_wp.status_full_err <= (OTHERS => '0');
300 300 reg_wp.status_new_err <= (OTHERS => '0');
301 301 reg_wp.delta_snapshot <= (OTHERS => '0');
302 302 reg_wp.delta_f0 <= (OTHERS => '0');
303 303 reg_wp.delta_f0_2 <= (OTHERS => '0');
304 304 reg_wp.delta_f1 <= (OTHERS => '0');
305 305 reg_wp.delta_f2 <= (OTHERS => '0');
306 306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
307 307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
308 308 reg_wp.start_date <= (OTHERS => '0');
309 309
310 310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
311 311 status_full_ack <= (OTHERS => '0');
312 312
313 313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
314 314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
315 315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
316 316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
317 317
318 318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
319 319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
320 320 all_status: FOR I IN 3 DOWNTO 0 LOOP
321 321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
322 322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
323 323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
324 324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
325 325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
326 326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
327 327 END LOOP all_status;
328 328
329 329 paddr := "000000";
330 330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
331 331 prdata <= (OTHERS => '0');
332 332 IF apbi.psel(pindex) = '1' THEN
333 333 -- APB DMA READ --
334 334 CASE paddr(7 DOWNTO 2) IS
335 335 --
336 336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
337 337 prdata(1) <= reg_sp.config_active_interruption_onError;
338 338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
339 339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
340 340 prdata(2) <= reg_sp.status_ready_matrix_f1;
341 341 prdata(3) <= reg_sp.status_ready_matrix_f2;
342 342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
343 343 prdata(5) <= reg_sp.status_error_bad_component_error;
344 344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
345 345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
346 346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
347 347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
348 348 WHEN "000110" => prdata <= debug_reg;
349 349 --
350 350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
351 351 prdata(1) <= reg_wp.data_shaping_SP0;
352 352 prdata(2) <= reg_wp.data_shaping_SP1;
353 353 prdata(3) <= reg_wp.data_shaping_R0;
354 354 prdata(4) <= reg_wp.data_shaping_R1;
355 355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
356 356 prdata(1) <= reg_wp.enable_f1;
357 357 prdata(2) <= reg_wp.enable_f2;
358 358 prdata(3) <= reg_wp.enable_f3;
359 359 prdata(4) <= reg_wp.burst_f0;
360 360 prdata(5) <= reg_wp.burst_f1;
361 361 prdata(6) <= reg_wp.burst_f2;
362 362 prdata(7) <= reg_wp.run;
363 363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
364 364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
365 365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
366 366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
367 367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
368 368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
369 369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
370 370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
371 371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
372 372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
373 373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
374 374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
375 375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
376 376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
377 377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
378 378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
379 379 ----------------------------------------------------
380 380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
382 382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
383 383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
384 384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
385 385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
386 386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
387 387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
388 388 ----------------------------------------------------
389 389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
390 390 WHEN OTHERS => NULL;
391 391 END CASE;
392 392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
393 393 -- APB DMA WRITE --
394 394 CASE paddr(7 DOWNTO 2) IS
395 395 --
396 396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
397 397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
398 398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
399 399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
400 400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
401 401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
402 402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
403 403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
404 404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
405 405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
406 406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
407 407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
408 408 --
409 409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
410 410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
411 411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
412 412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
413 413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
414 414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
415 415 reg_wp.enable_f1 <= apbi.pwdata(1);
416 416 reg_wp.enable_f2 <= apbi.pwdata(2);
417 417 reg_wp.enable_f3 <= apbi.pwdata(3);
418 418 reg_wp.burst_f0 <= apbi.pwdata(4);
419 419 reg_wp.burst_f1 <= apbi.pwdata(5);
420 420 reg_wp.burst_f2 <= apbi.pwdata(6);
421 421 reg_wp.run <= apbi.pwdata(7);
422 422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
423 423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
424 424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
425 425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
426 426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
427 427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
428 428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
429 429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
430 430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
431 431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
432 432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
433 433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
435 435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
436 436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
438 438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
439 439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
440 440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
441 441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
442 442 --
443 443 WHEN OTHERS => NULL;
444 444 END CASE;
445 445 END IF;
446 446 END IF;
447 447
448 448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
449 449 ready_matrix_f0_1 OR
450 450 ready_matrix_f1 OR
451 451 ready_matrix_f2)
452 452 )
453 453 OR
454 454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
455 455 error_bad_component_error)
456 456 ));
457 457
458 458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
459 459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
460 460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
461 461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
462 462 -- );
463 463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
464 464
465 465 END IF;
466 466 END PROCESS lpp_lfr_apbreg;
467 467
468 468 apbo.pindex <= pindex;
469 469 apbo.pconfig <= pconfig;
470 470 apbo.prdata <= prdata;
471 471
472 472 -----------------------------------------------------------------------------
473 473 -- IRQ
474 474 -----------------------------------------------------------------------------
475 475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
476 476
477 477 PROCESS (HCLK, HRESETn)
478 478 BEGIN -- PROCESS
479 479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
480 480 irq_wfp_reg <= (OTHERS => '0');
481 481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
482 482 irq_wfp_reg <= irq_wfp_reg_s;
483 483 END IF;
484 484 END PROCESS;
485 485
486 486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
487 487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
488 488 END GENERATE all_irq_wfp;
489 489
490 490 irq_wfp_ZERO <= (OTHERS => '0');
491 491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
492 492
493 493 END beh;
Show file before | Show file after | Hide comments
@@ -1,221 +1,252
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16
17 17 COMPONENT lpp_lfr_ms
18 18 GENERIC (
19 19 hindex : INTEGER);
20 20 PORT (
21 21 clk : IN STD_LOGIC;
22 22 rstn : IN STD_LOGIC;
23 23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 29 AHB_Master_In : IN AHB_Mst_In_Type;
30 30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 33 ready_matrix_f1 : OUT STD_LOGIC;
34 34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 36 error_bad_component_error : OUT STD_LOGIC;
37 37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 40 status_ready_matrix_f1 : IN STD_LOGIC;
41 41 status_ready_matrix_f2 : IN STD_LOGIC;
42 42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 43 status_error_bad_component_error : IN STD_LOGIC;
44 44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 45 config_active_interruption_onError : IN STD_LOGIC;
46 46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 50 END COMPONENT;
51 51
52 52 COMPONENT lpp_lfr_filter
53 53 GENERIC (
54 54 Mem_use : INTEGER);
55 55 PORT (
56 56 sample : IN Samples(7 DOWNTO 0);
57 57 sample_val : IN STD_LOGIC;
58 58 clk : IN STD_LOGIC;
59 59 rstn : IN STD_LOGIC;
60 60 data_shaping_SP0 : IN STD_LOGIC;
61 61 data_shaping_SP1 : IN STD_LOGIC;
62 62 data_shaping_R0 : IN STD_LOGIC;
63 63 data_shaping_R1 : IN STD_LOGIC;
64 64 sample_f0_val : OUT STD_LOGIC;
65 65 sample_f1_val : OUT STD_LOGIC;
66 66 sample_f2_val : OUT STD_LOGIC;
67 67 sample_f3_val : OUT STD_LOGIC;
68 68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 72 END COMPONENT;
73 73
74 74 COMPONENT lpp_lfr
75 75 GENERIC (
76 76 Mem_use : INTEGER;
77 77 nb_data_by_buffer_size : INTEGER;
78 78 nb_word_by_buffer_size : INTEGER;
79 79 nb_snapshot_param_size : INTEGER;
80 80 delta_vector_size : INTEGER;
81 81 delta_vector_size_f0_2 : INTEGER;
82 82 pindex : INTEGER;
83 83 paddr : INTEGER;
84 84 pmask : INTEGER;
85 85 pirq_ms : INTEGER;
86 86 pirq_wfp : INTEGER;
87 87 hindex : INTEGER;
88 88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
89 89 );
90 90 PORT (
91 91 clk : IN STD_LOGIC;
92 92 rstn : IN STD_LOGIC;
93 93 sample_B : IN Samples14v(2 DOWNTO 0);
94 94 sample_E : IN Samples14v(4 DOWNTO 0);
95 95 sample_val : IN STD_LOGIC;
96 96 apbi : IN apb_slv_in_type;
97 97 apbo : OUT apb_slv_out_type;
98 98 ahbi : IN AHB_Mst_In_Type;
99 99 ahbo : OUT AHB_Mst_Out_Type;
100 100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 102 data_shaping_BW : OUT STD_LOGIC;
103 103
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC );
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC;
113
114 -- debug FIFO_IN
115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123
124 --debug FIFO OUT
125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133
134 --debug DMA IN
135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 );
113 144 END COMPONENT;
114 145
115 146 COMPONENT lpp_lfr_apbreg
116 147 GENERIC (
117 148 nb_data_by_buffer_size : INTEGER;
118 149 nb_word_by_buffer_size : INTEGER;
119 150 nb_snapshot_param_size : INTEGER;
120 151 delta_vector_size : INTEGER;
121 152 delta_vector_size_f0_2 : INTEGER;
122 153 pindex : INTEGER;
123 154 paddr : INTEGER;
124 155 pmask : INTEGER;
125 156 pirq_ms : INTEGER;
126 157 pirq_wfp : INTEGER;
127 158 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
128 159 PORT (
129 160 HCLK : IN STD_ULOGIC;
130 161 HRESETn : IN STD_ULOGIC;
131 162 apbi : IN apb_slv_in_type;
132 163 apbo : OUT apb_slv_out_type;
133 164 ready_matrix_f0_0 : IN STD_LOGIC;
134 165 ready_matrix_f0_1 : IN STD_LOGIC;
135 166 ready_matrix_f1 : IN STD_LOGIC;
136 167 ready_matrix_f2 : IN STD_LOGIC;
137 168 error_anticipating_empty_fifo : IN STD_LOGIC;
138 169 error_bad_component_error : IN STD_LOGIC;
139 170 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 171 status_ready_matrix_f0_0 : OUT STD_LOGIC;
141 172 status_ready_matrix_f0_1 : OUT STD_LOGIC;
142 173 status_ready_matrix_f1 : OUT STD_LOGIC;
143 174 status_ready_matrix_f2 : OUT STD_LOGIC;
144 175 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
145 176 status_error_bad_component_error : OUT STD_LOGIC;
146 177 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
147 178 config_active_interruption_onError : OUT STD_LOGIC;
148 179 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 180 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 181 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 182 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 183 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
153 184 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
154 185 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
155 186 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
156 187 data_shaping_BW : OUT STD_LOGIC;
157 188 data_shaping_SP0 : OUT STD_LOGIC;
158 189 data_shaping_SP1 : OUT STD_LOGIC;
159 190 data_shaping_R0 : OUT STD_LOGIC;
160 191 data_shaping_R1 : OUT STD_LOGIC;
161 192 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 193 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 194 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 195 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 196 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 197 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 198 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 199 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 200 enable_f0 : OUT STD_LOGIC;
170 201 enable_f1 : OUT STD_LOGIC;
171 202 enable_f2 : OUT STD_LOGIC;
172 203 enable_f3 : OUT STD_LOGIC;
173 204 burst_f0 : OUT STD_LOGIC;
174 205 burst_f1 : OUT STD_LOGIC;
175 206 burst_f2 : OUT STD_LOGIC;
176 207 run : OUT STD_LOGIC;
177 208 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 209 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 210 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 211 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 212 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
182 213 ---------------------------------------------------------------------------
183 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
190 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
214 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
218 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
219 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
220 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
221 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
191 222 END COMPONENT;
192
223
193 224 COMPONENT lpp_top_ms
194 225 GENERIC (
195 226 Mem_use : INTEGER;
196 227 nb_burst_available_size : INTEGER;
197 228 nb_snapshot_param_size : INTEGER;
198 229 delta_snapshot_size : INTEGER;
199 230 delta_f2_f0_size : INTEGER;
200 231 delta_f2_f1_size : INTEGER;
201 232 pindex : INTEGER;
202 233 paddr : INTEGER;
203 234 pmask : INTEGER;
204 235 pirq_ms : INTEGER;
205 236 pirq_wfp : INTEGER;
206 237 hindex_wfp : INTEGER;
207 238 hindex_ms : INTEGER);
208 239 PORT (
209 240 clk : IN STD_LOGIC;
210 241 rstn : IN STD_LOGIC;
211 242 sample_B : IN Samples14v(2 DOWNTO 0);
212 243 sample_E : IN Samples14v(4 DOWNTO 0);
213 244 sample_val : IN STD_LOGIC;
214 245 apbi : IN apb_slv_in_type;
215 246 apbo : OUT apb_slv_out_type;
216 247 ahbi_ms : IN AHB_Mst_In_Type;
217 248 ahbo_ms : OUT AHB_Mst_Out_Type;
218 249 data_shaping_BW : OUT STD_LOGIC);
219 250 END COMPONENT;
220 251
221 252 END lpp_lfr_pkg;
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@@ -1,472 +1,495
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_waveform IS
40 40
41 41 GENERIC (
42 42 tech : INTEGER := inferred;
43 43 data_size : INTEGER := 96; --16*6
44 44 nb_data_by_buffer_size : INTEGER := 11;
45 45 nb_word_by_buffer_size : INTEGER := 11;
46 46 nb_snapshot_param_size : INTEGER := 11;
47 47 delta_vector_size : INTEGER := 20;
48 48 delta_vector_size_f0_2 : INTEGER := 3);
49 49
50 50 PORT (
51 51 clk : IN STD_LOGIC;
52 52 rstn : IN STD_LOGIC;
53 53
54 54 ---- AMBA AHB Master Interface
55 55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57 57
58 58 --config
59 59 reg_run : IN STD_LOGIC;
60 60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 66
67 67 enable_f0 : IN STD_LOGIC;
68 68 enable_f1 : IN STD_LOGIC;
69 69 enable_f2 : IN STD_LOGIC;
70 70 enable_f3 : IN STD_LOGIC;
71 71
72 72 burst_f0 : IN STD_LOGIC;
73 73 burst_f1 : IN STD_LOGIC;
74 74 burst_f2 : IN STD_LOGIC;
75 75
76 76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83 ---------------------------------------------------------------------------
84 84 -- INPUT
85 85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87 87
88 88 --f0
89 89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 data_f0_in_valid : IN STD_LOGIC;
91 91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 92 --f1
93 93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 data_f1_in_valid : IN STD_LOGIC;
95 95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 96 --f2
97 97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 data_f2_in_valid : IN STD_LOGIC;
99 99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 100 --f3
101 101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 data_f3_in_valid : IN STD_LOGIC;
103 103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 104
105 105 ---------------------------------------------------------------------------
106 106 -- OUTPUT
107 107 --f0
108 108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110 data_f0_data_out_valid : OUT STD_LOGIC;
111 111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 112 data_f0_data_out_ren : IN STD_LOGIC;
113 113 --f1
114 114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 116 data_f1_data_out_valid : OUT STD_LOGIC;
117 117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 118 data_f1_data_out_ren : IN STD_LOGIC;
119 119 --f2
120 120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122 data_f2_data_out_valid : OUT STD_LOGIC;
123 123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 124 data_f2_data_out_ren : IN STD_LOGIC;
125 125 --f3
126 126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 data_f3_data_out_valid : OUT STD_LOGIC;
129 129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 130 data_f3_data_out_ren : IN STD_LOGIC;
131 131
132 --debug
132 --debug SNAPSHOT OUT
133 133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 134 debug_f0_data_valid : OUT STD_LOGIC;
135 135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 136 debug_f1_data_valid : OUT STD_LOGIC;
137 137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 138 debug_f2_data_valid : OUT STD_LOGIC;
139 139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 debug_f3_data_valid : OUT STD_LOGIC
140 debug_f3_data_valid : OUT STD_LOGIC;
141
142 --debug FIFO IN
143 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
144 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
145 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
146 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
147 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
149 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
151
141 152 );
142 153
143 154 END lpp_waveform;
144 155
145 156 ARCHITECTURE beh OF lpp_waveform IS
146 157 SIGNAL start_snapshot_f0 : STD_LOGIC;
147 158 SIGNAL start_snapshot_f1 : STD_LOGIC;
148 159 SIGNAL start_snapshot_f2 : STD_LOGIC;
149 160
150 161 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
151 162 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 163 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 164 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
154 165
155 166 SIGNAL data_f0_out_valid : STD_LOGIC;
156 167 SIGNAL data_f1_out_valid : STD_LOGIC;
157 168 SIGNAL data_f2_out_valid : STD_LOGIC;
158 169 SIGNAL data_f3_out_valid : STD_LOGIC;
159 170 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
160 171 --
161 172 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 173 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 174 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 175 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 176 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 177 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 178 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 179 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 180 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 181 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 182 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 183 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 184 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 185 --
175 186 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 187 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 188 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 189 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 190 --
180 191 SIGNAL run : STD_LOGIC;
181 192 --
182 193 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
183 194 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
184 195 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
185 196 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
186 197 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
187 198 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 199 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 200 --
190 201
191 202 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
192 203 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 204 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 205 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 206
196 207 BEGIN -- beh
197 208
198 209 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
199 210 GENERIC MAP (
200 211 delta_vector_size => delta_vector_size,
201 212 delta_vector_size_f0_2 => delta_vector_size_f0_2
202 213 )
203 214 PORT MAP (
204 215 clk => clk,
205 216 rstn => rstn,
206 217 reg_run => reg_run,
207 218 reg_start_date => reg_start_date,
208 219 reg_delta_snapshot => reg_delta_snapshot,
209 220 reg_delta_f0 => reg_delta_f0,
210 221 reg_delta_f0_2 => reg_delta_f0_2,
211 222 reg_delta_f1 => reg_delta_f1,
212 223 reg_delta_f2 => reg_delta_f2,
213 224 coarse_time => coarse_time(30 DOWNTO 0),
214 225 data_f0_valid => data_f0_in_valid,
215 226 data_f2_valid => data_f2_in_valid,
216 227 start_snapshot_f0 => start_snapshot_f0,
217 228 start_snapshot_f1 => start_snapshot_f1,
218 229 start_snapshot_f2 => start_snapshot_f2,
219 230 wfp_on => run);
220 231
221 232 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
222 233 GENERIC MAP (
223 234 data_size => data_size,
224 235 nb_snapshot_param_size => nb_snapshot_param_size)
225 236 PORT MAP (
226 237 clk => clk,
227 238 rstn => rstn,
228 239 run => run,
229 240 enable => enable_f0,
230 241 burst_enable => burst_f0,
231 242 nb_snapshot_param => nb_snapshot_param,
232 243 start_snapshot => start_snapshot_f0,
233 244 data_in => data_f0_in,
234 245 data_in_valid => data_f0_in_valid,
235 246 data_out => data_f0_out,
236 247 data_out_valid => data_f0_out_valid);
237 248
238 249 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
239 250
240 251 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
241 252 GENERIC MAP (
242 253 data_size => data_size,
243 254 nb_snapshot_param_size => nb_snapshot_param_size+1)
244 255 PORT MAP (
245 256 clk => clk,
246 257 rstn => rstn,
247 258 run => run,
248 259 enable => enable_f1,
249 260 burst_enable => burst_f1,
250 261 nb_snapshot_param => nb_snapshot_param_more_one,
251 262 start_snapshot => start_snapshot_f1,
252 263 data_in => data_f1_in,
253 264 data_in_valid => data_f1_in_valid,
254 265 data_out => data_f1_out,
255 266 data_out_valid => data_f1_out_valid);
256 267
257 268 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
258 269 GENERIC MAP (
259 270 data_size => data_size,
260 271 nb_snapshot_param_size => nb_snapshot_param_size+1)
261 272 PORT MAP (
262 273 clk => clk,
263 274 rstn => rstn,
264 275 run => run,
265 276 enable => enable_f2,
266 277 burst_enable => burst_f2,
267 278 nb_snapshot_param => nb_snapshot_param_more_one,
268 279 start_snapshot => start_snapshot_f2,
269 280 data_in => data_f2_in,
270 281 data_in_valid => data_f2_in_valid,
271 282 data_out => data_f2_out,
272 283 data_out_valid => data_f2_out_valid);
273 284
274 285 lpp_waveform_burst_f3 : lpp_waveform_burst
275 286 GENERIC MAP (
276 287 data_size => data_size)
277 288 PORT MAP (
278 289 clk => clk,
279 290 rstn => rstn,
280 291 run => run,
281 292 enable => enable_f3,
282 293 data_in => data_f3_in,
283 294 data_in_valid => data_f3_in_valid,
284 295 data_out => data_f3_out,
285 296 data_out_valid => data_f3_out_valid);
286 297
287 298 -----------------------------------------------------------------------------
288 -- DEBUG
299 -- DEBUG -- SNAPSHOT OUT
289 300 debug_f0_data_valid <= data_f0_out_valid;
290 301 debug_f0_data <= data_f0_out;
291 302 debug_f1_data_valid <= data_f1_out_valid;
292 303 debug_f1_data <= data_f1_out;
293 304 debug_f2_data_valid <= data_f2_out_valid;
294 305 debug_f2_data <= data_f2_out;
295 306 debug_f3_data_valid <= data_f3_out_valid;
296 307 debug_f3_data <= data_f3_out;
297 308 -----------------------------------------------------------------------------
298 309
299 310 PROCESS (clk, rstn)
300 311 BEGIN -- PROCESS
301 312 IF rstn = '0' THEN -- asynchronous reset (active low)
302 313 time_reg1 <= (OTHERS => '0');
303 314 time_reg2 <= (OTHERS => '0');
304 315 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
305 316 time_reg1 <= fine_time & coarse_time;
306 317 time_reg2 <= time_reg1;
307 318 END IF;
308 319 END PROCESS;
309 320
310 321 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
311 322 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
312 323 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
313 324 PORT MAP (
314 325 HCLK => clk,
315 326 HRESETn => rstn,
316 327 run => run,
317 328 valid_in => valid_in(I),
318 329 ack_in => valid_ack(I),
319 330 time_in => time_reg2, -- Todo
320 331 valid_out => valid_out(I),
321 332 time_out => time_out(I), -- Todo
322 333 error => status_new_err(I));
323 334 END GENERATE all_input_valid;
324 335
325 336 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
326 337 data_out(0, I) <= data_f0_out(I);
327 338 data_out(1, I) <= data_f1_out(I);
328 339 data_out(2, I) <= data_f2_out(I);
329 340 data_out(3, I) <= data_f3_out(I);
330 341 END GENERATE all_bit_of_data_out;
331 342
332 343 -----------------------------------------------------------------------------
333 344 -- TODO : debug
334 345 -----------------------------------------------------------------------------
335 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
336 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
337 time_out_2(J,I) <= time_out(J)(I);
346 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
347 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
348 time_out_2(J, I) <= time_out(J)(I);
338 349 END GENERATE all_sample_of_time_out;
339 350 END GENERATE all_bit_of_time_out;
340 351
341 352 -- DEBUG --
342 353 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
343 354 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
344 355 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
345 356 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
346 357
347 358 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
348 359 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
349 360 -- time_out_2(J, I) <= time_out_debug(J)(I);
350 361 -- END GENERATE all_sample_of_time_out;
351 362 --END GENERATE all_bit_of_time_out;
352 363 -- DEBUG --
353
364
354 365 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
355 366 GENERIC MAP (tech => tech,
356 367 nb_data_by_buffer_size => nb_data_by_buffer_size)
357 368 PORT MAP (
358 369 clk => clk,
359 370 rstn => rstn,
360 371 run => run,
361 372 nb_data_by_buffer => nb_data_by_buffer,
362 373 data_in_valid => valid_out,
363 374 data_in_ack => valid_ack,
364 375 data_in => data_out,
365 376 time_in => time_out_2,
366 377
367 378 data_out => wdata,
368 379 data_out_wen => data_wen,
369 380 full_almost => full_almost,
370 381 full => full);
371 382
383 -----------------------------------------------------------------------------
384 -- DEBUG -- SNAPSHOT IN
385 debug_f0_data_fifo_in_valid <= NOT data_wen(0);
386 debug_f0_data_fifo_in <= wdata;
387 debug_f1_data_fifo_in_valid <= NOT data_wen(1);
388 debug_f1_data_fifo_in <= wdata;
389 debug_f2_data_fifo_in_valid <= NOT data_wen(2);
390 debug_f2_data_fifo_in <= wdata;
391 debug_f3_data_fifo_in_valid <= NOT data_wen(3);
392 debug_f3_data_fifo_in <= wdata;
393 -----------------------------------------------------------------------------
394
372 395 lpp_waveform_fifo_1 : lpp_waveform_fifo
373 396 GENERIC MAP (tech => tech)
374 397 PORT MAP (
375 398 clk => clk,
376 399 rstn => rstn,
377 400 run => run,
378 401
379 402 empty => s_empty,
380 403 empty_almost => s_empty_almost,
381 404 data_ren => s_data_ren,
382 405 rdata => s_rdata,
383 406
384 407
385 408 full_almost => full_almost,
386 409 full => full,
387 410 data_wen => data_wen,
388 411 wdata => wdata);
389 412
390 413 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
391 414 GENERIC MAP (tech => tech)
392 415 PORT MAP (
393 416 clk => clk,
394 417 rstn => rstn,
395 418 run => run,
396 419 o_empty_almost => empty_almost,
397 420 o_empty => empty,
398 421
399 422 o_data_ren => data_ren,
400 423 o_rdata_0 => data_f0_data_out,
401 424 o_rdata_1 => data_f1_data_out,
402 425 o_rdata_2 => data_f2_data_out,
403 426 o_rdata_3 => data_f3_data_out,
404 427
405 428 i_empty_almost => s_empty_almost,
406 429 i_empty => s_empty,
407 430 i_data_ren => s_data_ren,
408 431 i_rdata => s_rdata);
409 432
410 433
411 434 --data_f0_data_out <= rdata;
412 435 --data_f1_data_out <= rdata;
413 436 --data_f2_data_out <= rdata;
414 437 --data_f3_data_out <= rdata;
415 438
416 439 data_ren <= data_f3_data_out_ren &
417 440 data_f2_data_out_ren &
418 441 data_f1_data_out_ren &
419 442 data_f0_data_out_ren;
420 443
421 444 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
422 445 GENERIC MAP (
423 446 nb_data_by_buffer_size => nb_word_by_buffer_size)
424 447 PORT MAP (
425 448 clk => clk,
426 449 rstn => rstn,
427 450 run => run,
428 451
429 452 -------------------------------------------------------------------------
430 453 -- CONFIG
431 454 -------------------------------------------------------------------------
432 455 nb_data_by_buffer => nb_word_by_buffer,
433 456
434 457 addr_data_f0 => addr_data_f0,
435 458 addr_data_f1 => addr_data_f1,
436 459 addr_data_f2 => addr_data_f2,
437 460 addr_data_f3 => addr_data_f3,
438 461 -------------------------------------------------------------------------
439 462 -- CTRL
440 463 -------------------------------------------------------------------------
441 464 -- IN
442 465 empty => empty,
443 466 empty_almost => empty_almost,
444 467 data_ren => data_ren,
445 468
446 469 -------------------------------------------------------------------------
447 470 -- STATUS
448 471 -------------------------------------------------------------------------
449 472 status_full => status_full,
450 473 status_full_ack => status_full_ack,
451 474 status_full_err => status_full_err,
452 475
453 476 -------------------------------------------------------------------------
454 477 -- ADDR DATA OUT
455 478 -------------------------------------------------------------------------
456 479 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
457 480 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
458 481 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
459 482 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
460 483
461 484 data_f0_data_out_valid => data_f0_data_out_valid,
462 485 data_f1_data_out_valid => data_f1_data_out_valid,
463 486 data_f2_data_out_valid => data_f2_data_out_valid,
464 487 data_f3_data_out_valid => data_f3_data_out_valid,
465 488
466 489 data_f0_addr_out => data_f0_addr_out,
467 490 data_f1_addr_out => data_f1_addr_out,
468 491 data_f2_addr_out => data_f2_addr_out,
469 492 data_f3_addr_out => data_f3_addr_out
470 493 );
471 494
472 495 END beh;
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@@ -1,394 +1,394
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter IS
31 31 GENERIC(
32 32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
33 nb_data_by_buffer_size : INTEGER := 11
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
37 37 rstn : IN STD_LOGIC;
38 38 ---------------------------------------------------------------------------
39 39 run : IN STD_LOGIC;
40 40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 41 ---------------------------------------------------------------------------
42 42 -- SNAPSHOT INTERFACE (INPUT)
43 43 ---------------------------------------------------------------------------
44 44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48 48
49 49 ---------------------------------------------------------------------------
50 50 -- FIFO INTERFACE (OUTPUT)
51 51 ---------------------------------------------------------------------------
52 52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 54 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
55 55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
56 56
57 57 );
58 58 END ENTITY;
59 59
60 60
61 61 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
62 62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
63 63 SIGNAL state : state_type_fifo_arbiter;
64 64
65 65 -----------------------------------------------------------------------------
66 66 -- DATA MUX
67 67 -----------------------------------------------------------------------------
68 68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
69 69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 72 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
74 74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
75 75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
76 76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
77 77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
78 78
79 79 -----------------------------------------------------------------------------
80 80 -- RR and SELECTION
81 81 -----------------------------------------------------------------------------
82 82 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 83 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 84 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 85 SIGNAL sel_reg : STD_LOGIC;
86 86 SIGNAL sel_ack : STD_LOGIC;
87 87 SIGNAL no_sel : STD_LOGIC;
88 88
89 89 -----------------------------------------------------------------------------
90 90 -- REG
91 91 -----------------------------------------------------------------------------
92 92 SIGNAL count_enable : STD_LOGIC;
93 93 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 94 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
95 95
96 96 --SIGNAL shift_data_enable : STD_LOGIC;
97 97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
99 99
100 100 --SIGNAL shift_time_enable : STD_LOGIC;
101 101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
103 103
104 104 BEGIN
105 105
106 106 -----------------------------------------------------------------------------
107 107 -- CONTROL
108 108 -----------------------------------------------------------------------------
109 109 PROCESS (clk, rstn)
110 110 BEGIN -- PROCESS
111 111 IF rstn = '0' THEN -- asynchronous reset (active low)
112 112 count_enable <= '0';
113 113 data_in_ack <= (OTHERS => '0');
114 114 data_out_wen <= (OTHERS => '1');
115 115 sel_ack <= '0';
116 116 state <= IDLE;
117 117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 118 count_enable <= '0';
119 119 data_in_ack <= (OTHERS => '0');
120 120 data_out_wen <= (OTHERS => '1');
121 121 sel_ack <= '0';
122 122 IF run = '0' THEN
123 123 state <= IDLE;
124 124 ELSE
125 125 CASE state IS
126 126 WHEN IDLE =>
127 127 IF no_sel = '0' THEN
128 128 state <= TIME1;
129 129 END IF;
130 130 WHEN TIME1 =>
131 131 count_enable <= '1';
132 132 IF UNSIGNED(count) = 0 THEN
133 133 state <= TIME2;
134 134 data_out_wen <= NOT sel;
135 135 data_out <= data_sel(0);
136 136 ELSE
137 137 state <= DATA1;
138 138 END IF;
139 139 WHEN TIME2 =>
140 140 data_out_wen <= NOT sel;
141 141 data_out <= data_sel(1) ;
142 142 state <= DATA1;
143 143 WHEN DATA1 =>
144 144 data_out_wen <= NOT sel;
145 145 data_out <= data_sel(2);
146 146 state <= DATA2;
147 147 WHEN DATA2 =>
148 148 data_out_wen <= NOT sel;
149 149 data_out <= data_sel(3);
150 150 state <= DATA3;
151 151 WHEN DATA3 =>
152 152 data_out_wen <= NOT sel;
153 153 data_out <= data_sel(4);
154 154 state <= LAST;
155 155 data_in_ack <= sel;
156 156 WHEN LAST =>
157 157 state <= IDLE;
158 158 sel_ack <= '1';
159 159
160 160 WHEN OTHERS => NULL;
161 161 END CASE;
162 162 END IF;
163 163 END IF;
164 164 END PROCESS;
165 165 -----------------------------------------------------------------------------
166 166
167 167
168 168 --PROCESS (clk, rstn)
169 169 --BEGIN -- PROCESS
170 170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
171 171 -- count_enable <= '0';
172 172 -- shift_time_enable <= '0';
173 173 -- shift_data_enable <= '0';
174 174 -- data_in_ack <= (OTHERS => '0');
175 175 -- data_out_wen <= (OTHERS => '1');
176 176 -- sel_ack <= '0';
177 177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
178 178 -- IF run = '0' OR no_sel = '1' THEN
179 179 -- count_enable <= '0';
180 180 -- shift_time_enable <= '0';
181 181 -- shift_data_enable <= '0';
182 182 -- data_in_ack <= (OTHERS => '0');
183 183 -- data_out_wen <= (OTHERS => '1');
184 184 -- sel_ack <= '0';
185 185 -- ELSE
186 186 -- --COUNT
187 187 -- IF shift_data_s = "10" THEN
188 188 -- count_enable <= '1';
189 189 -- ELSE
190 190 -- count_enable <= '0';
191 191 -- END IF;
192 192 -- --DATA
193 193 -- IF shift_time_s = "10" THEN
194 194 -- shift_data_enable <= '1';
195 195 -- ELSE
196 196 -- shift_data_enable <= '0';
197 197 -- END IF;
198 198
199 199 -- --TIME
200 200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
201 201 -- shift_time_s = "00" OR
202 202 -- shift_time_s = "01"
203 203 -- THEN
204 204 -- shift_time_enable <= '1';
205 205 -- ELSE
206 206 -- shift_time_enable <= '0';
207 207 -- END IF;
208 208
209 209 -- --ACK
210 210 -- IF shift_data_s = "10" THEN
211 211 -- data_in_ack <= sel;
212 212 -- sel_ack <= '1';
213 213 -- ELSE
214 214 -- data_in_ack <= (OTHERS => '0');
215 215 -- sel_ack <= '0';
216 216 -- END IF;
217 217
218 218 -- --VALID OUT
219 219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
220 220 -- IF sel(I) = '1' AND count_enable = '0' THEN
221 221 -- data_out_wen(I) <= '0';
222 222 -- ELSE
223 223 -- data_out_wen(I) <= '1';
224 224 -- END IF;
225 225 -- END LOOP all_wen;
226 226
227 227 -- END IF;
228 228 -- END IF;
229 229 --END PROCESS;
230 230
231 231 -----------------------------------------------------------------------------
232 232 -- DATA MUX
233 233 -----------------------------------------------------------------------------
234 234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
235 235 I_time_in: IF I < 48 GENERATE
236 236 data_0_v(I) <= time_in(0,I);
237 237 data_1_v(I) <= time_in(1,I);
238 238 data_2_v(I) <= time_in(2,I);
239 239 data_3_v(I) <= time_in(3,I);
240 240 END GENERATE I_time_in;
241 241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
242 242 data_0_v(I) <= '0';
243 243 data_1_v(I) <= '0';
244 244 data_2_v(I) <= '0';
245 245 data_3_v(I) <= '0';
246 246 END GENERATE I_null;
247 247 I_data_in: IF I > 32*2-1 GENERATE
248 248 data_0_v(I) <= data_in(0,I-32*2);
249 249 data_1_v(I) <= data_in(1,I-32*2);
250 250 data_2_v(I) <= data_in(2,I-32*2);
251 251 data_3_v(I) <= data_in(3,I-32*2);
252 252 END GENERATE I_data_in;
253 253 END GENERATE all_bit_data_in;
254 254
255 255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
256 256 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
257 257 data_0(J)(I) <= data_0_v(J*32+I);
258 258 data_1(J)(I) <= data_1_v(J*32+I);
259 259 data_2(J)(I) <= data_2_v(J*32+I);
260 260 data_3(J)(I) <= data_3_v(J*32+I);
261 261 END GENERATE all_data_bit;
262 262 END GENERATE all_word;
263 263
264 264 data_sel <= data_0 WHEN sel(0) = '1' ELSE
265 265 data_1 WHEN sel(1) = '1' ELSE
266 266 data_2 WHEN sel(2) = '1' ELSE
267 267 data_3;
268 268
269 269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
270 270 -- data_sel(1) WHEN shift_time = "01" ELSE
271 271 -- data_sel(2) WHEN shift_data = "00" ELSE
272 272 -- data_sel(3) WHEN shift_data = "01" ELSE
273 273 -- data_sel(4);
274 274
275 275
276 276 -----------------------------------------------------------------------------
277 277 -- RR and SELECTION
278 278 -----------------------------------------------------------------------------
279 279 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
280 280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
281 281 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
282 282 END GENERATE all_input_rr;
283 283
284 284 RR_Arbiter_4_1 : RR_Arbiter_4
285 285 PORT MAP (
286 286 clk => clk,
287 287 rstn => rstn,
288 288 in_valid => valid_in_rr,
289 289 out_grant => sel_s); --sel_s);
290 290
291 291 -- sel <= sel_s;
292 292
293 293 PROCESS (clk, rstn)
294 294 BEGIN -- PROCESS
295 295 IF rstn = '0' THEN -- asynchronous reset (active low)
296 296 sel <= "0000";
297 297 sel_reg <= '0';
298 298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 299 -- sel_reg
300 300 -- sel_ack
301 301 -- sel_s
302 302 -- sel = "0000 "
303 303 --sel <= sel_s;
304 304 IF sel_reg = '0' OR sel_ack = '1'
305 305 --OR shift_data_s = "10"
306 306 THEN
307 307 sel <= sel_s;
308 308 IF sel_s = "0000" THEN
309 309 sel_reg <= '0';
310 310 ELSE
311 311 sel_reg <= '1';
312 312 END IF;
313 313 END IF;
314 314 END IF;
315 315 END PROCESS;
316 316
317 317 no_sel <= '1' WHEN sel = "0000" ELSE '0';
318 318
319 319 -----------------------------------------------------------------------------
320 320 -- REG
321 321 -----------------------------------------------------------------------------
322 322 reg_count_i: lpp_waveform_fifo_arbiter_reg
323 323 GENERIC MAP (
324 324 data_size => nb_data_by_buffer_size,
325 325 data_nb => 4)
326 326 PORT MAP (
327 327 clk => clk,
328 328 rstn => rstn,
329 329 run => run,
330 330 max_count => nb_data_by_buffer,
331 331 enable => count_enable,
332 332 sel => sel,
333 333 data => count,
334 334 data_s => count_s);
335 335
336 336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
337 337 -- GENERIC MAP (
338 338 -- data_size => 2,
339 339 -- data_nb => 4)
340 340 -- PORT MAP (
341 341 -- clk => clk,
342 342 -- rstn => rstn,
343 343 -- run => run,
344 344 -- max_count => "10", -- 2
345 345 -- enable => shift_data_enable,
346 346 -- sel => sel,
347 347 -- data => shift_data,
348 348 -- data_s => shift_data_s);
349 349
350 350
351 351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
352 352 -- GENERIC MAP (
353 353 -- data_size => 2,
354 354 -- data_nb => 4)
355 355 -- PORT MAP (
356 356 -- clk => clk,
357 357 -- rstn => rstn,
358 358 -- run => run,
359 359 -- max_count => "10", -- 2
360 360 -- enable => shift_time_enable,
361 361 -- sel => sel,
362 362 -- data => shift_time,
363 363 -- data_s => shift_time_s);
364 364
365 365
366 366
367 367
368 368 END ARCHITECTURE;
369 369
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter_reg IS
31 31 GENERIC(
32 32 data_size : INTEGER;
33 33 data_nb : INTEGER
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
37 37 rstn : IN STD_LOGIC;
38 38 ---------------------------------------------------------------------------
39 39 run : IN STD_LOGIC;
40 40
41 41 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
42 42
43 43 enable : IN STD_LOGIC;
44 44 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
45 45
46 46 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
47 47 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
48 48 );
49 49 END ENTITY;
50 50
51 51
52 52 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
53 53
54 54 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
55 55 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
56 56
57 SIGNAL reg_sel : INTEGER;
58 SIGNAL reg_sel_s : INTEGER;
57 SIGNAL reg_sel : INTEGER := 0;
58 SIGNAL reg_sel_s : INTEGER := 0;
59 59
60 60 BEGIN
61 61
62 62 all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE
63 63 PROCESS (clk, rstn)
64 64 BEGIN -- PROCESS
65 65 IF rstn = '0' THEN -- asynchronous reset (active low)
66 66 reg(I) <= 0;
67 67 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
68 68 IF run = '0' THEN
69 69 reg(I) <= 0;
70 70 ELSE
71 71 IF sel(I) = '1' THEN
72 72 reg(I) <= reg_sel_s;
73 73 END IF;
74 74 END IF;
75 75 END IF;
76 76 END PROCESS;
77 77 END GENERATE all_reg;
78 78
79 79 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
80 80 reg(1) WHEN sel(1) = '1' ELSE
81 81 reg(2) WHEN sel(2) = '1' ELSE
82 82 reg(3);
83 83
84 84 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
85 85 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
86 86 0;
87 87
88 88 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size));
89 89 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size));
90 90
91 91 END ARCHITECTURE;
92 92
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@@ -1,364 +1,375
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 USE GRLIB.DMA2AHB_Package.ALL;
31 31
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34
35 35 PACKAGE lpp_waveform_pkg IS
36 36
37 37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38 38
39 39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40 40
41 41 -----------------------------------------------------------------------------
42 42 -- SNAPSHOT
43 43 -----------------------------------------------------------------------------
44 44
45 45 COMPONENT lpp_waveform_snapshot
46 46 GENERIC (
47 47 data_size : INTEGER;
48 48 nb_snapshot_param_size : INTEGER);
49 49 PORT (
50 50 clk : IN STD_LOGIC;
51 51 rstn : IN STD_LOGIC;
52 52 run : IN STD_LOGIC;
53 53 enable : IN STD_LOGIC;
54 54 burst_enable : IN STD_LOGIC;
55 55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 56 start_snapshot : IN STD_LOGIC;
57 57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 58 data_in_valid : IN STD_LOGIC;
59 59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 60 data_out_valid : OUT STD_LOGIC);
61 61 END COMPONENT;
62 62
63 63 COMPONENT lpp_waveform_burst
64 64 GENERIC (
65 65 data_size : INTEGER);
66 66 PORT (
67 67 clk : IN STD_LOGIC;
68 68 rstn : IN STD_LOGIC;
69 69 run : IN STD_LOGIC;
70 70 enable : IN STD_LOGIC;
71 71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 72 data_in_valid : IN STD_LOGIC;
73 73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 74 data_out_valid : OUT STD_LOGIC);
75 75 END COMPONENT;
76 76
77 77 COMPONENT lpp_waveform_snapshot_controler
78 78 GENERIC (
79 79 delta_vector_size : INTEGER;
80 80 delta_vector_size_f0_2 : INTEGER);
81 81 PORT (
82 82 clk : IN STD_LOGIC;
83 83 rstn : IN STD_LOGIC;
84 84 reg_run : IN STD_LOGIC;
85 85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 92 data_f0_valid : IN STD_LOGIC;
93 93 data_f2_valid : IN STD_LOGIC;
94 94 start_snapshot_f0 : OUT STD_LOGIC;
95 95 start_snapshot_f1 : OUT STD_LOGIC;
96 96 start_snapshot_f2 : OUT STD_LOGIC;
97 97 wfp_on : OUT STD_LOGIC);
98 98 END COMPONENT;
99 99
100 100 -----------------------------------------------------------------------------
101 101 --
102 102 -----------------------------------------------------------------------------
103 103 COMPONENT lpp_waveform
104 104 GENERIC (
105 105 tech : INTEGER;
106 106 data_size : INTEGER;
107 107 nb_data_by_buffer_size : INTEGER;
108 108 nb_word_by_buffer_size : INTEGER;
109 109 nb_snapshot_param_size : INTEGER;
110 110 delta_vector_size : INTEGER;
111 111 delta_vector_size_f0_2 : INTEGER);
112 112 PORT (
113 113 clk : IN STD_LOGIC;
114 114 rstn : IN STD_LOGIC;
115 115 reg_run : IN STD_LOGIC;
116 116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
117 117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
120 120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 122 enable_f0 : IN STD_LOGIC;
123 123 enable_f1 : IN STD_LOGIC;
124 124 enable_f2 : IN STD_LOGIC;
125 125 enable_f3 : IN STD_LOGIC;
126 126 burst_f0 : IN STD_LOGIC;
127 127 burst_f1 : IN STD_LOGIC;
128 128 burst_f2 : IN STD_LOGIC;
129 129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 139 data_f0_in_valid : IN STD_LOGIC;
140 140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 142 data_f1_in_valid : IN STD_LOGIC;
143 143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 145 data_f2_in_valid : IN STD_LOGIC;
146 146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 data_f3_in_valid : IN STD_LOGIC;
149 149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 data_f0_data_out_valid : OUT STD_LOGIC;
153 153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
154 154 data_f0_data_out_ren : IN STD_LOGIC;
155 155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 157 data_f1_data_out_valid : OUT STD_LOGIC;
158 158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
159 159 data_f1_data_out_ren : IN STD_LOGIC;
160 160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 162 data_f2_data_out_valid : OUT STD_LOGIC;
163 163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 164 data_f2_data_out_ren : IN STD_LOGIC;
165 165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 167 data_f3_data_out_valid : OUT STD_LOGIC;
168 168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 169 data_f3_data_out_ren : IN STD_LOGIC;
170 170
171 171 --debug
172 172 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 173 debug_f0_data_valid : OUT STD_LOGIC;
174 174 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 175 debug_f1_data_valid : OUT STD_LOGIC;
176 176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177 177 debug_f2_data_valid : OUT STD_LOGIC;
178 178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 debug_f3_data_valid : OUT STD_LOGIC);
179 debug_f3_data_valid : OUT STD_LOGIC;
180
181 --debug FIFO IN
182 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
184 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
186 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
188 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
190 );
180 191 END COMPONENT;
181 192
182 193 COMPONENT lpp_waveform_dma_genvalid
183 194 PORT (
184 195 HCLK : IN STD_LOGIC;
185 196 HRESETn : IN STD_LOGIC;
186 197 run : IN STD_LOGIC;
187 198 valid_in : IN STD_LOGIC;
188 199 ack_in : IN STD_LOGIC;
189 200 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
190 201 valid_out : OUT STD_LOGIC;
191 202 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
192 203 error : OUT STD_LOGIC);
193 204 END COMPONENT;
194 205
195 206 -----------------------------------------------------------------------------
196 207 -- FIFO
197 208 -----------------------------------------------------------------------------
198 209 COMPONENT lpp_waveform_fifo_ctrl
199 210 GENERIC (
200 211 offset : INTEGER;
201 212 length : INTEGER);
202 213 PORT (
203 214 clk : IN STD_LOGIC;
204 215 rstn : IN STD_LOGIC;
205 216 run : IN STD_LOGIC;
206 217 ren : IN STD_LOGIC;
207 218 wen : IN STD_LOGIC;
208 219 mem_re : OUT STD_LOGIC;
209 220 mem_we : OUT STD_LOGIC;
210 221 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
211 222 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
212 223 empty_almost : OUT STD_LOGIC;
213 224 empty : OUT STD_LOGIC;
214 225 full_almost : OUT STD_LOGIC;
215 226 full : OUT STD_LOGIC);
216 227 END COMPONENT;
217 228
218 229 COMPONENT lpp_waveform_fifo_arbiter
219 230 GENERIC (
220 231 tech : INTEGER;
221 232 nb_data_by_buffer_size : INTEGER);
222 233 PORT (
223 234 clk : IN STD_LOGIC;
224 235 rstn : IN STD_LOGIC;
225 236 run : IN STD_LOGIC;
226 237 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
227 238 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
228 239 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
229 240 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
230 241 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
231 242 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
232 243 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 244 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 245 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
235 246 END COMPONENT;
236 247
237 248 COMPONENT lpp_waveform_fifo
238 249 GENERIC (
239 250 tech : INTEGER);
240 251 PORT (
241 252 clk : IN STD_LOGIC;
242 253 rstn : IN STD_LOGIC;
243 254 run : IN STD_LOGIC;
244 255 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 256 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
246 257 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
247 258 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
248 259 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249 260 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 261 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 262 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
252 263 END COMPONENT;
253 264
254 265 COMPONENT lpp_waveform_fifo_headreg
255 266 GENERIC (
256 267 tech : INTEGER);
257 268 PORT (
258 269 clk : IN STD_LOGIC;
259 270 rstn : IN STD_LOGIC;
260 271 run : IN STD_LOGIC;
261 272 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 273 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
263 274 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
264 275 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
265 276 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
266 277 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
267 278 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
268 279 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
269 280 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
270 281 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
271 282 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
272 283 END COMPONENT;
273 284
274 285 COMPONENT lpp_waveform_fifo_latencyCorrection
275 286 GENERIC (
276 287 tech : INTEGER);
277 288 PORT (
278 289 clk : IN STD_LOGIC;
279 290 rstn : IN STD_LOGIC;
280 291 run : IN STD_LOGIC;
281 292 empty_almost : OUT STD_LOGIC;
282 293 empty : OUT STD_LOGIC;
283 294 data_ren : IN STD_LOGIC;
284 295 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 296 empty_almost_fifo : IN STD_LOGIC;
286 297 empty_fifo : IN STD_LOGIC;
287 298 data_ren_fifo : OUT STD_LOGIC;
288 299 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
289 300 END COMPONENT;
290 301
291 302 COMPONENT lpp_waveform_fifo_withoutLatency
292 303 GENERIC (
293 304 tech : INTEGER);
294 305 PORT (
295 306 clk : IN STD_LOGIC;
296 307 rstn : IN STD_LOGIC;
297 308 run : IN STD_LOGIC;
298 309 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
299 310 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
300 311 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
301 312 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
302 313 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
303 314 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
304 315 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
305 316 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
306 317 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
307 318 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
308 319 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
309 320 END COMPONENT;
310 321
311 322 -----------------------------------------------------------------------------
312 323 -- GEN ADDRESS
313 324 -----------------------------------------------------------------------------
314 325 COMPONENT lpp_waveform_genaddress
315 326 GENERIC (
316 327 nb_data_by_buffer_size : INTEGER);
317 328 PORT (
318 329 clk : IN STD_LOGIC;
319 330 rstn : IN STD_LOGIC;
320 331 run : IN STD_LOGIC;
321 332 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
322 333 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
323 334 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
324 335 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
325 336 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
326 337 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 338 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 339 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 340 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
330 341 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
331 342 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
332 343 data_f0_data_out_valid_burst : OUT STD_LOGIC;
333 344 data_f1_data_out_valid_burst : OUT STD_LOGIC;
334 345 data_f2_data_out_valid_burst : OUT STD_LOGIC;
335 346 data_f3_data_out_valid_burst : OUT STD_LOGIC;
336 347 data_f0_data_out_valid : OUT STD_LOGIC;
337 348 data_f1_data_out_valid : OUT STD_LOGIC;
338 349 data_f2_data_out_valid : OUT STD_LOGIC;
339 350 data_f3_data_out_valid : OUT STD_LOGIC;
340 351 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
341 352 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
342 353 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
343 354 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
344 355 END COMPONENT;
345 356
346 357 -----------------------------------------------------------------------------
347 358 -- lpp_waveform_fifo_arbiter_reg
348 359 -----------------------------------------------------------------------------
349 360 COMPONENT lpp_waveform_fifo_arbiter_reg
350 361 GENERIC (
351 362 data_size : INTEGER;
352 363 data_nb : INTEGER);
353 364 PORT (
354 365 clk : IN STD_LOGIC;
355 366 rstn : IN STD_LOGIC;
356 367 run : IN STD_LOGIC;
357 368 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
358 369 enable : IN STD_LOGIC;
359 370 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
360 371 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
361 372 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
362 373 END COMPONENT;
363 374
364 375 END lpp_waveform_pkg;
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