@@ -0,0 +1,63 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------ | |
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19 | -- Author : Jean-christophe Pellion | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------ | |
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22 | library IEEE; | |
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23 | use IEEE.std_logic_1164.all; | |
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24 | use IEEE.numeric_std.all; | |
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25 | ||
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26 | ENTITY ramp_generator IS | |
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27 | ||
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28 | GENERIC ( | |
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29 | DATA_SIZE : INTEGER := 16; | |
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30 | VALUE_UNSIGNED_INIT : INTEGER := 0; | |
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31 | VALUE_UNSIGNED_INCR : INTEGER := 1; | |
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32 | VALUE_UNSIGNED_MASK : INTEGER := 16#FFFF#); | |
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33 | ||
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34 | PORT ( | |
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35 | clk : IN STD_LOGIC; | |
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36 | rstn : IN STD_LOGIC; | |
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37 | new_data : IN STD_LOGIC; | |
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38 | output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); | |
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39 | ||
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40 | END ramp_generator; | |
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41 | ||
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42 | ARCHITECTURE beh OF ramp_generator IS | |
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43 | ||
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44 | SIGNAL data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
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45 | ||
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46 | BEGIN -- beh | |
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47 | ||
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48 | PROCESS (clk, rstn) | |
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49 | BEGIN -- PROCESS | |
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50 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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51 | data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INIT,DATA_SIZE)) | |
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52 | AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK,DATA_SIZE)); | |
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53 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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54 | IF new_data = '1' THEN | |
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55 | data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INCR + to_integer(UNSIGNED(data)),DATA_SIZE)) | |
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56 | AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK ,DATA_SIZE)); | |
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57 | END IF; | |
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58 | END IF; | |
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59 | END PROCESS; | |
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60 | ||
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61 | output_data <= data; | |
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62 | ||
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63 | END beh; |
@@ -53,7 +53,10 USE lpp.lpp_bootloader_pkg.ALL; | |||
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53 | 53 | ENTITY LFR_EQM IS |
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54 | 54 | GENERIC ( |
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55 | 55 | Mem_use : INTEGER := use_RAM; |
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56 | USE_BOOTLOADER : INTEGER := 0 | |
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56 | USE_BOOTLOADER : INTEGER := 0; | |
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57 | USE_ADCDRIVER : INTEGER := 0; | |
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58 | tech : INTEGER := apa3e; | |
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59 | tech_leon : INTEGER := apa3e | |
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57 | 60 | ); |
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58 | 61 | |
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59 | 62 | PORT ( |
@@ -179,7 +182,7 BEGIN -- beh | |||
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179 | 182 | ----------------------------------------------------------------------------- |
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180 | 183 | -- CLK_LOCK |
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181 | 184 | ----------------------------------------------------------------------------- |
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182 |
rst_gen_global : rstgen PORT MAP (reset, clk |
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185 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); | |
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183 | 186 | |
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184 | 187 | PROCESS (clk50MHz_int, rstn_50) |
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185 | 188 | BEGIN -- PROCESS |
@@ -191,7 +194,7 BEGIN -- beh | |||
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191 | 194 | nSRAM_BUSY_reg <= nSRAM_BUSY; |
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192 | 195 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN |
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193 | 196 | IF clk_busy_counter = "1111" THEN |
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194 | clk_lock = '1'; | |
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197 | clk_lock <= '1'; | |
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195 | 198 | ELSE |
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196 | 199 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); |
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197 | 200 | END IF; |
@@ -228,8 +231,8 BEGIN -- beh | |||
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228 | 231 | -- |
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229 | 232 | leon3_soc_1 : leon3_soc |
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230 | 233 | GENERIC MAP ( |
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231 |
fabtech => |
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232 |
memtech => |
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234 | fabtech => tech_leon, | |
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235 | memtech => tech_leon, | |
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233 | 236 | padtech => inferred, |
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234 | 237 | clktech => inferred, |
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235 | 238 | disas => 0, |
@@ -290,7 +293,7 BEGIN -- beh | |||
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290 | 293 | ------------------------------------------------------------------------------- |
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291 | 294 | apb_lfr_management_1 : apb_lfr_management |
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292 | 295 | GENERIC MAP ( |
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293 |
tech => |
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296 | tech => tech, | |
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294 | 297 | pindex => 6, |
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295 | 298 | paddr => 6, |
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296 | 299 | pmask => 16#fff#, |
@@ -361,7 +364,7 BEGIN -- beh | |||
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361 | 364 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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362 | 365 | spw_phy0 : grspw_phy |
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363 | 366 | GENERIC MAP( |
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364 |
tech => |
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367 | tech => tech_leon, | |
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365 | 368 | rxclkbuftype => 1, |
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366 | 369 | scantest => 0) |
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367 | 370 | PORT MAP( |
@@ -376,7 +379,7 BEGIN -- beh | |||
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376 | 379 | |
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377 | 380 | -- SPW core |
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378 | 381 | sw0 : grspwm GENERIC MAP( |
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379 |
tech => |
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382 | tech => tech_leon, | |
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380 | 383 | hindex => 1, |
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381 | 384 | pindex => 5, |
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382 | 385 | paddr => 5, |
@@ -393,7 +396,7 BEGIN -- beh | |||
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393 | 396 | netlist => 0, |
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394 | 397 | ports => 2, |
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395 | 398 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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396 |
memtech => |
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399 | memtech => tech_leon, | |
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397 | 400 | destkey => 2, |
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398 | 401 | spwcore => 1 |
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399 | 402 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
@@ -468,23 +471,66 BEGIN -- beh | |||
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468 | 471 | ----------------------------------------------------------------------------- |
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469 | 472 | -- |
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470 | 473 | ----------------------------------------------------------------------------- |
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471 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
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472 | GENERIC MAP ( | |
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473 | ChanelCount => 9, | |
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474 | ncycle_cnv_high => 13, | |
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475 |
ncycle_cnv |
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476 | FILTER_ENABLED => 16#FF#) | |
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477 | PORT MAP ( | |
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478 | cnv_clk => clk_24, | |
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479 |
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480 | cnv => ADC_smpclk_s, | |
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481 |
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482 |
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483 | ADC_data => ADC_data, | |
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484 |
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485 | sample => sample, | |
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486 |
sample |
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474 | USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE | |
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475 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
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476 | GENERIC MAP ( | |
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477 | ChanelCount => 9, | |
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478 | ncycle_cnv_high => 13, | |
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479 | ncycle_cnv => 25, | |
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480 | FILTER_ENABLED => 16#FF#) | |
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481 | PORT MAP ( | |
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482 | cnv_clk => clk_24, | |
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483 | cnv_rstn => rstn_24, | |
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484 | cnv => ADC_smpclk_s, | |
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485 | clk => clk_25, | |
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486 | rstn => rstn_25, | |
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487 | ADC_data => ADC_data, | |
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488 | ADC_nOE => ADC_OEB_bar_CH_s, | |
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489 | sample => sample, | |
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490 | sample_val => sample_val); | |
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491 | ||
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492 | END GENERATE USE_ADCDRIVER_true; | |
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493 | ||
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494 | USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE | |
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495 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
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496 | GENERIC MAP ( | |
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497 | ChanelCount => 9, | |
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498 | ncycle_cnv_high => 13, | |
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499 | ncycle_cnv => 25, | |
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500 | FILTER_ENABLED => 16#FF#) | |
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501 | PORT MAP ( | |
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502 | cnv_clk => clk_24, | |
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503 | cnv_rstn => rstn_24, | |
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504 | cnv => ADC_smpclk_s, | |
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505 | clk => clk_25, | |
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506 | rstn => rstn_25, | |
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507 | ADC_data => ADC_data, | |
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508 | ADC_nOE => OPEN, | |
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509 | sample => OPEN, | |
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510 | sample_val => sample_val); | |
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511 | ||
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512 | ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); | |
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487 | 513 | |
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514 | all_sample: FOR I IN 8 DOWNTO 0 GENERATE | |
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515 | ramp_generator_1: ramp_generator | |
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516 | GENERIC MAP ( | |
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517 | DATA_SIZE => 14, | |
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518 | VALUE_UNSIGNED_INIT => 2**I, | |
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519 | VALUE_UNSIGNED_INCR => 0, | |
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520 | VALUE_UNSIGNED_MASK => 16#3FFF#) | |
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521 | PORT MAP ( | |
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522 | clk => clk_25, | |
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523 | rstn => rstn_25, | |
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524 | new_data => sample_val, | |
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525 | output_data => sample(I) ); | |
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526 | END GENERATE all_sample; | |
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527 | ||
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528 | ||
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529 | END GENERATE USE_ADCDRIVER_false; | |
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530 | ||
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531 | ||
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532 | ||
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533 | ||
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488 | 534 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
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489 | 535 | |
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490 | 536 | ADC_smpclk <= ADC_smpclk_s; |
@@ -16,7 +16,7 SYNPOPT="set_option -pipe 0; set_option | |||
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16 | 16 | VHDLSYNFILES=LFR-EQM.vhd |
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17 | 17 | VHDLSIMFILES=testbench.vhd |
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18 | 18 | #SIMTOP=testbench |
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19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc | |
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19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000_NoADC.pdc | |
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20 | 20 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc |
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21 | 21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc |
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22 | 22 |
@@ -24,6 +24,8 LIBRARY IEEE; | |||
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24 | 24 | USE IEEE.STD_LOGIC_1164.ALL; |
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25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
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26 | 26 | |
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27 | LIBRARY techmap; | |
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28 | USE techmap.gencomp.ALL; | |
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27 | 29 | |
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28 | 30 | LIBRARY lpp; |
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29 | 31 | USE lpp.lpp_sim_pkg.ALL; |
@@ -65,7 +67,10 ARCHITECTURE beh OF TB IS | |||
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65 | 67 | COMPONENT LFR_EQM |
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66 | 68 | GENERIC ( |
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67 | 69 | Mem_use : INTEGER; |
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68 |
USE_BOOTLOADER : INTEGER |
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70 | USE_BOOTLOADER : INTEGER; | |
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71 | USE_ADCDRIVER : INTEGER; | |
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72 | tech : INTEGER; | |
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73 | tech_leon : INTEGER); | |
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69 | 74 | PORT ( |
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70 | 75 | clk50MHz : IN STD_ULOGIC; |
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71 | 76 | clk49_152MHz : IN STD_ULOGIC; |
@@ -215,7 +220,10 BEGIN -- beh | |||
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215 | 220 | LFR_EQM_1 : LFR_EQM |
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216 | 221 | GENERIC MAP ( |
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217 | 222 | Mem_use => use_RAM, |
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218 |
USE_BOOTLOADER => 0 |
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223 | USE_BOOTLOADER => 0, | |
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224 | USE_ADCDRIVER => 0, | |
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225 | tech => apa3e, | |
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226 | tech_leon => inferred) | |
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219 | 227 | PORT MAP ( |
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220 | 228 | clk50MHz => clk50MHz, --IN --ok |
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221 | 229 | clk49_152MHz => clk49_152MHz, --in --ok |
@@ -316,7 +324,7 BEGIN -- beh | |||
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316 | 324 | reset <= '0'; |
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317 | 325 | WAIT FOR 500 ns; |
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318 | 326 | reset <= '1'; |
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319 |
WAIT FOR 100 |
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327 | WAIT FOR 100 us; | |
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320 | 328 | message_simu <= "0 - UART init "; |
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321 | 329 | UART_INIT(TXD1, txp); |
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322 | 330 | |
@@ -324,7 +332,7 BEGIN -- beh | |||
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324 | 332 | -- LAUNCH leon 3 software |
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325 | 333 | --------------------------------------------------------------------------- |
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326 | 334 | message_simu <= "2- GO Leon3...."; |
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327 | ||
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335 | ||
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328 | 336 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- |
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329 | 337 | --Force a debug break |
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330 | 338 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); |
@@ -523,18 +531,25 BEGIN -- beh | |||
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523 | 531 | |
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524 | 532 | |
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525 | 533 | message_simu <= "4 - GO GO GO !!"; |
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534 | data_message <= "---------------"; | |
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526 | 535 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); |
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527 |
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536 | -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); | |
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528 | 537 | |
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538 | ||
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539 | data_read_v := (OTHERS => '1'); | |
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529 | 540 | READ_STATUS : LOOP |
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541 | data_message <= "---------------"; | |
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530 | 542 | WAIT FOR 2 ms; |
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531 |
data_message <= "READ_ |
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532 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |
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533 | data_read <= data_read_v; | |
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543 | data_message <= "READ_STATUS_SM_"; | |
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544 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |
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545 | --data_message <= "--------------r"; | |
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546 | --data_read <= data_read_v; | |
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534 | 547 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
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535 | 548 | |
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536 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |
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537 | data_read <= data_read_v; | |
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549 | data_message <= "READ_STATUS_WF_"; | |
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550 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |
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551 | --data_message <= "--------------r"; | |
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552 | --data_read <= data_read_v; | |
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538 | 553 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
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539 | 554 | END LOOP READ_STATUS; |
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540 | 555 |
@@ -41,6 +41,7 vcom -quiet -93 -work lpp ../../../grl | |||
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41 | 41 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd |
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42 | 42 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd |
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43 | 43 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd |
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44 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd | |
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44 | 45 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd |
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45 | 46 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd |
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46 | 47 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd |
@@ -187,10 +188,36 vsim work.tb | |||
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187 | 188 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 |
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188 | 189 | #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 |
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189 | 190 | |
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190 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000 |
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191 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 00 |
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192 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 0 |
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193 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data |
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191 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
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192 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
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193 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
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194 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
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195 | ||
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196 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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197 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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198 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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199 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
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200 | ||
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201 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |
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202 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |
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203 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |
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204 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd | |
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205 | ||
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206 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd | |
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207 | ||
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208 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
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209 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
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210 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
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211 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
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212 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
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213 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
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214 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
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215 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
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216 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9 | |
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217 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9 | |
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218 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9 | |
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219 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9 | |
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220 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9 | |
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194 | 221 | |
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195 | 222 | log -r *; |
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196 | 223 | do wave.do ; |
@@ -15,16 +15,16 add wave -noupdate -expand -group RAM -r | |||
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15 | 15 | add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data |
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16 | 16 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk |
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17 | 17 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH |
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18 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
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19 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
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20 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
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21 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
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22 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
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23 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
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24 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
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25 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
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26 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
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27 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
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18 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
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19 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
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20 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
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21 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
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22 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
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23 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
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24 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
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25 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
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26 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
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27 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
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28 | 28 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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29 | 29 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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30 | 30 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
@@ -59,12 +59,12 add wave -noupdate -group LFR1_s -radix | |||
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59 | 59 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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60 | 60 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp |
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61 | 61 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp |
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62 | add wave -noupdate -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
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63 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f1 | |
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64 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f2 | |
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65 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
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66 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
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67 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
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62 | add wave -noupdate -expand -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
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63 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f1 | |
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64 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f2 | |
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65 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
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66 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
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67 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
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68 | 68 | add wave -noupdate /tb/error_wfp |
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69 | 69 | add wave -noupdate /tb/error_wfp_addr |
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70 | 70 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a |
@@ -94,11 +94,11 add wave -noupdate -group LPP_DMA_FSM -r | |||
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94 | 94 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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95 | 95 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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96 | 96 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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97 |
add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}} |
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98 |
add wave -noupdate |
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97 | add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-height 15 -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} /tb/sample(2)(5) {-height 15 -radix decimal} /tb/sample(2)(4) {-height 15 -radix decimal} /tb/sample(2)(3) {-height 15 -radix decimal} /tb/sample(2)(2) {-height 15 -radix decimal} /tb/sample(2)(1) {-height 15 -radix decimal} /tb/sample(2)(0) {-height 15 -radix decimal} /tb/sample(1) {-height 15 -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -expand} /tb/sample(1)(5) {-format Analog-Step -height 74 -min -4.0 -radix decimal} /tb/sample(1)(4) {-format Analog-Step -height 74 -min -8.0 -radix decimal} /tb/sample(1)(3) {-format Analog-Step -height 74 -max 70.0 -radix decimal} /tb/sample(1)(2) {-format Analog-Step -height 74 -max 512.0 -radix decimal} /tb/sample(1)(1) {-format Analog-Step -height 74 -max 256.0 -radix decimal} /tb/sample(1)(0) {-format Analog-Step -height 74 -max 16.0 -radix decimal} /tb/sample(0) {-height 15 -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-height 15 -radix decimal} /tb/sample(0)(4) {-height 15 -radix decimal} /tb/sample(0)(3) {-height 15 -radix decimal} /tb/sample(0)(2) {-height 15 -radix decimal} /tb/sample(0)(1) {-height 15 -radix decimal} /tb/sample(0)(0) {-height 15 -radix decimal}} /tb/sample | |
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98 | add wave -noupdate /tb/sample_counter | |
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99 | 99 | TreeUpdate [SetDefaultTree] |
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100 |
WaveRestoreCursors {{Cursor 1} { |
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101 |
quietly wave cursor active |
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100 | WaveRestoreCursors {{Cursor 1} {14590425667 ps} 0} {{Cursor 2} {5525050896 ps} 0} {{Cursor 3} {24728625854 ps} 0} | |
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101 | quietly wave cursor active 1 | |
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102 | 102 | configure wave -namecolwidth 517 |
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103 | 103 | configure wave -valuecolwidth 347 |
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104 | 104 | configure wave -justifyvalue left |
@@ -113,4 +113,4 configure wave -griddelta 40 | |||
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113 | 113 | configure wave -timeline 0 |
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114 | 114 | configure wave -timelineunits ns |
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115 | 115 | update |
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116 |
WaveRestoreZoom {0 ps} { |
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116 | WaveRestoreZoom {0 ps} {40323664500 ps} |
@@ -51,17 +51,17 PACKAGE general_purpose IS | |||
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51 | 51 | COMPONENT Clk_divider IS |
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52 | 52 | GENERIC(OSC_freqHz : INTEGER := 50000000; |
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53 | 53 | TargetFreq_Hz : INTEGER := 50000); |
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54 |
PORT (clk |
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55 |
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56 |
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54 | PORT (clk : IN STD_LOGIC; | |
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55 | reset : IN STD_LOGIC; | |
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56 | clk_divided : OUT STD_LOGIC); | |
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57 | 57 | END COMPONENT; |
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58 | 58 | |
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59 | 59 | |
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60 | 60 | COMPONENT Clk_divider2 IS |
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61 | generic(N : integer := 16); | |
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62 | port( | |
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63 |
clk_in : |
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64 | clk_out : out std_logic); | |
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61 | GENERIC(N : INTEGER := 16); | |
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62 | PORT( | |
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63 | clk_in : IN STD_LOGIC; | |
|
64 | clk_out : OUT STD_LOGIC); | |
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65 | 65 | END COMPONENT; |
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66 | 66 | |
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67 | 67 | COMPONENT Adder IS |
@@ -74,7 +74,7 PACKAGE general_purpose IS | |||
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74 | 74 | clk : IN STD_LOGIC; |
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75 | 75 | reset : IN STD_LOGIC; |
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76 | 76 | clr : IN STD_LOGIC; |
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77 | load : IN STD_LOGIC; | |
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77 | load : IN STD_LOGIC; | |
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78 | 78 | add : IN STD_LOGIC; |
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79 | 79 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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80 | 80 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
@@ -82,22 +82,22 PACKAGE general_purpose IS | |||
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82 | 82 | ); |
|
83 | 83 | END COMPONENT; |
|
84 | 84 | |
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85 |
COMPONENT Adder_V0 |
|
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86 | generic( | |
|
87 |
Input_SZ_A |
|
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88 |
Input_SZ_B |
|
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85 | COMPONENT Adder_V0 IS | |
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86 | GENERIC( | |
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87 | Input_SZ_A : INTEGER := 16; | |
|
88 | Input_SZ_B : INTEGER := 16 | |
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89 | 89 | |
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90 | ); | |
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91 | port( | |
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92 | clk : in std_logic; | |
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93 | reset : in std_logic; | |
|
94 | clr : in std_logic; | |
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95 | add : in std_logic; | |
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96 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
|
97 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
|
98 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) | |
|
99 | ); | |
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100 |
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|
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90 | ); | |
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91 | PORT( | |
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92 | clk : IN STD_LOGIC; | |
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93 | reset : IN STD_LOGIC; | |
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94 | clr : IN STD_LOGIC; | |
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95 | add : IN STD_LOGIC; | |
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96 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
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97 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
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98 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |
|
99 | ); | |
|
100 | END COMPONENT; | |
|
101 | 101 | |
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102 | 102 | COMPONENT ADDRcntr IS |
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103 | 103 | PORT( |
@@ -115,77 +115,77 end COMPONENT; | |||
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115 | 115 | Logic_en : INTEGER := 1; |
|
116 | 116 | Input_SZ_1 : INTEGER := 16; |
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117 | 117 | Input_SZ_2 : INTEGER := 9; |
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118 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
118 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
119 | 119 | |
|
120 | 120 | ); |
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121 | 121 | PORT( |
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122 | 122 | clk : IN STD_LOGIC; |
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123 | 123 | reset : IN STD_LOGIC; |
|
124 |
ctrl : IN STD_LOGIC_VECTOR(2 |
|
|
125 |
comp : IN STD_LOGIC_VECTOR(1 |
|
|
124 | ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
125 | comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
126 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
127 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |
|
128 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |
|
129 | ); | |
|
130 | END COMPONENT; | |
|
131 | ||
|
132 | COMPONENT ALU_V0 IS | |
|
133 | GENERIC( | |
|
134 | Arith_en : INTEGER := 1; | |
|
135 | Logic_en : INTEGER := 1; | |
|
136 | Input_SZ_1 : INTEGER := 16; | |
|
137 | Input_SZ_2 : INTEGER := 9 | |
|
138 | ||
|
139 | ); | |
|
140 | PORT( | |
|
141 | clk : IN STD_LOGIC; | |
|
142 | reset : IN STD_LOGIC; | |
|
143 | ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
126 | 144 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
127 | 145 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); |
|
128 | 146 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) |
|
129 | 147 | ); |
|
130 | 148 | END COMPONENT; |
|
131 | 149 | |
|
132 |
COMPONENT |
|
|
133 | GENERIC( | |
|
134 |
|
|
|
135 |
|
|
|
136 | Input_SZ_1 : INTEGER := 16; | |
|
137 | Input_SZ_2 : INTEGER := 9 | |
|
150 | COMPONENT MAC_V0 IS | |
|
151 | GENERIC( | |
|
152 | Input_SZ_A : INTEGER := 8; | |
|
153 | Input_SZ_B : INTEGER := 8 | |
|
138 | 154 | |
|
139 | ); | |
|
140 | PORT( | |
|
141 | clk : IN STD_LOGIC; | |
|
142 | reset : IN STD_LOGIC; | |
|
143 |
|
|
|
144 |
|
|
|
145 |
|
|
|
146 |
|
|
|
147 | ); | |
|
148 | END COMPONENT; | |
|
149 | ||
|
150 | COMPONENT MAC_V0 is | |
|
151 | generic( | |
|
152 | Input_SZ_A : integer := 8; | |
|
153 | Input_SZ_B : integer := 8 | |
|
154 | ||
|
155 | ); | |
|
156 | port( | |
|
157 | clk : in std_logic; | |
|
158 | reset : in std_logic; | |
|
159 | clr_MAC : in std_logic; | |
|
160 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); | |
|
161 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
|
162 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
|
163 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
|
164 | ); | |
|
165 | end COMPONENT; | |
|
155 | ); | |
|
156 | PORT( | |
|
157 | clk : IN STD_LOGIC; | |
|
158 | reset : IN STD_LOGIC; | |
|
159 | clr_MAC : IN STD_LOGIC; | |
|
160 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
161 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
162 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
163 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
|
164 | ); | |
|
165 | END COMPONENT; | |
|
166 | 166 | |
|
167 | 167 | --------------------------------------------------------- |
|
168 | 168 | -------- // Sélection grace a l'entrée "ctrl" \\ -------- |
|
169 | 169 | --------------------------------------------------------- |
|
170 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; | |
|
171 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; | |
|
172 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; | |
|
173 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; | |
|
174 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; | |
|
170 | CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; | |
|
171 | CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001"; | |
|
172 | CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010"; | |
|
173 | CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011"; | |
|
174 | CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100"; | |
|
175 | 175 | |
|
176 | 176 | |
|
177 | Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; | |
|
178 | Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; | |
|
179 | Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; | |
|
180 | Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; | |
|
181 | Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; | |
|
177 | CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; | |
|
178 | CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; | |
|
179 | CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; | |
|
180 | CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; | |
|
181 | CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; | |
|
182 | 182 | --------------------------------------------------------- |
|
183 | 183 | |
|
184 | 184 | COMPONENT MAC IS |
|
185 | 185 | GENERIC( |
|
186 | 186 | Input_SZ_A : INTEGER := 8; |
|
187 | 187 | Input_SZ_B : INTEGER := 8; |
|
188 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
188 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
189 | 189 | ); |
|
190 | 190 | PORT( |
|
191 | 191 | clk : IN STD_LOGIC; |
@@ -199,18 +199,18 Constant CLR_MAC_V0 : std_logic_vector(3 | |||
|
199 | 199 | ); |
|
200 | 200 | END COMPONENT; |
|
201 | 201 | |
|
202 |
COMPONENT TwoComplementer |
|
|
203 | generic( | |
|
204 |
Input_SZ : |
|
|
205 | port( | |
|
206 |
clk : |
|
|
207 |
reset : |
|
|
208 |
clr : |
|
|
209 |
TwoComp : |
|
|
210 |
OP : |
|
|
211 |
RES : |
|
|
212 | ); | |
|
213 |
|
|
|
202 | COMPONENT TwoComplementer IS | |
|
203 | GENERIC( | |
|
204 | Input_SZ : INTEGER := 16); | |
|
205 | PORT( | |
|
206 | clk : IN STD_LOGIC; --! Horloge du composant | |
|
207 | reset : IN STD_LOGIC; --! Reset general du composant | |
|
208 | clr : IN STD_LOGIC; --! Un reset spécifique au programme | |
|
209 | TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément | |
|
210 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée | |
|
211 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non | |
|
212 | ); | |
|
213 | END COMPONENT; | |
|
214 | 214 | |
|
215 | 215 | COMPONENT MAC_CONTROLER IS |
|
216 | 216 | PORT( |
@@ -275,19 +275,19 Constant CLR_MAC_V0 : std_logic_vector(3 | |||
|
275 | 275 | |
|
276 | 276 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
277 | 277 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; |
|
278 | ||
|
278 | ||
|
279 | 279 | COMPONENT MUXN |
|
280 | 280 | GENERIC ( |
|
281 | 281 | Input_SZ : INTEGER; |
|
282 | 282 | NbStage : INTEGER); |
|
283 | 283 | PORT ( |
|
284 | 284 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); |
|
285 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); | |
|
285 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0); | |
|
286 | 286 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
287 | 287 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); |
|
288 | 288 | END COMPONENT; |
|
289 | 289 | |
|
290 | ||
|
290 | ||
|
291 | 291 | |
|
292 | 292 | COMPONENT Multiplier IS |
|
293 | 293 | GENERIC( |
@@ -365,7 +365,7 Constant CLR_MAC_V0 : std_logic_vector(3 | |||
|
365 | 365 | sin : IN STD_LOGIC; |
|
366 | 366 | sout : OUT STD_LOGIC); |
|
367 | 367 | END COMPONENT; |
|
368 | ||
|
368 | ||
|
369 | 369 | --COMPONENT SYNC_VALID_BIT |
|
370 | 370 | -- GENERIC ( |
|
371 | 371 | -- NB_FF_OF_SYNC : INTEGER); |
@@ -397,11 +397,24 Constant CLR_MAC_V0 : std_logic_vector(3 | |||
|
397 | 397 | out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
398 | 398 | END COMPONENT; |
|
399 | 399 | |
|
400 |
COMPONENT Clock_Divider |
|
|
401 | generic(N :integer := 10); | |
|
402 | port( | |
|
403 | clk, rst : in std_logic; | |
|
404 | sclk : out std_logic); | |
|
405 |
|
|
|
400 | COMPONENT Clock_Divider IS | |
|
401 | GENERIC(N : INTEGER := 10); | |
|
402 | PORT( | |
|
403 | clk, rst : IN STD_LOGIC; | |
|
404 | sclk : OUT STD_LOGIC); | |
|
405 | END COMPONENT; | |
|
406 | ||
|
407 | COMPONENT ramp_generator | |
|
408 | GENERIC ( | |
|
409 | DATA_SIZE : INTEGER; | |
|
410 | VALUE_UNSIGNED_INIT : INTEGER; | |
|
411 | VALUE_UNSIGNED_INCR : INTEGER; | |
|
412 | VALUE_UNSIGNED_MASK : INTEGER); | |
|
413 | PORT ( | |
|
414 | clk : IN STD_LOGIC; | |
|
415 | rstn : IN STD_LOGIC; | |
|
416 | new_data : IN STD_LOGIC; | |
|
417 | output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); | |
|
418 | END COMPONENT; | |
|
406 | 419 | |
|
407 | 420 | END; |
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