@@ -0,0 +1,63 | |||
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1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------ | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------ | |
|
22 | library IEEE; | |
|
23 | use IEEE.std_logic_1164.all; | |
|
24 | use IEEE.numeric_std.all; | |
|
25 | ||
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26 | ENTITY ramp_generator IS | |
|
27 | ||
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28 | GENERIC ( | |
|
29 | DATA_SIZE : INTEGER := 16; | |
|
30 | VALUE_UNSIGNED_INIT : INTEGER := 0; | |
|
31 | VALUE_UNSIGNED_INCR : INTEGER := 1; | |
|
32 | VALUE_UNSIGNED_MASK : INTEGER := 16#FFFF#); | |
|
33 | ||
|
34 | PORT ( | |
|
35 | clk : IN STD_LOGIC; | |
|
36 | rstn : IN STD_LOGIC; | |
|
37 | new_data : IN STD_LOGIC; | |
|
38 | output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); | |
|
39 | ||
|
40 | END ramp_generator; | |
|
41 | ||
|
42 | ARCHITECTURE beh OF ramp_generator IS | |
|
43 | ||
|
44 | SIGNAL data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
|
45 | ||
|
46 | BEGIN -- beh | |
|
47 | ||
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48 | PROCESS (clk, rstn) | |
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49 | BEGIN -- PROCESS | |
|
50 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
51 | data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INIT,DATA_SIZE)) | |
|
52 | AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK,DATA_SIZE)); | |
|
53 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
54 | IF new_data = '1' THEN | |
|
55 | data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INCR + to_integer(UNSIGNED(data)),DATA_SIZE)) | |
|
56 | AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK ,DATA_SIZE)); | |
|
57 | END IF; | |
|
58 | END IF; | |
|
59 | END PROCESS; | |
|
60 | ||
|
61 | output_data <= data; | |
|
62 | ||
|
63 | END beh; |
@@ -1,520 +1,566 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.sim.ALL; |
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32 | 32 | USE gaisler.memctrl.ALL; |
|
33 | 33 | USE gaisler.leon3.ALL; |
|
34 | 34 | USE gaisler.uart.ALL; |
|
35 | 35 | USE gaisler.misc.ALL; |
|
36 | 36 | USE gaisler.spacewire.ALL; |
|
37 | 37 | LIBRARY esa; |
|
38 | 38 | USE esa.memoryctrl.ALL; |
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39 | 39 | LIBRARY lpp; |
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40 | 40 | USE lpp.lpp_memory.ALL; |
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41 | 41 | USE lpp.lpp_ad_conv.ALL; |
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42 | 42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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43 | 43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
44 | 44 | USE lpp.iir_filter.ALL; |
|
45 | 45 | USE lpp.general_purpose.ALL; |
|
46 | 46 | USE lpp.lpp_lfr_management.ALL; |
|
47 | 47 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
48 | 48 | USE lpp.lpp_bootloader_pkg.ALL; |
|
49 | 49 | |
|
50 | 50 | --library proasic3l; |
|
51 | 51 | --use proasic3l.all; |
|
52 | 52 | |
|
53 | 53 | ENTITY LFR_EQM IS |
|
54 | 54 | GENERIC ( |
|
55 | 55 | Mem_use : INTEGER := use_RAM; |
|
56 | USE_BOOTLOADER : INTEGER := 0 | |
|
56 | USE_BOOTLOADER : INTEGER := 0; | |
|
57 | USE_ADCDRIVER : INTEGER := 0; | |
|
58 | tech : INTEGER := apa3e; | |
|
59 | tech_leon : INTEGER := apa3e | |
|
57 | 60 | ); |
|
58 | 61 | |
|
59 | 62 | PORT ( |
|
60 | 63 | clk50MHz : IN STD_ULOGIC; |
|
61 | 64 | clk49_152MHz : IN STD_ULOGIC; |
|
62 | 65 | reset : IN STD_ULOGIC; |
|
63 | 66 | |
|
64 | 67 | -- TAG -------------------------------------------------------------------- |
|
65 | 68 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
|
66 | 69 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
|
67 | 70 | -- UART APB --------------------------------------------------------------- |
|
68 | 71 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
|
69 | 72 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
|
70 | 73 | -- RAM -------------------------------------------------------------------- |
|
71 | 74 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
72 | 75 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | 76 | |
|
74 | 77 | nSRAM_MBE : INOUT STD_LOGIC; -- new |
|
75 | 78 | nSRAM_E1 : OUT STD_LOGIC; -- new |
|
76 | 79 | nSRAM_E2 : OUT STD_LOGIC; -- new |
|
77 | 80 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new |
|
78 | 81 | nSRAM_W : OUT STD_LOGIC; -- new |
|
79 | 82 | nSRAM_G : OUT STD_LOGIC; -- new |
|
80 | 83 | nSRAM_BUSY : IN STD_LOGIC; -- new |
|
81 | 84 | -- SPW -------------------------------------------------------------------- |
|
82 | 85 | spw1_en : OUT STD_LOGIC; -- new |
|
83 | 86 | spw1_din : IN STD_LOGIC; |
|
84 | 87 | spw1_sin : IN STD_LOGIC; |
|
85 | 88 | spw1_dout : OUT STD_LOGIC; |
|
86 | 89 | spw1_sout : OUT STD_LOGIC; |
|
87 | 90 | spw2_en : OUT STD_LOGIC; -- new |
|
88 | 91 | spw2_din : IN STD_LOGIC; |
|
89 | 92 | spw2_sin : IN STD_LOGIC; |
|
90 | 93 | spw2_dout : OUT STD_LOGIC; |
|
91 | 94 | spw2_sout : OUT STD_LOGIC; |
|
92 | 95 | -- ADC -------------------------------------------------------------------- |
|
93 | 96 | bias_fail_sw : OUT STD_LOGIC; |
|
94 | 97 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
95 | 98 | ADC_smpclk : OUT STD_LOGIC; |
|
96 | 99 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
97 | 100 | -- DAC -------------------------------------------------------------------- |
|
98 | 101 | DAC_SDO : OUT STD_LOGIC; |
|
99 | 102 | DAC_SCK : OUT STD_LOGIC; |
|
100 | 103 | DAC_SYNC : OUT STD_LOGIC; |
|
101 | 104 | DAC_CAL_EN : OUT STD_LOGIC; |
|
102 | 105 | -- HK --------------------------------------------------------------------- |
|
103 | 106 | HK_smpclk : OUT STD_LOGIC; |
|
104 | 107 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
|
105 | 108 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
106 | 109 | --------------------------------------------------------------------------- |
|
107 | 110 | TAG8 : OUT STD_LOGIC |
|
108 | 111 | ); |
|
109 | 112 | |
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110 | 113 | END LFR_EQM; |
|
111 | 114 | |
|
112 | 115 | |
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113 | 116 | ARCHITECTURE beh OF LFR_EQM IS |
|
114 | 117 | |
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115 | 118 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
116 | 119 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
117 | 120 | ----------------------------------------------------------------------------- |
|
118 | 121 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | 122 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
120 | 123 | |
|
121 | 124 | -- CONSTANTS |
|
122 | 125 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
123 | 126 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
124 | 127 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
125 | 128 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
126 | 129 | |
|
127 | 130 | SIGNAL apbi_ext : apb_slv_in_type; |
|
128 | 131 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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129 | 132 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
130 | 133 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
131 | 134 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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132 | 135 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
133 | 136 | |
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134 | 137 | -- Spacewire signals |
|
135 | 138 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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136 | 139 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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137 | 140 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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138 | 141 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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139 | 142 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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140 | 143 | SIGNAL spw_clk : STD_LOGIC; |
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141 | 144 | SIGNAL swni : grspw_in_type; |
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142 | 145 | SIGNAL swno : grspw_out_type; |
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143 | 146 | |
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144 | 147 | --GPIO |
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145 | 148 | SIGNAL gpioi : gpio_in_type; |
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146 | 149 | SIGNAL gpioo : gpio_out_type; |
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147 | 150 | |
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148 | 151 | -- AD Converter ADS7886 |
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149 | 152 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
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150 | 153 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
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151 | 154 | SIGNAL sample_val : STD_LOGIC; |
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152 | 155 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
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153 | 156 | |
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154 | 157 | ----------------------------------------------------------------------------- |
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155 | 158 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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156 | 159 | |
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157 | 160 | ----------------------------------------------------------------------------- |
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158 | 161 | SIGNAL rstn_25 : STD_LOGIC; |
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159 | 162 | SIGNAL rstn_24 : STD_LOGIC; |
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160 | 163 | |
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161 | 164 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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162 | 165 | SIGNAL LFR_rstn : STD_LOGIC; |
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163 | 166 | |
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164 | 167 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
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165 | 168 | |
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166 | 169 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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167 | 170 | |
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168 | 171 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; |
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169 | 172 | SIGNAL clk_25_int : STD_LOGIC := '0'; |
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170 | 173 | |
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171 | 174 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; |
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172 | 175 | |
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173 | 176 | SIGNAL rstn_50 : STD_LOGIC; |
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174 | 177 | SIGNAL clk_lock : STD_LOGIC; |
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175 | 178 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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176 | 179 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; |
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177 | 180 | BEGIN -- beh |
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178 | 181 | |
|
179 | 182 | ----------------------------------------------------------------------------- |
|
180 | 183 | -- CLK_LOCK |
|
181 | 184 | ----------------------------------------------------------------------------- |
|
182 |
rst_gen_global : rstgen PORT MAP (reset, clk |
|
|
185 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); | |
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183 | 186 | |
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184 | 187 | PROCESS (clk50MHz_int, rstn_50) |
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185 | 188 | BEGIN -- PROCESS |
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186 | 189 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
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187 | 190 | clk_lock <= '0'; |
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188 | 191 | clk_busy_counter <= (OTHERS => '0'); |
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189 | 192 | nSRAM_BUSY_reg <= '0'; |
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190 | 193 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge |
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191 | 194 | nSRAM_BUSY_reg <= nSRAM_BUSY; |
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192 | 195 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN |
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193 | 196 | IF clk_busy_counter = "1111" THEN |
|
194 | clk_lock = '1'; | |
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197 | clk_lock <= '1'; | |
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195 | 198 | ELSE |
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196 | 199 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); |
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197 | 200 | END IF; |
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198 | 201 | END IF; |
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199 | 202 | END IF; |
|
200 | 203 | END PROCESS; |
|
201 | 204 | |
|
202 | 205 | ----------------------------------------------------------------------------- |
|
203 | 206 | -- CLK |
|
204 | 207 | ----------------------------------------------------------------------------- |
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205 | 208 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); |
|
206 | 209 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); |
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207 | 210 | |
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208 | 211 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); |
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209 | 212 | clk50MHz_int <= clk50MHz; |
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210 | 213 | |
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211 | 214 | PROCESS(clk50MHz_int) |
|
212 | 215 | BEGIN |
|
213 | 216 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN |
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214 | 217 | --clk_25_int <= NOT clk_25_int; |
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215 | 218 | clk_25 <= NOT clk_25; |
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216 | 219 | END IF; |
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217 | 220 | END PROCESS; |
|
218 | 221 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); |
|
219 | 222 | |
|
220 | 223 | PROCESS(clk49_152MHz) |
|
221 | 224 | BEGIN |
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222 | 225 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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223 | 226 | clk_24 <= NOT clk_24; |
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224 | 227 | END IF; |
|
225 | 228 | END PROCESS; |
|
226 | 229 | |
|
227 | 230 | ----------------------------------------------------------------------------- |
|
228 | 231 | -- |
|
229 | 232 | leon3_soc_1 : leon3_soc |
|
230 | 233 | GENERIC MAP ( |
|
231 |
fabtech => |
|
|
232 |
memtech => |
|
|
234 | fabtech => tech_leon, | |
|
235 | memtech => tech_leon, | |
|
233 | 236 | padtech => inferred, |
|
234 | 237 | clktech => inferred, |
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235 | 238 | disas => 0, |
|
236 | 239 | dbguart => 0, |
|
237 | 240 | pclow => 2, |
|
238 | 241 | clk_freq => 25000, |
|
239 | 242 | IS_RADHARD => 0, |
|
240 | 243 | NB_CPU => 1, |
|
241 | 244 | ENABLE_FPU => 1, |
|
242 | 245 | FPU_NETLIST => 0, |
|
243 | 246 | ENABLE_DSU => 1, |
|
244 | 247 | ENABLE_AHB_UART => 1, |
|
245 | 248 | ENABLE_APB_UART => 1, |
|
246 | 249 | ENABLE_IRQMP => 1, |
|
247 | 250 | ENABLE_GPT => 1, |
|
248 | 251 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
249 | 252 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
250 | 253 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
251 | 254 | ADDRESS_SIZE => 19, |
|
252 | 255 | USES_IAP_MEMCTRLR => 1, |
|
253 | 256 | BYPASS_EDAC_MEMCTRLR => '0', |
|
254 | 257 | SRBANKSZ => 8) |
|
255 | 258 | PORT MAP ( |
|
256 | 259 | clk => clk_25, |
|
257 | 260 | reset => rstn_25, |
|
258 | 261 | errorn => OPEN, |
|
259 | 262 | |
|
260 | 263 | ahbrxd => TAG1, |
|
261 | 264 | ahbtxd => TAG3, |
|
262 | 265 | urxd1 => TAG2, |
|
263 | 266 | utxd1 => TAG4, |
|
264 | 267 | |
|
265 | 268 | address => address, |
|
266 | 269 | data => data, |
|
267 | 270 | nSRAM_BE0 => OPEN, |
|
268 | 271 | nSRAM_BE1 => OPEN, |
|
269 | 272 | nSRAM_BE2 => OPEN, |
|
270 | 273 | nSRAM_BE3 => OPEN, |
|
271 | 274 | nSRAM_WE => nSRAM_W, |
|
272 | 275 | nSRAM_CE => nSRAM_CE, |
|
273 | 276 | nSRAM_OE => nSRAM_G, |
|
274 | 277 | nSRAM_READY => nSRAM_BUSY, |
|
275 | 278 | SRAM_MBE => nSRAM_MBE, |
|
276 | 279 | |
|
277 | 280 | apbi_ext => apbi_ext, |
|
278 | 281 | apbo_ext => apbo_ext, |
|
279 | 282 | ahbi_s_ext => ahbi_s_ext, |
|
280 | 283 | ahbo_s_ext => ahbo_s_ext, |
|
281 | 284 | ahbi_m_ext => ahbi_m_ext, |
|
282 | 285 | ahbo_m_ext => ahbo_m_ext); |
|
283 | 286 | |
|
284 | 287 | |
|
285 | 288 | nSRAM_E1 <= nSRAM_CE(0); |
|
286 | 289 | nSRAM_E2 <= nSRAM_CE(1); |
|
287 | 290 | |
|
288 | 291 | ------------------------------------------------------------------------------- |
|
289 | 292 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
290 | 293 | ------------------------------------------------------------------------------- |
|
291 | 294 | apb_lfr_management_1 : apb_lfr_management |
|
292 | 295 | GENERIC MAP ( |
|
293 |
tech => |
|
|
296 | tech => tech, | |
|
294 | 297 | pindex => 6, |
|
295 | 298 | paddr => 6, |
|
296 | 299 | pmask => 16#fff#, |
|
297 | 300 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
298 | 301 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
299 | 302 | PORT MAP ( |
|
300 | 303 | clk25MHz => clk_25, |
|
301 | 304 | resetn_25MHz => rstn_25, -- TODO |
|
302 | 305 | --clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
303 | 306 | --resetn_24_576MHz => rstn_24, -- TODO |
|
304 | 307 | |
|
305 | 308 | grspw_tick => swno.tickout, |
|
306 | 309 | apbi => apbi_ext, |
|
307 | 310 | apbo => apbo_ext(6), |
|
308 | 311 | |
|
309 | 312 | HK_sample => sample_s(8), |
|
310 | 313 | HK_val => sample_val, |
|
311 | 314 | HK_sel => HK_SEL, |
|
312 | 315 | |
|
313 | 316 | DAC_SDO => DAC_SDO, |
|
314 | 317 | DAC_SCK => DAC_SCK, |
|
315 | 318 | DAC_SYNC => DAC_SYNC, |
|
316 | 319 | DAC_CAL_EN => DAC_CAL_EN, |
|
317 | 320 | |
|
318 | 321 | coarse_time => coarse_time, |
|
319 | 322 | fine_time => fine_time, |
|
320 | 323 | LFR_soft_rstn => LFR_soft_rstn |
|
321 | 324 | ); |
|
322 | 325 | |
|
323 | 326 | ----------------------------------------------------------------------- |
|
324 | 327 | --- SpaceWire -------------------------------------------------------- |
|
325 | 328 | ----------------------------------------------------------------------- |
|
326 | 329 | |
|
327 | 330 | ------------------------------------------------------------------------------ |
|
328 | 331 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ |
|
329 | 332 | ------------------------------------------------------------------------------ |
|
330 | 333 | spw1_en <= '1'; |
|
331 | 334 | spw2_en <= '1'; |
|
332 | 335 | ------------------------------------------------------------------------------ |
|
333 | 336 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ |
|
334 | 337 | ------------------------------------------------------------------------------ |
|
335 | 338 | |
|
336 | 339 | --spw_clk <= clk50MHz; |
|
337 | 340 | --spw_rxtxclk <= spw_clk; |
|
338 | 341 | --spw_rxclkn <= NOT spw_rxtxclk; |
|
339 | 342 | |
|
340 | 343 | -- PADS for SPW1 |
|
341 | 344 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
342 | 345 | PORT MAP (spw1_din, dtmp(0)); |
|
343 | 346 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
344 | 347 | PORT MAP (spw1_sin, stmp(0)); |
|
345 | 348 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
346 | 349 | PORT MAP (spw1_dout, swno.d(0)); |
|
347 | 350 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
348 | 351 | PORT MAP (spw1_sout, swno.s(0)); |
|
349 | 352 | -- PADS FOR SPW2 |
|
350 | 353 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
351 | 354 | PORT MAP (spw2_din, dtmp(1)); |
|
352 | 355 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
353 | 356 | PORT MAP (spw2_sin, stmp(1)); |
|
354 | 357 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
355 | 358 | PORT MAP (spw2_dout, swno.d(1)); |
|
356 | 359 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
357 | 360 | PORT MAP (spw2_sout, swno.s(1)); |
|
358 | 361 | |
|
359 | 362 | -- GRSPW PHY |
|
360 | 363 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
361 | 364 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
362 | 365 | spw_phy0 : grspw_phy |
|
363 | 366 | GENERIC MAP( |
|
364 |
tech => |
|
|
367 | tech => tech_leon, | |
|
365 | 368 | rxclkbuftype => 1, |
|
366 | 369 | scantest => 0) |
|
367 | 370 | PORT MAP( |
|
368 | 371 | rxrst => swno.rxrst, |
|
369 | 372 | di => dtmp(j), |
|
370 | 373 | si => stmp(j), |
|
371 | 374 | rxclko => spw_rxclk(j), |
|
372 | 375 | do => swni.d(j), |
|
373 | 376 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
374 | 377 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
375 | 378 | END GENERATE spw_inputloop; |
|
376 | 379 | |
|
377 | 380 | -- SPW core |
|
378 | 381 | sw0 : grspwm GENERIC MAP( |
|
379 |
tech => |
|
|
382 | tech => tech_leon, | |
|
380 | 383 | hindex => 1, |
|
381 | 384 | pindex => 5, |
|
382 | 385 | paddr => 5, |
|
383 | 386 | pirq => 11, |
|
384 | 387 | sysfreq => 25000, -- CPU_FREQ |
|
385 | 388 | rmap => 1, |
|
386 | 389 | rmapcrc => 1, |
|
387 | 390 | fifosize1 => 16, |
|
388 | 391 | fifosize2 => 16, |
|
389 | 392 | rxclkbuftype => 1, |
|
390 | 393 | rxunaligned => 0, |
|
391 | 394 | rmapbufs => 4, |
|
392 | 395 | ft => 0, |
|
393 | 396 | netlist => 0, |
|
394 | 397 | ports => 2, |
|
395 | 398 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
396 |
memtech => |
|
|
399 | memtech => tech_leon, | |
|
397 | 400 | destkey => 2, |
|
398 | 401 | spwcore => 1 |
|
399 | 402 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
400 | 403 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
401 | 404 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
402 | 405 | ) |
|
403 | 406 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
404 | 407 | spw_rxclk(1), |
|
405 | 408 | clk50MHz_int, |
|
406 | 409 | clk50MHz_int, |
|
407 | 410 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, |
|
408 | 411 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
409 | 412 | swni, swno); |
|
410 | 413 | |
|
411 | 414 | swni.tickin <= '0'; |
|
412 | 415 | swni.rmapen <= '1'; |
|
413 | 416 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
|
414 | 417 | swni.tickinraw <= '0'; |
|
415 | 418 | swni.timein <= (OTHERS => '0'); |
|
416 | 419 | swni.dcrstval <= (OTHERS => '0'); |
|
417 | 420 | swni.timerrstval <= (OTHERS => '0'); |
|
418 | 421 | |
|
419 | 422 | ------------------------------------------------------------------------------- |
|
420 | 423 | -- LFR ------------------------------------------------------------------------ |
|
421 | 424 | ------------------------------------------------------------------------------- |
|
422 | 425 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
423 | 426 | |
|
424 | 427 | lpp_lfr_1 : lpp_lfr |
|
425 | 428 | GENERIC MAP ( |
|
426 | 429 | Mem_use => Mem_use, |
|
427 | 430 | nb_data_by_buffer_size => 32, |
|
428 | 431 | --nb_word_by_buffer_size => 30, |
|
429 | 432 | nb_snapshot_param_size => 32, |
|
430 | 433 | delta_vector_size => 32, |
|
431 | 434 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
432 | 435 | pindex => 15, |
|
433 | 436 | paddr => 15, |
|
434 | 437 | pmask => 16#fff#, |
|
435 | 438 | pirq_ms => 6, |
|
436 | 439 | pirq_wfp => 14, |
|
437 | 440 | hindex => 2, |
|
438 | 441 | top_lfr_version => X"020147") -- aa.bb.cc version |
|
439 | 442 | -- AA : BOARD NUMBER |
|
440 | 443 | -- 0 => MINI_LFR |
|
441 | 444 | -- 1 => EM |
|
442 | 445 | -- 2 => EQM (with A3PE3000) |
|
443 | 446 | PORT MAP ( |
|
444 | 447 | clk => clk_25, |
|
445 | 448 | rstn => LFR_rstn, |
|
446 | 449 | sample_B => sample_s(2 DOWNTO 0), |
|
447 | 450 | sample_E => sample_s(7 DOWNTO 3), |
|
448 | 451 | sample_val => sample_val, |
|
449 | 452 | apbi => apbi_ext, |
|
450 | 453 | apbo => apbo_ext(15), |
|
451 | 454 | ahbi => ahbi_m_ext, |
|
452 | 455 | ahbo => ahbo_m_ext(2), |
|
453 | 456 | coarse_time => coarse_time, |
|
454 | 457 | fine_time => fine_time, |
|
455 | 458 | data_shaping_BW => bias_fail_sw, |
|
456 | 459 | debug_vector => OPEN, |
|
457 | 460 | debug_vector_ms => OPEN); --, |
|
458 | 461 | --observation_vector_0 => OPEN, |
|
459 | 462 | --observation_vector_1 => OPEN, |
|
460 | 463 | --observation_reg => observation_reg); |
|
461 | 464 | |
|
462 | 465 | |
|
463 | 466 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
464 | 467 | sample_s(I) <= sample(I) & '0' & '0'; |
|
465 | 468 | END GENERATE all_sample; |
|
466 | 469 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
467 | 470 | |
|
468 | 471 | ----------------------------------------------------------------------------- |
|
469 | 472 | -- |
|
470 | 473 | ----------------------------------------------------------------------------- |
|
471 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
|
472 | GENERIC MAP ( | |
|
473 | ChanelCount => 9, | |
|
474 | ncycle_cnv_high => 13, | |
|
475 |
ncycle_cnv |
|
|
476 | FILTER_ENABLED => 16#FF#) | |
|
477 | PORT MAP ( | |
|
478 | cnv_clk => clk_24, | |
|
479 |
|
|
|
480 | cnv => ADC_smpclk_s, | |
|
481 |
|
|
|
482 |
|
|
|
483 | ADC_data => ADC_data, | |
|
484 |
|
|
|
485 | sample => sample, | |
|
486 |
sample |
|
|
474 | USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE | |
|
475 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
|
476 | GENERIC MAP ( | |
|
477 | ChanelCount => 9, | |
|
478 | ncycle_cnv_high => 13, | |
|
479 | ncycle_cnv => 25, | |
|
480 | FILTER_ENABLED => 16#FF#) | |
|
481 | PORT MAP ( | |
|
482 | cnv_clk => clk_24, | |
|
483 | cnv_rstn => rstn_24, | |
|
484 | cnv => ADC_smpclk_s, | |
|
485 | clk => clk_25, | |
|
486 | rstn => rstn_25, | |
|
487 | ADC_data => ADC_data, | |
|
488 | ADC_nOE => ADC_OEB_bar_CH_s, | |
|
489 | sample => sample, | |
|
490 | sample_val => sample_val); | |
|
491 | ||
|
492 | END GENERATE USE_ADCDRIVER_true; | |
|
493 | ||
|
494 | USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE | |
|
495 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
|
496 | GENERIC MAP ( | |
|
497 | ChanelCount => 9, | |
|
498 | ncycle_cnv_high => 13, | |
|
499 | ncycle_cnv => 25, | |
|
500 | FILTER_ENABLED => 16#FF#) | |
|
501 | PORT MAP ( | |
|
502 | cnv_clk => clk_24, | |
|
503 | cnv_rstn => rstn_24, | |
|
504 | cnv => ADC_smpclk_s, | |
|
505 | clk => clk_25, | |
|
506 | rstn => rstn_25, | |
|
507 | ADC_data => ADC_data, | |
|
508 | ADC_nOE => OPEN, | |
|
509 | sample => OPEN, | |
|
510 | sample_val => sample_val); | |
|
511 | ||
|
512 | ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); | |
|
487 | 513 | |
|
514 | all_sample: FOR I IN 8 DOWNTO 0 GENERATE | |
|
515 | ramp_generator_1: ramp_generator | |
|
516 | GENERIC MAP ( | |
|
517 | DATA_SIZE => 14, | |
|
518 | VALUE_UNSIGNED_INIT => 2**I, | |
|
519 | VALUE_UNSIGNED_INCR => 0, | |
|
520 | VALUE_UNSIGNED_MASK => 16#3FFF#) | |
|
521 | PORT MAP ( | |
|
522 | clk => clk_25, | |
|
523 | rstn => rstn_25, | |
|
524 | new_data => sample_val, | |
|
525 | output_data => sample(I) ); | |
|
526 | END GENERATE all_sample; | |
|
527 | ||
|
528 | ||
|
529 | END GENERATE USE_ADCDRIVER_false; | |
|
530 | ||
|
531 | ||
|
532 | ||
|
533 | ||
|
488 | 534 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
489 | 535 | |
|
490 | 536 | ADC_smpclk <= ADC_smpclk_s; |
|
491 | 537 | HK_smpclk <= ADC_smpclk_s; |
|
492 | 538 | |
|
493 | 539 | TAG8 <= nSRAM_BUSY; |
|
494 | 540 | |
|
495 | 541 | ----------------------------------------------------------------------------- |
|
496 | 542 | -- HK |
|
497 | 543 | ----------------------------------------------------------------------------- |
|
498 | 544 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
499 | 545 | |
|
500 | 546 | ----------------------------------------------------------------------------- |
|
501 | 547 | -- |
|
502 | 548 | ----------------------------------------------------------------------------- |
|
503 | 549 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE |
|
504 | 550 | lpp_bootloader_1: lpp_bootloader |
|
505 | 551 | GENERIC MAP ( |
|
506 | 552 | pindex => 13, |
|
507 | 553 | paddr => 13, |
|
508 | 554 | pmask => 16#fff#, |
|
509 | 555 | hindex => 3, |
|
510 | 556 | haddr => 0, |
|
511 | 557 | hmask => 16#fff#) |
|
512 | 558 | PORT MAP ( |
|
513 | 559 | HCLK => clk_25, |
|
514 | 560 | HRESETn => rstn_25, |
|
515 | 561 | apbi => apbi_ext, |
|
516 | 562 | apbo => apbo_ext(13), |
|
517 | 563 | ahbsi => ahbi_s_ext, |
|
518 | 564 | ahbso => ahbo_s_ext(3)); |
|
519 | 565 | END GENERATE inst_bootloader; |
|
520 | 566 | END beh; |
@@ -1,54 +1,54 | |||
|
1 | 1 | #GRLIB=../.. |
|
2 | 2 | VHDLIB=../.. |
|
3 | 3 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
4 | 4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
5 | 5 | TOP=LFR_EQM |
|
6 | 6 | BOARD=LFR-EQM |
|
7 | 7 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc |
|
8 | 8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
9 | 9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf |
|
10 | 10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf |
|
11 | 11 | EFFORT=high |
|
12 | 12 | XSTOPT= |
|
13 | 13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
14 | 14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
|
15 | 15 | #VHDLSYNFILES=config.vhd leon3mp.vhd |
|
16 | 16 | VHDLSYNFILES=LFR-EQM.vhd |
|
17 | 17 | VHDLSIMFILES=testbench.vhd |
|
18 | 18 | #SIMTOP=testbench |
|
19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc | |
|
19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000_NoADC.pdc | |
|
20 | 20 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc |
|
21 | 21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc |
|
22 | 22 | |
|
23 | 23 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
|
24 | 24 | CLEAN=soft-clean |
|
25 | 25 | |
|
26 | 26 | TECHLIBS = proasic3e |
|
27 | 27 | |
|
28 | 28 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
29 | 29 | tmtc openchip hynix ihp gleichmann micron usbhc |
|
30 | 30 | |
|
31 | 31 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
|
32 | 32 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
|
33 | 33 | ./amba_lcd_16x2_ctrlr \ |
|
34 | 34 | ./general_purpose/lpp_AMR \ |
|
35 | 35 | ./general_purpose/lpp_balise \ |
|
36 | 36 | ./general_purpose/lpp_delay \ |
|
37 | 37 | ./dsp/lpp_fft_rtax \ |
|
38 | 38 | ./lpp_uart \ |
|
39 | 39 | ./lpp_usb \ |
|
40 | 40 | ./lpp_sim/CY7C1061DV33 \ |
|
41 | 41 | |
|
42 | 42 | FILESKIP = i2cmst.vhd \ |
|
43 | 43 | APB_MULTI_DIODE.vhd \ |
|
44 | 44 | APB_MULTI_DIODE.vhd \ |
|
45 | 45 | Top_MatrixSpec.vhd \ |
|
46 | 46 | APB_FFT.vhd\ |
|
47 | 47 | CoreFFT_simu.vhd \ |
|
48 | 48 | lpp_lfr_apbreg_simu.vhd |
|
49 | 49 | |
|
50 | 50 | include $(GRLIB)/bin/Makefile |
|
51 | 51 | include $(GRLIB)/software/leon3/Makefile |
|
52 | 52 | |
|
53 | 53 | ################## project specific targets ########################## |
|
54 | 54 |
@@ -1,657 +1,672 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | |
|
23 | 23 | LIBRARY IEEE; |
|
24 | 24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
|
26 | 26 | |
|
27 | LIBRARY techmap; | |
|
28 | USE techmap.gencomp.ALL; | |
|
27 | 29 | |
|
28 | 30 | LIBRARY lpp; |
|
29 | 31 | USE lpp.lpp_sim_pkg.ALL; |
|
30 | 32 | USE lpp.lpp_lfr_sim_pkg.ALL; |
|
31 | 33 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
32 | 34 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
33 | 35 | USE lpp.iir_filter.ALL; |
|
34 | 36 | USE lpp.FILTERcfg.ALL; |
|
35 | 37 | USE lpp.lpp_memory.ALL; |
|
36 | 38 | USE lpp.lpp_waveform_pkg.ALL; |
|
37 | 39 | USE lpp.lpp_dma_pkg.ALL; |
|
38 | 40 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
39 | 41 | USE lpp.lpp_lfr_pkg.ALL; |
|
40 | 42 | USE lpp.general_purpose.ALL; |
|
41 | 43 | --LIBRARY lpp; |
|
42 | 44 | USE lpp.lpp_ad_conv.ALL; |
|
43 | 45 | --USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
44 | 46 | --USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
45 | 47 | |
|
46 | 48 | --USE work.debug.ALL; |
|
47 | 49 | |
|
48 | 50 | LIBRARY gaisler; |
|
49 | 51 | USE gaisler.libdcom.ALL; |
|
50 | 52 | USE gaisler.sim.ALL; |
|
51 | 53 | USE gaisler.memctrl.ALL; |
|
52 | 54 | USE gaisler.leon3.ALL; |
|
53 | 55 | USE gaisler.uart.ALL; |
|
54 | 56 | USE gaisler.misc.ALL; |
|
55 | 57 | USE gaisler.spacewire.ALL; |
|
56 | 58 | |
|
57 | 59 | ENTITY TB IS |
|
58 | 60 | |
|
59 | 61 | END TB; |
|
60 | 62 | |
|
61 | 63 | ARCHITECTURE beh OF TB IS |
|
62 | 64 | |
|
63 | 65 | CONSTANT USE_ESA_MEMCTRL : INTEGER := 0; |
|
64 | 66 | |
|
65 | 67 | COMPONENT LFR_EQM |
|
66 | 68 | GENERIC ( |
|
67 | 69 | Mem_use : INTEGER; |
|
68 |
USE_BOOTLOADER : INTEGER |
|
|
70 | USE_BOOTLOADER : INTEGER; | |
|
71 | USE_ADCDRIVER : INTEGER; | |
|
72 | tech : INTEGER; | |
|
73 | tech_leon : INTEGER); | |
|
69 | 74 | PORT ( |
|
70 | 75 | clk50MHz : IN STD_ULOGIC; |
|
71 | 76 | clk49_152MHz : IN STD_ULOGIC; |
|
72 | 77 | reset : IN STD_ULOGIC; |
|
73 | 78 | TAG1 : IN STD_ULOGIC; |
|
74 | 79 | TAG3 : OUT STD_ULOGIC; |
|
75 | 80 | TAG2 : IN STD_ULOGIC; |
|
76 | 81 | TAG4 : OUT STD_ULOGIC; |
|
77 | 82 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
78 | 83 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | 84 | nSRAM_MBE : INOUT STD_LOGIC; |
|
80 | 85 | nSRAM_E1 : OUT STD_LOGIC; |
|
81 | 86 | nSRAM_E2 : OUT STD_LOGIC; |
|
82 | 87 | nSRAM_W : OUT STD_LOGIC; |
|
83 | 88 | nSRAM_G : OUT STD_LOGIC; |
|
84 | 89 | nSRAM_BUSY : IN STD_LOGIC; |
|
85 | 90 | spw1_en : OUT STD_LOGIC; |
|
86 | 91 | spw1_din : IN STD_LOGIC; |
|
87 | 92 | spw1_sin : IN STD_LOGIC; |
|
88 | 93 | spw1_dout : OUT STD_LOGIC; |
|
89 | 94 | spw1_sout : OUT STD_LOGIC; |
|
90 | 95 | spw2_en : OUT STD_LOGIC; |
|
91 | 96 | spw2_din : IN STD_LOGIC; |
|
92 | 97 | spw2_sin : IN STD_LOGIC; |
|
93 | 98 | spw2_dout : OUT STD_LOGIC; |
|
94 | 99 | spw2_sout : OUT STD_LOGIC; |
|
95 | 100 | bias_fail_sw : OUT STD_LOGIC; |
|
96 | 101 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
97 | 102 | ADC_smpclk : OUT STD_LOGIC; |
|
98 | 103 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
99 | 104 | DAC_SDO : OUT STD_LOGIC; |
|
100 | 105 | DAC_SCK : OUT STD_LOGIC; |
|
101 | 106 | DAC_SYNC : OUT STD_LOGIC; |
|
102 | 107 | DAC_CAL_EN : OUT STD_LOGIC; |
|
103 | 108 | HK_smpclk : OUT STD_LOGIC; |
|
104 | 109 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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105 | 110 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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106 | 111 | TAG8 : OUT STD_LOGIC); |
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107 | 112 | END COMPONENT; |
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108 | 113 | |
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109 | 114 | SIGNAL clk50MHz : STD_ULOGIC := '0'; |
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110 | 115 | SIGNAL clk49_152MHz : STD_ULOGIC := '0'; |
|
111 | 116 | SIGNAL reset : STD_ULOGIC; |
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112 | 117 | SIGNAL TAG1 : STD_ULOGIC := '1'; |
|
113 | 118 | SIGNAL TAG3 : STD_ULOGIC; |
|
114 | 119 | SIGNAL TAG2 : STD_ULOGIC := '1'; |
|
115 | 120 | SIGNAL TAG4 : STD_ULOGIC; |
|
116 | 121 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
117 | 122 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | 123 | SIGNAL nSRAM_MBE : STD_LOGIC; |
|
119 | 124 | SIGNAL nSRAM_E1 : STD_LOGIC; |
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120 | 125 | SIGNAL nSRAM_E2 : STD_LOGIC; |
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121 | 126 | SIGNAL nSRAM_W : STD_LOGIC; |
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122 | 127 | SIGNAL nSRAM_G : STD_LOGIC; |
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123 | 128 | SIGNAL nSRAM_BUSY : STD_LOGIC; |
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124 | 129 | SIGNAL spw1_en : STD_LOGIC; |
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125 | 130 | SIGNAL spw1_din : STD_LOGIC := '1'; |
|
126 | 131 | SIGNAL spw1_sin : STD_LOGIC := '1'; |
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127 | 132 | SIGNAL spw1_dout : STD_LOGIC; |
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128 | 133 | SIGNAL spw1_sout : STD_LOGIC; |
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129 | 134 | SIGNAL spw2_en : STD_LOGIC; |
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130 | 135 | SIGNAL spw2_din : STD_LOGIC := '1'; |
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131 | 136 | SIGNAL spw2_sin : STD_LOGIC := '1'; |
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132 | 137 | SIGNAL spw2_dout : STD_LOGIC; |
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133 | 138 | SIGNAL spw2_sout : STD_LOGIC; |
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134 | 139 | SIGNAL bias_fail_sw : STD_LOGIC; |
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135 | 140 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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136 | 141 | SIGNAL ADC_smpclk : STD_LOGIC; |
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137 | 142 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); |
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138 | 143 | SIGNAL DAC_SDO : STD_LOGIC; |
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139 | 144 | SIGNAL DAC_SCK : STD_LOGIC; |
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140 | 145 | SIGNAL DAC_SYNC : STD_LOGIC; |
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141 | 146 | SIGNAL DAC_CAL_EN : STD_LOGIC; |
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142 | 147 | SIGNAL HK_smpclk : STD_LOGIC; |
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143 | 148 | SIGNAL ADC_OEB_bar_HK : STD_LOGIC; |
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144 | 149 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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145 | 150 | SIGNAL TAG8 : STD_LOGIC; |
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146 | 151 | |
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147 | 152 | CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20; |
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148 | 153 | CONSTANT SCRUB_PERIOD : INTEGER := 200/20; |
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149 | 154 | CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20; |
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150 | 155 | CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20; |
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151 | 156 | SIGNAL counter_scrub_period : INTEGER; |
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152 | 157 | |
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153 | 158 | |
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154 | 159 | --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800"; |
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155 | 160 | --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006"; |
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156 | 161 | --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F"; |
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157 | 162 | |
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158 | 163 | CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90"; |
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159 | 164 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; |
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160 | 165 | CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E"; |
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161 | 166 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; |
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162 | 167 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; |
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163 | 168 | CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000"; |
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164 | 169 | |
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165 | 170 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; |
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166 | 171 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; |
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167 | 172 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); |
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168 | 173 | SIGNAL TXD1 : STD_LOGIC; |
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169 | 174 | SIGNAL RXD1 : STD_LOGIC; |
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170 | 175 | |
|
171 | 176 | ----------------------------------------------------------------------------- |
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172 | 177 | CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000"; |
|
173 | 178 | CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000"; |
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174 | 179 | CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000"; |
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175 | 180 | CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000"; |
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176 | 181 | CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000"; |
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177 | 182 | CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000"; |
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178 | 183 | CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000"; |
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179 | 184 | CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000"; |
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180 | 185 | CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000"; |
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181 | 186 | CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000"; |
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182 | 187 | CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000"; |
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183 | 188 | CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000"; |
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184 | 189 | CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000"; |
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185 | 190 | CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000"; |
|
186 | 191 | |
|
187 | 192 | |
|
188 | 193 | TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
189 | 194 | SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0); |
|
190 | 195 | |
|
191 | 196 | TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
|
192 | 197 | SIGNAL sample_counter : counter_vector( 2 DOWNTO 0); |
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193 | 198 | |
|
194 | 199 | SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
195 | 200 | SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | 201 | SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | 202 | SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
198 | 203 | |
|
199 | 204 | SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
200 | 205 | SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
201 | 206 | SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
202 | 207 | |
|
203 | 208 | |
|
204 | 209 | SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
205 | 210 | ----------------------------------------------------------------------------- |
|
206 | 211 | CONSTANT srambanks : INTEGER := 2; |
|
207 | 212 | CONSTANT sramwidth : INTEGER := 32; |
|
208 | 213 | CONSTANT sramdepth : INTEGER := 19; |
|
209 | 214 | CONSTANT sramfile : STRING := "prom.srec"; |
|
210 | 215 | SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0); |
|
211 | 216 | ----------------------------------------------------------------------------- |
|
212 | 217 | |
|
213 | 218 | BEGIN -- beh |
|
214 | 219 | |
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215 | 220 | LFR_EQM_1 : LFR_EQM |
|
216 | 221 | GENERIC MAP ( |
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217 | 222 | Mem_use => use_RAM, |
|
218 |
USE_BOOTLOADER => 0 |
|
|
223 | USE_BOOTLOADER => 0, | |
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224 | USE_ADCDRIVER => 0, | |
|
225 | tech => apa3e, | |
|
226 | tech_leon => inferred) | |
|
219 | 227 | PORT MAP ( |
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220 | 228 | clk50MHz => clk50MHz, --IN --ok |
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221 | 229 | clk49_152MHz => clk49_152MHz, --in --ok |
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222 | 230 | reset => reset, --IN --ok |
|
223 | 231 | |
|
224 | 232 | TAG1 => TAG1, --in |
|
225 | 233 | TAG3 => TAG3, --out |
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226 | 234 | TAG2 => TAG2, --IN --ok |
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227 | 235 | TAG4 => TAG4, --out --ok |
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228 | 236 | |
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229 | 237 | address => address, --out |
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230 | 238 | data => data, --inout |
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231 | 239 | nSRAM_MBE => nSRAM_MBE, --inout |
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232 | 240 | nSRAM_E1 => nSRAM_E1, --out |
|
233 | 241 | nSRAM_E2 => nSRAM_E2, --out |
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234 | 242 | nSRAM_W => nSRAM_W, --out |
|
235 | 243 | nSRAM_G => nSRAM_G, --out |
|
236 | 244 | nSRAM_BUSY => nSRAM_BUSY, --in |
|
237 | 245 | |
|
238 | 246 | spw1_en => spw1_en, --out --ok |
|
239 | 247 | spw1_din => spw1_din, --in --ok |
|
240 | 248 | spw1_sin => spw1_sin, --in --ok |
|
241 | 249 | spw1_dout => spw1_dout, --out --ok |
|
242 | 250 | spw1_sout => spw1_sout, --out --ok |
|
243 | 251 | |
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244 | 252 | spw2_en => spw2_en, --out --ok |
|
245 | 253 | spw2_din => spw2_din, --in --ok |
|
246 | 254 | spw2_sin => spw2_sin, --in --ok |
|
247 | 255 | spw2_dout => spw2_dout, --out --ok |
|
248 | 256 | spw2_sout => spw2_sout, --out --ok |
|
249 | 257 | |
|
250 | 258 | bias_fail_sw => bias_fail_sw, --OUT --ok |
|
251 | 259 | |
|
252 | 260 | ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok |
|
253 | 261 | ADC_smpclk => ADC_smpclk, --out --ok |
|
254 | 262 | ADC_data => ADC_data, --IN --ok |
|
255 | 263 | |
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256 | 264 | DAC_SDO => DAC_SDO, --out --ok |
|
257 | 265 | DAC_SCK => DAC_SCK, --out --ok |
|
258 | 266 | DAC_SYNC => DAC_SYNC, --out --ok |
|
259 | 267 | DAC_CAL_EN => DAC_CAL_EN, --out --ok |
|
260 | 268 | |
|
261 | 269 | HK_smpclk => HK_smpclk, --out --ok |
|
262 | 270 | ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok |
|
263 | 271 | HK_SEL => HK_SEL, --out --ok |
|
264 | 272 | TAG8 => TAG8); --out --ok |
|
265 | 273 | |
|
266 | 274 | |
|
267 | 275 | ----------------------------------------------------------------------------- |
|
268 | 276 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
269 | 277 | clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz |
|
270 | 278 | ----------------------------------------------------------------------------- |
|
271 | 279 | |
|
272 | 280 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
|
273 | 281 | TestModule_RHF1401_1 : TestModule_RHF1401 |
|
274 | 282 | GENERIC MAP ( |
|
275 | 283 | freq => 24*(I+1), |
|
276 | 284 | amplitude => 8000/(I+1), |
|
277 | 285 | impulsion => 0) |
|
278 | 286 | PORT MAP ( |
|
279 | 287 | ADC_smpclk => ADC_smpclk, |
|
280 | 288 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
281 | 289 | ADC_data => ADC_data); |
|
282 | 290 | END GENERATE MODULE_RHF1401; |
|
283 | 291 | |
|
284 | 292 | ----------------------------------------------------------------------------- |
|
285 | 293 | PROCESS (clk50MHz, reset) |
|
286 | 294 | BEGIN -- PROCESS |
|
287 | 295 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
288 | 296 | nSRAM_BUSY <= '1'; |
|
289 | 297 | counter_scrub_period <= 0; |
|
290 | 298 | ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge |
|
291 | 299 | IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN |
|
292 | 300 | counter_scrub_period <= 0; |
|
293 | 301 | ELSE |
|
294 | 302 | counter_scrub_period <= counter_scrub_period + 1; |
|
295 | 303 | END IF; |
|
296 | 304 | |
|
297 | 305 | IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN |
|
298 | 306 | nSRAM_BUSY <= '1'; |
|
299 | 307 | ELSE |
|
300 | 308 | nSRAM_BUSY <= '0'; |
|
301 | 309 | END IF; |
|
302 | 310 | END IF; |
|
303 | 311 | END PROCESS; |
|
304 | 312 | |
|
305 | 313 | ----------------------------------------------------------------------------- |
|
306 | 314 | -- TB |
|
307 | 315 | ----------------------------------------------------------------------------- |
|
308 | 316 | TAG1 <= TXD1; |
|
309 | 317 | RXD1 <= TAG3; |
|
310 | 318 | |
|
311 | 319 | PROCESS |
|
312 | 320 | CONSTANT txp : TIME := 320 ns; |
|
313 | 321 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | 322 | BEGIN -- PROCESS |
|
315 | 323 | TXD1 <= '1'; |
|
316 | 324 | reset <= '0'; |
|
317 | 325 | WAIT FOR 500 ns; |
|
318 | 326 | reset <= '1'; |
|
319 |
WAIT FOR 100 |
|
|
327 | WAIT FOR 100 us; | |
|
320 | 328 | message_simu <= "0 - UART init "; |
|
321 | 329 | UART_INIT(TXD1, txp); |
|
322 | 330 | |
|
323 | 331 | --------------------------------------------------------------------------- |
|
324 | 332 | -- LAUNCH leon 3 software |
|
325 | 333 | --------------------------------------------------------------------------- |
|
326 | 334 | message_simu <= "2- GO Leon3...."; |
|
327 | ||
|
335 | ||
|
328 | 336 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- |
|
329 | 337 | --Force a debug break |
|
330 | 338 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); |
|
331 | 339 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20); |
|
332 | 340 | --Clear time tag counter |
|
333 | 341 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8); |
|
334 | 342 | --Clear ASR registers |
|
335 | 343 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
|
336 | 344 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000"); |
|
337 | 345 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000"); |
|
338 | 346 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024); |
|
339 | 347 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
|
340 | 348 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
|
341 | 349 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
342 | 350 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
343 | 351 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000"); |
|
344 | 352 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000"); |
|
345 | 353 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000"); |
|
346 | 354 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000"); |
|
347 | 355 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48); |
|
348 | 356 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C); |
|
349 | 357 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
|
350 | 358 | |
|
351 | 359 | IF USE_ESA_MEMCTRL = 1 THEN |
|
352 | 360 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS); |
|
353 | 361 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60"); |
|
354 | 362 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000"); |
|
355 | 363 | END IF; |
|
356 | 364 | |
|
357 | 365 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
|
358 | 366 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
|
359 | 367 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
360 | 368 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
361 | 369 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24); |
|
362 | 370 | |
|
363 | 371 | --memSet(DSUBASEADDRESS+0x300000,0,1567); |
|
364 | 372 | |
|
365 | 373 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000); |
|
366 | 374 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0"); |
|
367 | 375 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002"); |
|
368 | 376 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000"); |
|
369 | 377 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000"); |
|
370 | 378 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004"); |
|
371 | 379 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000"); |
|
372 | 380 | |
|
373 | 381 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020); |
|
374 | 382 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000"); |
|
375 | 383 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000"); |
|
376 | 384 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000"); |
|
377 | 385 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000"); |
|
378 | 386 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000"); |
|
379 | 387 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0"); |
|
380 | 388 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000"); |
|
381 | 389 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000"); |
|
382 | 390 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000"); |
|
383 | 391 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000"); |
|
384 | 392 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000"); |
|
385 | 393 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000"); |
|
386 | 394 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000"); |
|
387 | 395 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000"); |
|
388 | 396 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000"); |
|
389 | 397 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000"); |
|
390 | 398 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000"); |
|
391 | 399 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000"); |
|
392 | 400 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000"); |
|
393 | 401 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000"); |
|
394 | 402 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000"); |
|
395 | 403 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000"); |
|
396 | 404 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000"); |
|
397 | 405 | |
|
398 | 406 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS); |
|
399 | 407 | |
|
400 | 408 | --//Disable interrupts |
|
401 | 409 | --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0); |
|
402 | 410 | --if(APBIRQCTRLRBASEADD == (unsigned int)-1) |
|
403 | 411 | -- return false; |
|
404 | 412 | --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040); |
|
405 | 413 | --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080); |
|
406 | 414 | --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD); |
|
407 | 415 | |
|
408 | 416 | -- //Set up timer |
|
409 | 417 | --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0); |
|
410 | 418 | --if(APBTIMERBASEADD == (unsigned int)-1) |
|
411 | 419 | -- return false; |
|
412 | 420 | --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014); |
|
413 | 421 | --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04); |
|
414 | 422 | --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018); |
|
415 | 423 | |
|
416 | 424 | |
|
417 | 425 | --------------------------------------------------------------------------- |
|
418 | 426 | --bool dsu3plugin::setCacheEnable(bool enabled) |
|
419 | 427 | --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0); |
|
420 | 428 | --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000; |
|
421 | 429 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024); |
|
422 | 430 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000); |
|
423 | 431 | data_read <= data_read_v; |
|
424 | 432 | --if(enabled){ |
|
425 | 433 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000); |
|
426 | 434 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000); |
|
427 | 435 | --}else{ |
|
428 | 436 | --WriteRegs(uIntlist()<<((!0x0001000F)®),DSUBASEADDRESS+0x700000); |
|
429 | 437 | --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000); |
|
430 | 438 | --} |
|
431 | 439 | |
|
432 | 440 | |
|
433 | 441 | -- void dsu3plugin::run() --------------------------------------------------------------------------------------------------------------------------------------- |
|
434 | 442 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020); |
|
435 | 443 | |
|
436 | 444 | --------------------------------------------------------------------------- |
|
437 | 445 | --message_simu <= "1 - UART test "; |
|
438 | 446 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF"); |
|
439 | 447 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A"); |
|
440 | 448 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B"); |
|
441 | 449 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v); |
|
442 | 450 | --data_read <= data_read_v; |
|
443 | 451 | --data_message <= "GPIO_data_write"; |
|
444 | 452 | |
|
445 | 453 | -- UNSET the LFR reset |
|
446 | 454 | message_simu <= "2 - LFR UNRESET"; |
|
447 | 455 | UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT); |
|
448 | 456 | -- |
|
449 | 457 | message_simu <= "3 - LFR CONFIG "; |
|
450 | 458 | LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR, |
|
451 | 459 | ADDR_BUFFER_MS_F0_0, |
|
452 | 460 | ADDR_BUFFER_MS_F0_1, |
|
453 | 461 | ADDR_BUFFER_MS_F1_0, |
|
454 | 462 | ADDR_BUFFER_MS_F1_1, |
|
455 | 463 | ADDR_BUFFER_MS_F2_0, |
|
456 | 464 | ADDR_BUFFER_MS_F2_1); |
|
457 | 465 | |
|
458 | 466 | |
|
459 | 467 | LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp, |
|
460 | 468 | LFR_MODE_SBM1, |
|
461 | 469 | X"7FFFFFFF", -- START DATE |
|
462 | 470 | |
|
463 | 471 | "00000", --DATA_SHAPING ( 4 DOWNTO 0) |
|
464 | 472 | X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0) |
|
465 | 473 | X"0001280A", --DELTA_F0 (31 DOWNTO 0) |
|
466 | 474 | X"00000007", --DELTA_F0_2 (31 DOWNTO 0) |
|
467 | 475 | X"0001283F", --DELTA_F1 (31 DOWNTO 0) |
|
468 | 476 | X"000127FF", --DELTA_F2 (31 DOWNTO 0) |
|
469 | 477 | |
|
470 | 478 | ADDR_BASE_LFR, |
|
471 | 479 | ADDR_BUFFER_WFP_F0_0, |
|
472 | 480 | ADDR_BUFFER_WFP_F0_1, |
|
473 | 481 | ADDR_BUFFER_WFP_F1_0, |
|
474 | 482 | ADDR_BUFFER_WFP_F1_1, |
|
475 | 483 | ADDR_BUFFER_WFP_F2_0, |
|
476 | 484 | ADDR_BUFFER_WFP_F2_1, |
|
477 | 485 | ADDR_BUFFER_WFP_F3_0, |
|
478 | 486 | ADDR_BUFFER_WFP_F3_1); |
|
479 | 487 | |
|
480 | 488 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
481 | 489 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
482 | 490 | |
|
483 | 491 | |
|
484 | 492 | --------------------------------------------------------------------------- |
|
485 | 493 | -- CONFIG LFR 2 |
|
486 | 494 | --------------------------------------------------------------------------- |
|
487 | 495 | --message_simu <= "3 - LFR2 CONFIG"; |
|
488 | 496 | --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2, |
|
489 | 497 | -- X"40000000", |
|
490 | 498 | -- X"40001000", |
|
491 | 499 | -- X"40002000", |
|
492 | 500 | -- X"40003000", |
|
493 | 501 | -- X"40004000", |
|
494 | 502 | -- X"40005000"); |
|
495 | 503 | |
|
496 | 504 | |
|
497 | 505 | --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, |
|
498 | 506 | -- LFR_MODE_SBM1, |
|
499 | 507 | -- X"7FFFFFFF", -- START DATE |
|
500 | 508 | |
|
501 | 509 | -- "00000",--DATA_SHAPING ( 4 DOWNTO 0) |
|
502 | 510 | -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) |
|
503 | 511 | -- X"0001280A",--DELTA_F0 (31 DOWNTO 0) |
|
504 | 512 | -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0) |
|
505 | 513 | -- X"0001283F",--DELTA_F1 (31 DOWNTO 0) |
|
506 | 514 | -- X"000127FF",--DELTA_F2 (31 DOWNTO 0) |
|
507 | 515 | |
|
508 | 516 | -- ADDR_BASE_LFR_2, |
|
509 | 517 | -- X"40006000", |
|
510 | 518 | -- X"40007000", |
|
511 | 519 | -- X"40008000", |
|
512 | 520 | -- X"40009000", |
|
513 | 521 | -- X"4000A000", |
|
514 | 522 | -- X"4000B000", |
|
515 | 523 | -- X"4000C000", |
|
516 | 524 | -- X"4000D000"); |
|
517 | 525 | |
|
518 | 526 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
519 | 527 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
520 | 528 | |
|
521 | 529 | --------------------------------------------------------------------------- |
|
522 | 530 | --------------------------------------------------------------------------- |
|
523 | 531 | |
|
524 | 532 | |
|
525 | 533 | message_simu <= "4 - GO GO GO !!"; |
|
534 | data_message <= "---------------"; | |
|
526 | 535 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); |
|
527 |
|
|
|
536 | -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); | |
|
528 | 537 | |
|
538 | ||
|
539 | data_read_v := (OTHERS => '1'); | |
|
529 | 540 | READ_STATUS : LOOP |
|
541 | data_message <= "---------------"; | |
|
530 | 542 | WAIT FOR 2 ms; |
|
531 |
data_message <= "READ_ |
|
|
532 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |
|
533 | data_read <= data_read_v; | |
|
543 | data_message <= "READ_STATUS_SM_"; | |
|
544 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |
|
545 | --data_message <= "--------------r"; | |
|
546 | --data_read <= data_read_v; | |
|
534 | 547 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
535 | 548 | |
|
536 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |
|
537 | data_read <= data_read_v; | |
|
549 | data_message <= "READ_STATUS_WF_"; | |
|
550 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |
|
551 | --data_message <= "--------------r"; | |
|
552 | --data_read <= data_read_v; | |
|
538 | 553 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
539 | 554 | END LOOP READ_STATUS; |
|
540 | 555 | |
|
541 | 556 | WAIT; |
|
542 | 557 | END PROCESS; |
|
543 | 558 | |
|
544 | 559 | |
|
545 | 560 | ----------------------------------------------------------------------------- |
|
546 | 561 | PROCESS (nSRAM_W, reset) |
|
547 | 562 | BEGIN -- PROCESS |
|
548 | 563 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
549 | 564 | data_pre_f0 <= X"00020001"; |
|
550 | 565 | data_pre_f1 <= X"00020001"; |
|
551 | 566 | data_pre_f2 <= X"00020001"; |
|
552 | 567 | |
|
553 | 568 | addr_pre_f0 <= (OTHERS => '0'); |
|
554 | 569 | addr_pre_f1 <= (OTHERS => '0'); |
|
555 | 570 | addr_pre_f2 <= (OTHERS => '0'); |
|
556 | 571 | |
|
557 | 572 | error_wfp <= "000"; |
|
558 | 573 | error_wfp_addr <= "000"; |
|
559 | 574 | |
|
560 | 575 | sample_counter <= (0,0,0); |
|
561 | 576 | |
|
562 | 577 | ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge |
|
563 | 578 | error_wfp <= "000"; |
|
564 | 579 | error_wfp_addr <= "000"; |
|
565 | 580 | ------------------------------------------------------------------------- |
|
566 | 581 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR |
|
567 | 582 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN |
|
568 | 583 | |
|
569 | 584 | addr_pre_f0 <= address(13 DOWNTO 0); |
|
570 | 585 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN |
|
571 | 586 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
572 | 587 | error_wfp_addr(0) <= '1'; |
|
573 | 588 | END IF; |
|
574 | 589 | END IF; |
|
575 | 590 | |
|
576 | 591 | data_pre_f0 <= data; |
|
577 | 592 | CASE data_pre_f0 IS |
|
578 | 593 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF; |
|
579 | 594 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF; |
|
580 | 595 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF; |
|
581 | 596 | WHEN OTHERS => error_wfp(0) <= '1'; |
|
582 | 597 | END CASE; |
|
583 | 598 | |
|
584 | 599 | |
|
585 | 600 | END IF; |
|
586 | 601 | ------------------------------------------------------------------------- |
|
587 | 602 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR |
|
588 | 603 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN |
|
589 | 604 | |
|
590 | 605 | addr_pre_f1 <= address(13 DOWNTO 0); |
|
591 | 606 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN |
|
592 | 607 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
593 | 608 | error_wfp_addr(1) <= '1'; |
|
594 | 609 | END IF; |
|
595 | 610 | END IF; |
|
596 | 611 | |
|
597 | 612 | data_pre_f1 <= data; |
|
598 | 613 | CASE data_pre_f1 IS |
|
599 | 614 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF; |
|
600 | 615 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF; |
|
601 | 616 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF; |
|
602 | 617 | WHEN OTHERS => error_wfp(1) <= '1'; |
|
603 | 618 | END CASE; |
|
604 | 619 | |
|
605 | 620 | sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16); |
|
606 | 621 | sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0); |
|
607 | 622 | sample_counter(1) <= (sample_counter(1) + 1) MOD 3; |
|
608 | 623 | |
|
609 | 624 | END IF; |
|
610 | 625 | ------------------------------------------------------------------------- |
|
611 | 626 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR |
|
612 | 627 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN |
|
613 | 628 | |
|
614 | 629 | addr_pre_f2 <= address(13 DOWNTO 0); |
|
615 | 630 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN |
|
616 | 631 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
617 | 632 | error_wfp_addr(2) <= '1'; |
|
618 | 633 | END IF; |
|
619 | 634 | END IF; |
|
620 | 635 | |
|
621 | 636 | data_pre_f2 <= data; |
|
622 | 637 | CASE data_pre_f2 IS |
|
623 | 638 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF; |
|
624 | 639 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF; |
|
625 | 640 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF; |
|
626 | 641 | WHEN OTHERS => error_wfp(2) <= '1'; |
|
627 | 642 | END CASE; |
|
628 | 643 | |
|
629 | 644 | sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16); |
|
630 | 645 | sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0); |
|
631 | 646 | sample_counter(2) <= (sample_counter(2) + 1) MOD 3; |
|
632 | 647 | |
|
633 | 648 | END IF; |
|
634 | 649 | END IF; |
|
635 | 650 | END PROCESS; |
|
636 | 651 | ----------------------------------------------------------------------------- |
|
637 | 652 | ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; |
|
638 | 653 | |
|
639 | 654 | sbanks : FOR k IN 0 TO srambanks-1 GENERATE |
|
640 | 655 | sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE |
|
641 | 656 | sr0 : sram |
|
642 | 657 | GENERIC MAP ( |
|
643 | 658 | index => i, |
|
644 | 659 | abits => sramdepth, |
|
645 | 660 | fname => sramfile) |
|
646 | 661 | PORT MAP ( |
|
647 | 662 | address, |
|
648 | 663 | data(31-i*8 DOWNTO 24-i*8), |
|
649 | 664 | ramsn(k), |
|
650 | 665 | nSRAM_W, |
|
651 | 666 | nSRAM_G |
|
652 | 667 | ); |
|
653 | 668 | END GENERATE; |
|
654 | 669 | END GENERATE; |
|
655 | 670 | |
|
656 | 671 | END beh; |
|
657 | 672 |
@@ -1,199 +1,226 | |||
|
1 | 1 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
2 | 2 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
3 | 3 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
4 | 4 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
5 | 5 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd |
|
6 | 6 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd |
|
7 | 7 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd |
|
8 | 8 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd |
|
9 | 9 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd |
|
10 | 10 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd |
|
11 | 11 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd |
|
12 | 12 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
|
13 | 13 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd |
|
14 | 14 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd |
|
15 | 15 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd |
|
16 | 16 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd |
|
17 | 17 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd |
|
18 | 18 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd |
|
19 | 19 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd |
|
20 | 20 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd |
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21 | 21 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd |
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22 | 22 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd |
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23 | 23 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd |
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24 | 24 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd |
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25 | 25 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd |
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26 | 26 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd |
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27 | 27 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd |
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28 | 28 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd |
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29 | 29 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd |
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30 | 30 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd |
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31 | 31 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd |
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32 | 32 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd |
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33 | 33 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd |
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34 | 34 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd |
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35 | 35 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd |
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36 | 36 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd |
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37 | 37 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd |
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38 | 38 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd |
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39 | 39 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd |
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40 | 40 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd |
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41 | 41 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd |
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42 | 42 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd |
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43 | 43 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd |
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44 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd | |
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44 | 45 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd |
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45 | 46 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd |
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46 | 47 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd |
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47 | 48 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd |
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48 | 49 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
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49 | 50 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd |
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50 | 51 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd |
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51 | 52 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
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52 | 53 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd |
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53 | 54 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd |
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54 | 55 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
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55 | 56 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd |
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56 | 57 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd |
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57 | 58 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd |
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58 | 59 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd |
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59 | 60 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd |
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60 | 61 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd |
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61 | 62 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd |
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62 | 63 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd |
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63 | 64 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd |
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64 | 65 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd |
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65 | 66 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd |
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66 | 67 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd |
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67 | 68 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd |
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68 | 69 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd |
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69 | 70 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd |
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70 | 71 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd |
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71 | 72 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd |
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72 | 73 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd |
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73 | 74 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd |
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74 | 75 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd |
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75 | 76 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd |
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76 | 77 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd |
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77 | 78 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
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78 | 79 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
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79 | 80 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd |
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80 | 81 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd |
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81 | 82 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd |
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82 | 83 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd |
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83 | 84 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd |
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84 | 85 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd |
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85 | 86 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd |
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86 | 87 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd |
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87 | 88 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd |
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88 | 89 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
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89 | 90 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd |
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90 | 91 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd |
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91 | 92 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd |
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92 | 93 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd |
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93 | 94 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd |
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94 | 95 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd |
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95 | 96 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd |
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96 | 97 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd |
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97 | 98 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd |
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98 | 99 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd |
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99 | 100 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd |
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100 | 101 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd |
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101 | 102 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd |
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102 | 103 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd |
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103 | 104 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd |
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104 | 105 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd |
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105 | 106 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd |
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106 | 107 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd |
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107 | 108 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd |
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108 | 109 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd |
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109 | 110 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd |
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110 | 111 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd |
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111 | 112 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd |
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112 | 113 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd |
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113 | 114 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd |
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114 | 115 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd |
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115 | 116 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd |
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116 | 117 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
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117 | 118 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
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118 | 119 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd |
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119 | 120 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd |
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120 | 121 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd |
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121 | 122 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
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122 | 123 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd |
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123 | 124 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd |
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124 | 125 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd |
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125 | 126 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd |
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126 | 127 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd |
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127 | 128 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd |
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128 | 129 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd |
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129 | 130 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd |
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130 | 131 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd |
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131 | 132 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd |
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132 | 133 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
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133 | 134 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
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134 | 135 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd |
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135 | 136 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd |
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136 | 137 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
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137 | 138 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
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138 | 139 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
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139 | 140 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd |
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140 | 141 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd |
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141 | 142 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd |
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142 | 143 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd |
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143 | 144 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd |
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144 | 145 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd |
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145 | 146 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd |
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146 | 147 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd |
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147 | 148 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd |
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148 | 149 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd |
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149 | 150 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd |
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150 | 151 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd |
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151 | 152 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd |
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152 | 153 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd |
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153 | 154 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
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154 | 155 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd |
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155 | 156 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd |
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156 | 157 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd |
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157 | 158 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd |
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158 | 159 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd |
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159 | 160 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
160 | 161 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd |
|
161 | 162 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd |
|
162 | 163 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd |
|
163 | 164 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd |
|
164 | 165 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd |
|
165 | 166 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd |
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166 | 167 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
167 | 168 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd |
|
168 | 169 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd |
|
169 | 170 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd |
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170 | 171 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd |
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171 | 172 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd |
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172 | 173 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
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173 | 174 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
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174 | 175 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd |
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175 | 176 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd |
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176 | 177 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd |
|
177 | 178 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd |
|
178 | 179 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd |
|
179 | 180 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd |
|
180 | 181 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd |
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181 | 182 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd |
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182 | 183 | vcom -quiet -93 -work work LFR-EQM.vhd |
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183 | 184 | vcom -quiet -93 -work work TB.vhd |
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184 | 185 | |
|
185 | 186 | vsim work.tb |
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186 | 187 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0 |
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187 | 188 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 |
|
188 | 189 | #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 |
|
189 | 190 | |
|
190 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000 |
|
|
191 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 00 |
|
|
192 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 0 |
|
|
193 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data |
|
|
191 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
|
192 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
|
193 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
|
194 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
|
195 | ||
|
196 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
|
197 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
|
198 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
|
199 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |
|
200 | ||
|
201 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |
|
202 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |
|
203 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |
|
204 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd | |
|
205 | ||
|
206 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd | |
|
207 | ||
|
208 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
|
209 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
|
210 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
|
211 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
|
212 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
|
213 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
|
214 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |
|
215 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |
|
216 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9 | |
|
217 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9 | |
|
218 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9 | |
|
219 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9 | |
|
220 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9 | |
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194 | 221 | |
|
195 | 222 | log -r *; |
|
196 | 223 | do wave.do ; |
|
197 | 224 | run -all |
|
198 | 225 | |
|
199 | 226 |
@@ -1,116 +1,116 | |||
|
1 | 1 | onerror {resume} |
|
2 | 2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc |
|
3 | 3 | quietly WaveActivateNextPane {} 0 |
|
4 | 4 | add wave -noupdate /tb/data_message |
|
5 | 5 | add wave -noupdate /tb/message_simu |
|
6 | 6 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 |
|
7 | 7 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 |
|
8 | 8 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G |
|
9 | 9 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W |
|
10 | 10 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data |
|
11 | 11 | add wave -noupdate -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc |
|
12 | 12 | add wave -noupdate -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address |
|
13 | 13 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY |
|
14 | 14 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE |
|
15 | 15 | add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data |
|
16 | 16 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk |
|
17 | 17 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH |
|
18 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
|
19 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
|
20 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
|
21 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
|
22 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
|
23 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
|
24 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
|
25 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
|
26 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
|
27 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
|
18 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
|
19 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
|
20 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
|
21 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
|
22 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
|
23 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
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24 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
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25 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
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26 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
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27 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
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28 | 28 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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29 | 29 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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30 | 30 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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31 | 31 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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32 | 32 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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33 | 33 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter |
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34 | 34 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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35 | 35 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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36 | 36 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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37 | 37 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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38 | 38 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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39 | 39 | add wave -noupdate -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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40 | 40 | add wave -noupdate -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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41 | 41 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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42 | 42 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk |
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43 | 43 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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44 | 44 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid |
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45 | 45 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex |
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46 | 46 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn |
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47 | 47 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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48 | 48 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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49 | 49 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid |
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50 | 50 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version |
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51 | 51 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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52 | 52 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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53 | 53 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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54 | 54 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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55 | 55 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter |
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56 | 56 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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57 | 57 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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58 | 58 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window |
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59 | 59 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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60 | 60 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp |
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61 | 61 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp |
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62 | add wave -noupdate -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
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63 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f1 | |
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64 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f2 | |
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65 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
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66 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
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67 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
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62 | add wave -noupdate -expand -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
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63 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f1 | |
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64 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f2 | |
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65 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
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66 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
|
67 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
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68 | 68 | add wave -noupdate /tb/error_wfp |
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69 | 69 | add wave -noupdate /tb/error_wfp_addr |
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70 | 70 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a |
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71 | 71 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 |
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72 | 72 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe |
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73 | 73 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we |
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74 | 74 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a |
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75 | 75 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 |
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76 | 76 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe |
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77 | 77 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we |
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78 | 78 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi |
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79 | 79 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo |
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80 | 80 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi |
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81 | 81 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso |
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82 | 82 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbmi |
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83 | 83 | add wave -noupdate -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo |
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84 | 84 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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85 | 85 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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86 | 86 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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87 | 87 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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88 | 88 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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89 | 89 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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90 | 90 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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91 | 91 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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92 | 92 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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93 | 93 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window |
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94 | 94 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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95 | 95 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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96 | 96 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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97 |
add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}} |
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98 |
add wave -noupdate |
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97 | add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-height 15 -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} /tb/sample(2)(5) {-height 15 -radix decimal} /tb/sample(2)(4) {-height 15 -radix decimal} /tb/sample(2)(3) {-height 15 -radix decimal} /tb/sample(2)(2) {-height 15 -radix decimal} /tb/sample(2)(1) {-height 15 -radix decimal} /tb/sample(2)(0) {-height 15 -radix decimal} /tb/sample(1) {-height 15 -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -expand} /tb/sample(1)(5) {-format Analog-Step -height 74 -min -4.0 -radix decimal} /tb/sample(1)(4) {-format Analog-Step -height 74 -min -8.0 -radix decimal} /tb/sample(1)(3) {-format Analog-Step -height 74 -max 70.0 -radix decimal} /tb/sample(1)(2) {-format Analog-Step -height 74 -max 512.0 -radix decimal} /tb/sample(1)(1) {-format Analog-Step -height 74 -max 256.0 -radix decimal} /tb/sample(1)(0) {-format Analog-Step -height 74 -max 16.0 -radix decimal} /tb/sample(0) {-height 15 -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-height 15 -radix decimal} /tb/sample(0)(4) {-height 15 -radix decimal} /tb/sample(0)(3) {-height 15 -radix decimal} /tb/sample(0)(2) {-height 15 -radix decimal} /tb/sample(0)(1) {-height 15 -radix decimal} /tb/sample(0)(0) {-height 15 -radix decimal}} /tb/sample | |
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98 | add wave -noupdate /tb/sample_counter | |
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99 | 99 | TreeUpdate [SetDefaultTree] |
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100 |
WaveRestoreCursors {{Cursor 1} { |
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101 |
quietly wave cursor active |
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100 | WaveRestoreCursors {{Cursor 1} {14590425667 ps} 0} {{Cursor 2} {5525050896 ps} 0} {{Cursor 3} {24728625854 ps} 0} | |
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101 | quietly wave cursor active 1 | |
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102 | 102 | configure wave -namecolwidth 517 |
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103 | 103 | configure wave -valuecolwidth 347 |
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104 | 104 | configure wave -justifyvalue left |
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105 | 105 | configure wave -signalnamewidth 0 |
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106 | 106 | configure wave -snapdistance 10 |
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107 | 107 | configure wave -datasetprefix 0 |
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108 | 108 | configure wave -rowmargin 4 |
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109 | 109 | configure wave -childrowmargin 2 |
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110 | 110 | configure wave -gridoffset 0 |
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111 | 111 | configure wave -gridperiod 1 |
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112 | 112 | configure wave -griddelta 40 |
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113 | 113 | configure wave -timeline 0 |
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114 | 114 | configure wave -timelineunits ns |
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115 | 115 | update |
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116 |
WaveRestoreZoom {0 ps} { |
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116 | WaveRestoreZoom {0 ps} {40323664500 ps} |
@@ -1,407 +1,420 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Alexis Jeandet |
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20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
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21 | 21 | ---------------------------------------------------------------------------- |
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22 | 22 | --UPDATE |
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23 | 23 | ------------------------------------------------------------------------------- |
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24 | 24 | -- 14-03-2013 - Jean-christophe Pellion |
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25 | 25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) |
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26 | 26 | ------------------------------------------------------------------------------- |
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27 | 27 | |
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28 | 28 | LIBRARY ieee; |
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29 | 29 | USE ieee.std_logic_1164.ALL; |
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30 | 30 | USE IEEE.NUMERIC_STD.ALL; |
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31 | 31 | |
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32 | 32 | |
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33 | 33 | |
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34 | 34 | PACKAGE general_purpose IS |
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35 | 35 | |
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36 | 36 | COMPONENT general_counter |
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37 | 37 | GENERIC ( |
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38 | 38 | CYCLIC : STD_LOGIC; |
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39 | 39 | NB_BITS_COUNTER : INTEGER; |
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40 | 40 | RST_VALUE : INTEGER); |
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41 | 41 | PORT ( |
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42 | 42 | clk : IN STD_LOGIC; |
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43 | 43 | rstn : IN STD_LOGIC; |
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44 | 44 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
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45 | 45 | set : IN STD_LOGIC; |
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46 | 46 | set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
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47 | 47 | add1 : IN STD_LOGIC; |
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48 | 48 | counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)); |
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49 | 49 | END COMPONENT; |
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50 | 50 | |
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51 | 51 | COMPONENT Clk_divider IS |
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52 | 52 | GENERIC(OSC_freqHz : INTEGER := 50000000; |
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53 | 53 | TargetFreq_Hz : INTEGER := 50000); |
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54 |
PORT (clk |
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55 |
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56 |
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54 | PORT (clk : IN STD_LOGIC; | |
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55 | reset : IN STD_LOGIC; | |
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56 | clk_divided : OUT STD_LOGIC); | |
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57 | 57 | END COMPONENT; |
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58 | 58 | |
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59 | 59 | |
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60 | 60 | COMPONENT Clk_divider2 IS |
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61 | generic(N : integer := 16); | |
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62 | port( | |
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63 |
clk_in : |
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64 | clk_out : out std_logic); | |
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61 | GENERIC(N : INTEGER := 16); | |
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62 | PORT( | |
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63 | clk_in : IN STD_LOGIC; | |
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64 | clk_out : OUT STD_LOGIC); | |
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65 | 65 | END COMPONENT; |
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66 | 66 | |
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67 | 67 | COMPONENT Adder IS |
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68 | 68 | GENERIC( |
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69 | 69 | Input_SZ_A : INTEGER := 16; |
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70 | 70 | Input_SZ_B : INTEGER := 16 |
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71 | 71 | |
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72 | 72 | ); |
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73 | 73 | PORT( |
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74 | 74 | clk : IN STD_LOGIC; |
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75 | 75 | reset : IN STD_LOGIC; |
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76 | 76 | clr : IN STD_LOGIC; |
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77 | load : IN STD_LOGIC; | |
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77 | load : IN STD_LOGIC; | |
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78 | 78 | add : IN STD_LOGIC; |
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79 | 79 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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80 | 80 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
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81 | 81 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) |
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82 | 82 | ); |
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83 | 83 | END COMPONENT; |
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84 | 84 | |
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85 |
COMPONENT Adder_V0 |
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86 | generic( | |
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87 |
Input_SZ_A |
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88 |
Input_SZ_B |
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85 | COMPONENT Adder_V0 IS | |
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86 | GENERIC( | |
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87 | Input_SZ_A : INTEGER := 16; | |
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88 | Input_SZ_B : INTEGER := 16 | |
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89 | 89 | |
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90 | ); | |
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91 | port( | |
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92 | clk : in std_logic; | |
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93 | reset : in std_logic; | |
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94 | clr : in std_logic; | |
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95 | add : in std_logic; | |
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96 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
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97 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
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98 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) | |
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99 | ); | |
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100 |
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90 | ); | |
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91 | PORT( | |
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92 | clk : IN STD_LOGIC; | |
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93 | reset : IN STD_LOGIC; | |
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94 | clr : IN STD_LOGIC; | |
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95 | add : IN STD_LOGIC; | |
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96 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
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97 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
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98 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |
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99 | ); | |
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100 | END COMPONENT; | |
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101 | 101 | |
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102 | 102 | COMPONENT ADDRcntr IS |
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103 | 103 | PORT( |
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104 | 104 | clk : IN STD_LOGIC; |
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105 | 105 | reset : IN STD_LOGIC; |
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106 | 106 | count : IN STD_LOGIC; |
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107 | 107 | clr : IN STD_LOGIC; |
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108 | 108 | Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
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109 | 109 | ); |
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110 | 110 | END COMPONENT; |
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111 | 111 | |
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112 | 112 | COMPONENT ALU IS |
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113 | 113 | GENERIC( |
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114 | 114 | Arith_en : INTEGER := 1; |
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115 | 115 | Logic_en : INTEGER := 1; |
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116 | 116 | Input_SZ_1 : INTEGER := 16; |
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117 | 117 | Input_SZ_2 : INTEGER := 9; |
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118 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
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118 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
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119 | 119 | |
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120 | 120 | ); |
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121 | 121 | PORT( |
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122 | 122 | clk : IN STD_LOGIC; |
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123 | 123 | reset : IN STD_LOGIC; |
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124 |
ctrl : IN STD_LOGIC_VECTOR(2 |
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125 |
comp : IN STD_LOGIC_VECTOR(1 |
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124 | ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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125 | comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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126 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
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127 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |
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128 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |
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129 | ); | |
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130 | END COMPONENT; | |
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131 | ||
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132 | COMPONENT ALU_V0 IS | |
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133 | GENERIC( | |
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134 | Arith_en : INTEGER := 1; | |
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135 | Logic_en : INTEGER := 1; | |
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136 | Input_SZ_1 : INTEGER := 16; | |
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137 | Input_SZ_2 : INTEGER := 9 | |
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138 | ||
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139 | ); | |
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140 | PORT( | |
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141 | clk : IN STD_LOGIC; | |
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142 | reset : IN STD_LOGIC; | |
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143 | ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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126 | 144 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
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127 | 145 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); |
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128 | 146 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) |
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129 | 147 | ); |
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130 | 148 | END COMPONENT; |
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131 | 149 | |
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132 |
COMPONENT |
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133 | GENERIC( | |
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134 |
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135 |
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136 | Input_SZ_1 : INTEGER := 16; | |
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137 | Input_SZ_2 : INTEGER := 9 | |
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150 | COMPONENT MAC_V0 IS | |
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151 | GENERIC( | |
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152 | Input_SZ_A : INTEGER := 8; | |
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153 | Input_SZ_B : INTEGER := 8 | |
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138 | 154 | |
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139 | ); | |
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140 | PORT( | |
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141 | clk : IN STD_LOGIC; | |
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142 | reset : IN STD_LOGIC; | |
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143 |
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144 |
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145 |
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146 |
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147 | ); | |
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148 | END COMPONENT; | |
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149 | ||
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150 | COMPONENT MAC_V0 is | |
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151 | generic( | |
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152 | Input_SZ_A : integer := 8; | |
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153 | Input_SZ_B : integer := 8 | |
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154 | ||
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155 | ); | |
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156 | port( | |
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157 | clk : in std_logic; | |
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158 | reset : in std_logic; | |
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159 | clr_MAC : in std_logic; | |
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160 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); | |
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161 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
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162 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
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163 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
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164 | ); | |
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165 | end COMPONENT; | |
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155 | ); | |
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156 | PORT( | |
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157 | clk : IN STD_LOGIC; | |
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158 | reset : IN STD_LOGIC; | |
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159 | clr_MAC : IN STD_LOGIC; | |
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160 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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161 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
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162 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
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163 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
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164 | ); | |
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165 | END COMPONENT; | |
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166 | 166 | |
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167 | 167 | --------------------------------------------------------- |
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168 | 168 | -------- // Sélection grace a l'entrée "ctrl" \\ -------- |
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169 | 169 | --------------------------------------------------------- |
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170 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; | |
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171 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; | |
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172 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; | |
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173 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; | |
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174 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; | |
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170 | CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; | |
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171 | CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001"; | |
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172 | CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010"; | |
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173 | CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011"; | |
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174 | CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100"; | |
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175 | 175 | |
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176 | 176 | |
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177 | Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; | |
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178 | Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; | |
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179 | Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; | |
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180 | Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; | |
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181 | Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; | |
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177 | CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; | |
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178 | CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; | |
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179 | CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; | |
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180 | CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; | |
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181 | CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; | |
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182 | 182 | --------------------------------------------------------- |
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183 | 183 | |
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184 | 184 | COMPONENT MAC IS |
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185 | 185 | GENERIC( |
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186 | 186 | Input_SZ_A : INTEGER := 8; |
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187 | 187 | Input_SZ_B : INTEGER := 8; |
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188 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
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188 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
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189 | 189 | ); |
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190 | 190 | PORT( |
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191 | 191 | clk : IN STD_LOGIC; |
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192 | 192 | reset : IN STD_LOGIC; |
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193 | 193 | clr_MAC : IN STD_LOGIC; |
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194 | 194 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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195 | 195 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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196 | 196 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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197 | 197 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
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198 | 198 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
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199 | 199 | ); |
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200 | 200 | END COMPONENT; |
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201 | 201 | |
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202 |
COMPONENT TwoComplementer |
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203 | generic( | |
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204 |
Input_SZ : |
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205 | port( | |
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206 |
clk : |
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207 |
reset : |
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208 |
clr : |
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209 |
TwoComp : |
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210 |
OP : |
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211 |
RES : |
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212 | ); | |
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213 |
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202 | COMPONENT TwoComplementer IS | |
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203 | GENERIC( | |
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204 | Input_SZ : INTEGER := 16); | |
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205 | PORT( | |
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206 | clk : IN STD_LOGIC; --! Horloge du composant | |
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207 | reset : IN STD_LOGIC; --! Reset general du composant | |
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208 | clr : IN STD_LOGIC; --! Un reset spécifique au programme | |
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209 | TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément | |
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210 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée | |
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211 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non | |
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212 | ); | |
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213 | END COMPONENT; | |
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214 | 214 | |
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215 | 215 | COMPONENT MAC_CONTROLER IS |
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216 | 216 | PORT( |
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217 | 217 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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218 | 218 | MULT : OUT STD_LOGIC; |
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219 | 219 | ADD : OUT STD_LOGIC; |
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220 | 220 | -- LOAD_ADDER : out std_logic; |
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221 | 221 | MACMUX_sel : OUT STD_LOGIC; |
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222 | 222 | MACMUX2_sel : OUT STD_LOGIC |
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223 | 223 | ); |
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224 | 224 | END COMPONENT; |
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225 | 225 | |
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226 | 226 | COMPONENT MAC_MUX IS |
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227 | 227 | GENERIC( |
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228 | 228 | Input_SZ_A : INTEGER := 16; |
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229 | 229 | Input_SZ_B : INTEGER := 16 |
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230 | 230 | |
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231 | 231 | ); |
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232 | 232 | PORT( |
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233 | 233 | sel : IN STD_LOGIC; |
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234 | 234 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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235 | 235 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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236 | 236 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
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237 | 237 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
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238 | 238 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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239 | 239 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) |
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240 | 240 | ); |
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241 | 241 | END COMPONENT; |
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242 | 242 | |
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243 | 243 | |
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244 | 244 | COMPONENT MAC_MUX2 IS |
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245 | 245 | GENERIC(Input_SZ : INTEGER := 16); |
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246 | 246 | PORT( |
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247 | 247 | sel : IN STD_LOGIC; |
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248 | 248 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
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249 | 249 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
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250 | 250 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
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251 | 251 | ); |
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252 | 252 | END COMPONENT; |
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253 | 253 | |
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254 | 254 | |
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255 | 255 | COMPONENT MAC_REG IS |
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256 | 256 | GENERIC(size : INTEGER := 16); |
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257 | 257 | PORT( |
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258 | 258 | reset : IN STD_LOGIC; |
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259 | 259 | clk : IN STD_LOGIC; |
|
260 | 260 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
261 | 261 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
262 | 262 | ); |
|
263 | 263 | END COMPONENT; |
|
264 | 264 | |
|
265 | 265 | |
|
266 | 266 | COMPONENT MUX2 IS |
|
267 | 267 | GENERIC(Input_SZ : INTEGER := 16); |
|
268 | 268 | PORT( |
|
269 | 269 | sel : IN STD_LOGIC; |
|
270 | 270 | IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
271 | 271 | IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
272 | 272 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
273 | 273 | ); |
|
274 | 274 | END COMPONENT; |
|
275 | 275 | |
|
276 | 276 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
277 | 277 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; |
|
278 | ||
|
278 | ||
|
279 | 279 | COMPONENT MUXN |
|
280 | 280 | GENERIC ( |
|
281 | 281 | Input_SZ : INTEGER; |
|
282 | 282 | NbStage : INTEGER); |
|
283 | 283 | PORT ( |
|
284 | 284 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); |
|
285 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); | |
|
285 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0); | |
|
286 | 286 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
287 | 287 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); |
|
288 | 288 | END COMPONENT; |
|
289 | 289 | |
|
290 | ||
|
290 | ||
|
291 | 291 | |
|
292 | 292 | COMPONENT Multiplier IS |
|
293 | 293 | GENERIC( |
|
294 | 294 | Input_SZ_A : INTEGER := 16; |
|
295 | 295 | Input_SZ_B : INTEGER := 16 |
|
296 | 296 | |
|
297 | 297 | ); |
|
298 | 298 | PORT( |
|
299 | 299 | clk : IN STD_LOGIC; |
|
300 | 300 | reset : IN STD_LOGIC; |
|
301 | 301 | mult : IN STD_LOGIC; |
|
302 | 302 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
303 | 303 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
304 | 304 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
305 | 305 | ); |
|
306 | 306 | END COMPONENT; |
|
307 | 307 | |
|
308 | 308 | COMPONENT REG IS |
|
309 | 309 | GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0); |
|
310 | 310 | PORT( |
|
311 | 311 | reset : IN STD_LOGIC; |
|
312 | 312 | clk : IN STD_LOGIC; |
|
313 | 313 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
314 | 314 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
315 | 315 | ); |
|
316 | 316 | END COMPONENT; |
|
317 | 317 | |
|
318 | 318 | |
|
319 | 319 | |
|
320 | 320 | COMPONENT RShifter IS |
|
321 | 321 | GENERIC( |
|
322 | 322 | Input_SZ : INTEGER := 16; |
|
323 | 323 | shift_SZ : INTEGER := 4 |
|
324 | 324 | ); |
|
325 | 325 | PORT( |
|
326 | 326 | clk : IN STD_LOGIC; |
|
327 | 327 | reset : IN STD_LOGIC; |
|
328 | 328 | shift : IN STD_LOGIC; |
|
329 | 329 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
330 | 330 | cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0); |
|
331 | 331 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
332 | 332 | ); |
|
333 | 333 | END COMPONENT; |
|
334 | 334 | |
|
335 | 335 | COMPONENT SYNC_FF |
|
336 | 336 | GENERIC ( |
|
337 | 337 | NB_FF_OF_SYNC : INTEGER); |
|
338 | 338 | PORT ( |
|
339 | 339 | clk : IN STD_LOGIC; |
|
340 | 340 | rstn : IN STD_LOGIC; |
|
341 | 341 | A : IN STD_LOGIC; |
|
342 | 342 | A_sync : OUT STD_LOGIC); |
|
343 | 343 | END COMPONENT; |
|
344 | 344 | |
|
345 | 345 | COMPONENT lpp_front_to_level |
|
346 | 346 | PORT ( |
|
347 | 347 | clk : IN STD_LOGIC; |
|
348 | 348 | rstn : IN STD_LOGIC; |
|
349 | 349 | sin : IN STD_LOGIC; |
|
350 | 350 | sout : OUT STD_LOGIC); |
|
351 | 351 | END COMPONENT; |
|
352 | 352 | |
|
353 | 353 | COMPONENT lpp_front_detection |
|
354 | 354 | PORT ( |
|
355 | 355 | clk : IN STD_LOGIC; |
|
356 | 356 | rstn : IN STD_LOGIC; |
|
357 | 357 | sin : IN STD_LOGIC; |
|
358 | 358 | sout : OUT STD_LOGIC); |
|
359 | 359 | END COMPONENT; |
|
360 | 360 | |
|
361 | 361 | COMPONENT lpp_front_positive_detection |
|
362 | 362 | PORT ( |
|
363 | 363 | clk : IN STD_LOGIC; |
|
364 | 364 | rstn : IN STD_LOGIC; |
|
365 | 365 | sin : IN STD_LOGIC; |
|
366 | 366 | sout : OUT STD_LOGIC); |
|
367 | 367 | END COMPONENT; |
|
368 | ||
|
368 | ||
|
369 | 369 | --COMPONENT SYNC_VALID_BIT |
|
370 | 370 | -- GENERIC ( |
|
371 | 371 | -- NB_FF_OF_SYNC : INTEGER); |
|
372 | 372 | -- PORT ( |
|
373 | 373 | -- clk_in : IN STD_LOGIC; |
|
374 | 374 | -- clk_out : IN STD_LOGIC; |
|
375 | 375 | -- rstn : IN STD_LOGIC; |
|
376 | 376 | -- sin : IN STD_LOGIC; |
|
377 | 377 | -- sout : OUT STD_LOGIC); |
|
378 | 378 | --END COMPONENT; |
|
379 | 379 | |
|
380 | 380 | COMPONENT SYNC_VALID_BIT |
|
381 | 381 | GENERIC ( |
|
382 | 382 | NB_FF_OF_SYNC : INTEGER); |
|
383 | 383 | PORT ( |
|
384 | 384 | clk_in : IN STD_LOGIC; |
|
385 | 385 | rstn_in : IN STD_LOGIC; |
|
386 | 386 | clk_out : IN STD_LOGIC; |
|
387 | 387 | rstn_out : IN STD_LOGIC; |
|
388 | 388 | sin : IN STD_LOGIC; |
|
389 | 389 | sout : OUT STD_LOGIC); |
|
390 | 390 | END COMPONENT; |
|
391 | 391 | |
|
392 | 392 | COMPONENT RR_Arbiter_4 |
|
393 | 393 | PORT ( |
|
394 | 394 | clk : IN STD_LOGIC; |
|
395 | 395 | rstn : IN STD_LOGIC; |
|
396 | 396 | in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
397 | 397 | out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
398 | 398 | END COMPONENT; |
|
399 | 399 | |
|
400 |
COMPONENT Clock_Divider |
|
|
401 | generic(N :integer := 10); | |
|
402 | port( | |
|
403 | clk, rst : in std_logic; | |
|
404 | sclk : out std_logic); | |
|
405 |
|
|
|
400 | COMPONENT Clock_Divider IS | |
|
401 | GENERIC(N : INTEGER := 10); | |
|
402 | PORT( | |
|
403 | clk, rst : IN STD_LOGIC; | |
|
404 | sclk : OUT STD_LOGIC); | |
|
405 | END COMPONENT; | |
|
406 | ||
|
407 | COMPONENT ramp_generator | |
|
408 | GENERIC ( | |
|
409 | DATA_SIZE : INTEGER; | |
|
410 | VALUE_UNSIGNED_INIT : INTEGER; | |
|
411 | VALUE_UNSIGNED_INCR : INTEGER; | |
|
412 | VALUE_UNSIGNED_MASK : INTEGER); | |
|
413 | PORT ( | |
|
414 | clk : IN STD_LOGIC; | |
|
415 | rstn : IN STD_LOGIC; | |
|
416 | new_data : IN STD_LOGIC; | |
|
417 | output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); | |
|
418 | END COMPONENT; | |
|
406 | 419 | |
|
407 | 420 | END; |
@@ -1,26 +1,27 | |||
|
1 | 1 | data_type_pkg.vhd |
|
2 | 2 | general_purpose.vhd |
|
3 | 3 | ADDRcntr.vhd |
|
4 | 4 | ALU.vhd |
|
5 | 5 | Adder.vhd |
|
6 | 6 | Clk_Divider2.vhd |
|
7 | 7 | Clk_divider.vhd |
|
8 | 8 | MAC.vhd |
|
9 | 9 | MAC_CONTROLER.vhd |
|
10 | 10 | MAC_MUX.vhd |
|
11 | 11 | MAC_MUX2.vhd |
|
12 | 12 | MAC_REG.vhd |
|
13 | 13 | MUX2.vhd |
|
14 | 14 | MUXN.vhd |
|
15 | 15 | Multiplier.vhd |
|
16 | 16 | REG.vhd |
|
17 | 17 | SYNC_FF.vhd |
|
18 | 18 | Shifter.vhd |
|
19 | 19 | TwoComplementer.vhd |
|
20 | 20 | Clock_Divider.vhd |
|
21 | 21 | lpp_front_to_level.vhd |
|
22 | 22 | lpp_front_detection.vhd |
|
23 | 23 | lpp_front_positive_detection.vhd |
|
24 | 24 | SYNC_VALID_BIT.vhd |
|
25 | 25 | RR_Arbiter_4.vhd |
|
26 | 26 | general_counter.vhd |
|
27 | ramp_generator.vhd |
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