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WaveForm Picker : Big Endian Correction
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r206:82098655f36b em-2013-07-24-vhdlib206 JC
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1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY grlib;
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
7 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
8 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
10
10
11 LIBRARY lpp;
11 LIBRARY lpp;
12 USE lpp.lpp_waveform_pkg.ALL;
12 USE lpp.lpp_waveform_pkg.ALL;
13
13
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 ENTITY lpp_waveform IS
17 ENTITY lpp_waveform IS
18
18
19 GENERIC (
19 GENERIC (
20 hindex : INTEGER := 2;
20 hindex : INTEGER := 2;
21 tech : INTEGER := inferred;
21 tech : INTEGER := inferred;
22 data_size : INTEGER := 160;
22 data_size : INTEGER := 160;
23 nb_burst_available_size : INTEGER := 11;
23 nb_burst_available_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
25 delta_snapshot_size : INTEGER := 16;
25 delta_snapshot_size : INTEGER := 16;
26 delta_f2_f0_size : INTEGER := 10;
26 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f1_size : INTEGER := 10);
27 delta_f2_f1_size : INTEGER := 10);
28
28
29 PORT (
29 PORT (
30 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32
32
33 -- AMBA AHB Master Interface
33 -- AMBA AHB Master Interface
34 AHB_Master_In : IN AHB_Mst_In_Type;
34 AHB_Master_In : IN AHB_Mst_In_Type;
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
36
36
37 coarse_time_0 : IN STD_LOGIC;
37 coarse_time_0 : IN STD_LOGIC;
38
38
39 --config
39 --config
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
43
43
44 enable_f0 : IN STD_LOGIC;
44 enable_f0 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
48
48
49 burst_f0 : IN STD_LOGIC;
49 burst_f0 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
52
52
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63
63
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
68
68
69 data_f0_in_valid : IN STD_LOGIC;
69 data_f0_in_valid : IN STD_LOGIC;
70 data_f1_in_valid : IN STD_LOGIC;
70 data_f1_in_valid : IN STD_LOGIC;
71 data_f2_in_valid : IN STD_LOGIC;
71 data_f2_in_valid : IN STD_LOGIC;
72 data_f3_in_valid : IN STD_LOGIC
72 data_f3_in_valid : IN STD_LOGIC
73 );
73 );
74
74
75 END lpp_waveform;
75 END lpp_waveform;
76
76
77 ARCHITECTURE beh OF lpp_waveform IS
77 ARCHITECTURE beh OF lpp_waveform IS
78 SIGNAL start_snapshot_f0 : STD_LOGIC;
78 SIGNAL start_snapshot_f0 : STD_LOGIC;
79 SIGNAL start_snapshot_f1 : STD_LOGIC;
79 SIGNAL start_snapshot_f1 : STD_LOGIC;
80 SIGNAL start_snapshot_f2 : STD_LOGIC;
80 SIGNAL start_snapshot_f2 : STD_LOGIC;
81
81
82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86
86
87 SIGNAL data_f0_out_valid : STD_LOGIC;
87 SIGNAL data_f0_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
92
92
93 --
93 --
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --
102 --
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
106
106
107 BEGIN -- beh
107 BEGIN -- beh
108
108
109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
110 GENERIC MAP (
110 GENERIC MAP (
111 delta_snapshot_size => delta_snapshot_size,
111 delta_snapshot_size => delta_snapshot_size,
112 delta_f2_f0_size => delta_f2_f0_size,
112 delta_f2_f0_size => delta_f2_f0_size,
113 delta_f2_f1_size => delta_f2_f1_size)
113 delta_f2_f1_size => delta_f2_f1_size)
114 PORT MAP (
114 PORT MAP (
115 clk => clk,
115 clk => clk,
116 rstn => rstn,
116 rstn => rstn,
117 delta_snapshot => delta_snapshot,
117 delta_snapshot => delta_snapshot,
118 delta_f2_f1 => delta_f2_f1,
118 delta_f2_f1 => delta_f2_f1,
119 delta_f2_f0 => delta_f2_f0,
119 delta_f2_f0 => delta_f2_f0,
120 coarse_time_0 => coarse_time_0,
120 coarse_time_0 => coarse_time_0,
121 data_f0_in_valid => data_f0_in_valid,
121 data_f0_in_valid => data_f0_in_valid,
122 data_f2_in_valid => data_f2_in_valid,
122 data_f2_in_valid => data_f2_in_valid,
123 start_snapshot_f0 => start_snapshot_f0,
123 start_snapshot_f0 => start_snapshot_f0,
124 start_snapshot_f1 => start_snapshot_f1,
124 start_snapshot_f1 => start_snapshot_f1,
125 start_snapshot_f2 => start_snapshot_f2);
125 start_snapshot_f2 => start_snapshot_f2);
126
126
127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
128 GENERIC MAP (
128 GENERIC MAP (
129 data_size => data_size,
129 data_size => data_size,
130 nb_snapshot_param_size => nb_snapshot_param_size)
130 nb_snapshot_param_size => nb_snapshot_param_size)
131 PORT MAP (
131 PORT MAP (
132 clk => clk,
132 clk => clk,
133 rstn => rstn,
133 rstn => rstn,
134 enable => enable_f0,
134 enable => enable_f0,
135 burst_enable => burst_f0,
135 burst_enable => burst_f0,
136 nb_snapshot_param => nb_snapshot_param,
136 nb_snapshot_param => nb_snapshot_param,
137 start_snapshot => start_snapshot_f0,
137 start_snapshot => start_snapshot_f0,
138 data_in => data_f0_in,
138 data_in => data_f0_in,
139 data_in_valid => data_f0_in_valid,
139 data_in_valid => data_f0_in_valid,
140 data_out => data_f0_out,
140 data_out => data_f0_out,
141 data_out_valid => data_f0_out_valid);
141 data_out_valid => data_f0_out_valid);
142
142
143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
144
144
145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
146 GENERIC MAP (
146 GENERIC MAP (
147 data_size => data_size,
147 data_size => data_size,
148 nb_snapshot_param_size => nb_snapshot_param_size+1)
148 nb_snapshot_param_size => nb_snapshot_param_size+1)
149 PORT MAP (
149 PORT MAP (
150 clk => clk,
150 clk => clk,
151 rstn => rstn,
151 rstn => rstn,
152 enable => enable_f1,
152 enable => enable_f1,
153 burst_enable => burst_f1,
153 burst_enable => burst_f1,
154 nb_snapshot_param => nb_snapshot_param_more_one,
154 nb_snapshot_param => nb_snapshot_param_more_one,
155 start_snapshot => start_snapshot_f1,
155 start_snapshot => start_snapshot_f1,
156 data_in => data_f1_in,
156 data_in => data_f1_in,
157 data_in_valid => data_f1_in_valid,
157 data_in_valid => data_f1_in_valid,
158 data_out => data_f1_out,
158 data_out => data_f1_out,
159 data_out_valid => data_f1_out_valid);
159 data_out_valid => data_f1_out_valid);
160
160
161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
162 GENERIC MAP (
162 GENERIC MAP (
163 data_size => data_size,
163 data_size => data_size,
164 nb_snapshot_param_size => nb_snapshot_param_size+1)
164 nb_snapshot_param_size => nb_snapshot_param_size+1)
165 PORT MAP (
165 PORT MAP (
166 clk => clk,
166 clk => clk,
167 rstn => rstn,
167 rstn => rstn,
168 enable => enable_f2,
168 enable => enable_f2,
169 burst_enable => burst_f2,
169 burst_enable => burst_f2,
170 nb_snapshot_param => nb_snapshot_param_more_one,
170 nb_snapshot_param => nb_snapshot_param_more_one,
171 start_snapshot => start_snapshot_f2,
171 start_snapshot => start_snapshot_f2,
172 data_in => data_f2_in,
172 data_in => data_f2_in,
173 data_in_valid => data_f2_in_valid,
173 data_in_valid => data_f2_in_valid,
174 data_out => data_f2_out,
174 data_out => data_f2_out,
175 data_out_valid => data_f2_out_valid);
175 data_out_valid => data_f2_out_valid);
176
176
177 lpp_waveform_burst_f3: lpp_waveform_burst
177 lpp_waveform_burst_f3: lpp_waveform_burst
178 GENERIC MAP (
178 GENERIC MAP (
179 data_size => data_size)
179 data_size => data_size)
180 PORT MAP (
180 PORT MAP (
181 clk => clk,
181 clk => clk,
182 rstn => rstn,
182 rstn => rstn,
183 enable => enable_f3,
183 enable => enable_f3,
184 data_in => data_f3_in,
184 data_in => data_f3_in,
185 data_in_valid => data_f3_in_valid,
185 data_in_valid => data_f3_in_valid,
186 data_out => data_f3_out,
186 data_out => data_f3_out,
187 data_out_valid => data_f3_out_valid);
187 data_out_valid => data_f3_out_valid);
188
188
189
189
190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
191
191
192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
194 PORT MAP (
194 PORT MAP (
195 HCLK => clk,
195 HCLK => clk,
196 HRESETn => rstn,
196 HRESETn => rstn,
197 valid_in => valid_in(I),
197 valid_in => valid_in(I),
198 ack_in => valid_ack(I),
198 ack_in => valid_ack(I),
199 valid_out => valid_out(I),
199 valid_out => valid_out(I),
200 error => status_new_err(I));
200 error => status_new_err(I));
201 END GENERATE all_input_valid;
201 END GENERATE all_input_valid;
202
202
203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
204 GENERIC MAP (tech => tech)
204 GENERIC MAP (tech => tech)
205 PORT MAP (
205 PORT MAP (
206 clk => clk,
206 clk => clk,
207 rstn => rstn,
207 rstn => rstn,
208 data_f0_valid => valid_out(0),
208 data_f0_valid => valid_out(0),
209 data_f1_valid => valid_out(1),
209 data_f1_valid => valid_out(1),
210 data_f2_valid => valid_out(2),
210 data_f2_valid => valid_out(2),
211 data_f3_valid => valid_out(3),
211 data_f3_valid => valid_out(3),
212
212
213 data_valid_ack => valid_ack,
213 data_valid_ack => valid_ack,
214
214
215 data_f0 => data_f0_out,
215 data_f0 => data_f0_out,
216 data_f1 => data_f1_out,
216 data_f1 => data_f1_out,
217 data_f2 => data_f2_out,
217 data_f2 => data_f2_out,
218 data_f3 => data_f3_out,
218 data_f3 => data_f3_out,
219
219
220 ready => ready_arb,
220 ready => ready_arb,
221 time_wen => time_wen,
221 time_wen => time_wen,
222 data_wen => data_wen,
222 data_wen => data_wen,
223 data => wdata);
223 data => wdata);
224
224
225 ready_arb <= NOT ready;
225 ready_arb <= NOT ready;
226
226
227 lpp_waveform_fifo_1: lpp_waveform_fifo
227 lpp_waveform_fifo_1: lpp_waveform_fifo
228 GENERIC MAP (tech => tech)
228 GENERIC MAP (tech => tech)
229 PORT MAP (
229 PORT MAP (
230 clk => clk,
230 clk => clk,
231 rstn => rstn,
231 rstn => rstn,
232 ready => ready,
232 ready => ready,
233 time_ren => time_ren, -- todo
233 time_ren => time_ren, -- todo
234 data_ren => data_ren, -- todo
234 data_ren => data_ren, -- todo
235 rdata => rdata, -- todo
235 rdata => rdata, -- todo
236
236
237 time_wen => time_wen,
237 time_wen => time_wen,
238 data_wen => data_wen,
238 data_wen => data_wen,
239 wdata => wdata);
239 wdata => wdata);
240
241 --time_ren <= (OTHERS => '1');
242 --data_ren <= (OTHERS => '1');
243
240
244 pp_waveform_dma_1: lpp_waveform_dma
241 pp_waveform_dma_1: lpp_waveform_dma
245 GENERIC MAP (
242 GENERIC MAP (
246 data_size => data_size,
243 data_size => data_size,
247 tech => tech,
244 tech => tech,
248 hindex => hindex,
245 hindex => hindex,
249 nb_burst_available_size => nb_burst_available_size)
246 nb_burst_available_size => nb_burst_available_size)
250 PORT MAP (
247 PORT MAP (
251 HCLK => clk,
248 HCLK => clk,
252 HRESETn => rstn,
249 HRESETn => rstn,
253 AHB_Master_In => AHB_Master_In,
250 AHB_Master_In => AHB_Master_In,
254 AHB_Master_Out => AHB_Master_Out,
251 AHB_Master_Out => AHB_Master_Out,
255 data_ready => ready,
252 data_ready => ready,
256 data => rdata,
253 data => rdata,
257 data_data_ren => data_ren,
254 data_data_ren => data_ren,
258 data_time_ren => time_ren,
255 data_time_ren => time_ren,
259 --data_f0_in => data_f0_out,
260 --data_f1_in => data_f1_out,
261 --data_f2_in => data_f2_out,
262 --data_f3_in => data_f3_out,
263 --data_f0_in_valid => data_f0_out_valid,
264 --data_f1_in_valid => data_f1_out_valid,
265 --data_f2_in_valid => data_f2_out_valid,
266 --data_f3_in_valid => data_f3_out_valid,
267 nb_burst_available => nb_burst_available,
256 nb_burst_available => nb_burst_available,
268 status_full => status_full,
257 status_full => status_full,
269 status_full_ack => status_full_ack,
258 status_full_ack => status_full_ack,
270 status_full_err => status_full_err,
259 status_full_err => status_full_err,
271 addr_data_f0 => addr_data_f0,
260 addr_data_f0 => addr_data_f0,
272 addr_data_f1 => addr_data_f1,
261 addr_data_f1 => addr_data_f1,
273 addr_data_f2 => addr_data_f2,
262 addr_data_f2 => addr_data_f2,
274 addr_data_f3 => addr_data_f3);
263 addr_data_f3 => addr_data_f3);
275
264
276 END beh;
265 END beh;
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@@ -1,386 +1,326
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_waveform_dma IS
45 ENTITY lpp_waveform_dma IS
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER := 160;
47 data_size : INTEGER := 160;
48 tech : INTEGER := inferred;
48 tech : INTEGER := inferred;
49 hindex : INTEGER := 2;
49 hindex : INTEGER := 2;
50 nb_burst_available_size : INTEGER := 11
50 nb_burst_available_size : INTEGER := 11
51 );
51 );
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 -- Reg
64 -- Reg
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
74 );
74 );
75 END;
75 END;
76
76
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 SIGNAL DMAIn : DMA_In_Type;
79 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
82 TYPE state_DMAWriteBurst IS (IDLE,
83 SEND_TIME_0, WAIT_TIME_0,
83 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
84 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
85 SEND_5_TIME,
86 SEND_DATA, WAIT_DATA);
86 SEND_DATA, WAIT_DATA);
87 SIGNAL state : state_DMAWriteBurst ;
87 SIGNAL state : state_DMAWriteBurst ;
88 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
89 -- CONTROL
89 -- CONTROL
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
93 SIGNAL time_select : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
96 SIGNAL time_already_send_s : STD_LOGIC;
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 -- SEND TIME MODULE
98 -- SEND TIME MODULE
99 SIGNAL time_dmai : DMA_In_Type;
99 SIGNAL time_dmai : DMA_In_Type;
100 SIGNAL time_send : STD_LOGIC;
100 SIGNAL time_send : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106 -- SEND DATA MODULE
106 -- SEND DATA MODULE
107 SIGNAL data_dmai : DMA_In_Type;
107 SIGNAL data_dmai : DMA_In_Type;
108 SIGNAL data_send : STD_LOGIC;
108 SIGNAL data_send : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 -- SELECT ADDRESS
114 -- SELECT ADDRESS
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 SIGNAL send_16_3_time : STD_LOGIC;
123 SIGNAL send_16_3_time : STD_LOGIC;
124 SIGNAL count_send_time : INTEGER;
124 SIGNAL count_send_time : INTEGER;
125 -----------------------------------------------------------------------------
126 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
125 BEGIN
127 BEGIN
126
128
127 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
128 -- DMA to AHB interface
130 -- DMA to AHB interface
129 DMA2AHB_1 : DMA2AHB
131 DMA2AHB_1 : DMA2AHB
130 GENERIC MAP (
132 GENERIC MAP (
131 hindex => hindex,
133 hindex => hindex,
132 vendorid => VENDOR_LPP,
134 vendorid => VENDOR_LPP,
133 deviceid => 10,
135 deviceid => 10,
134 version => 0,
136 version => 0,
135 syncrst => 1,
137 syncrst => 1,
136 boundary => 1) -- FIX 11/01/2013
138 boundary => 1) -- FIX 11/01/2013
137 PORT MAP (
139 PORT MAP (
138 HCLK => HCLK,
140 HCLK => HCLK,
139 HRESETn => HRESETn,
141 HRESETn => HRESETn,
140 DMAIn => DMAIn,
142 DMAIn => DMAIn,
141 DMAOut => DMAOut,
143 DMAOut => DMAOut,
142 AHBIn => AHB_Master_In,
144 AHBIn => AHB_Master_In,
143 AHBOut => AHB_Master_Out);
145 AHBOut => AHB_Master_Out);
144 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
145
147
146 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
147 -- This module memorises when the Times info are write. When FSM send
149 -- This module memorises when the Times info are write. When FSM send
148 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
150 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
149 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
151 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
150 PROCESS (HCLK, HRESETn)
152 PROCESS (HCLK, HRESETn)
151 BEGIN -- PROCESS
153 BEGIN -- PROCESS
152 IF HRESETn = '0' THEN -- asynchronous reset (active low)
154 IF HRESETn = '0' THEN -- asynchronous reset (active low)
153 time_already_send(I) <= '0';
155 time_already_send(I) <= '0';
154 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
156 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
155 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
157 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
156 time_already_send(I) <= '1';
158 time_already_send(I) <= '1';
157 ELSIF status_full_ack(I) = '1' THEN
159 ELSIF status_full_ack(I) = '1' THEN
158 time_already_send(I) <= '0';
160 time_already_send(I) <= '0';
159 END IF;
161 END IF;
160 END IF;
162 END IF;
161 END PROCESS;
163 END PROCESS;
162 END GENERATE all_time_write;
164 END GENERATE all_time_write;
163
165
164
166
165
167
166 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
167 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
169 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
168 "01" WHEN data_ready(1) = '1' ELSE
170 "01" WHEN data_ready(1) = '1' ELSE
169 "10" WHEN data_ready(2) = '1' ELSE
171 "10" WHEN data_ready(2) = '1' ELSE
170 "11";
172 "11";
171
173
172 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
174 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
173 time_already_send(1) WHEN data_ready(1) = '1' ELSE
175 time_already_send(1) WHEN data_ready(1) = '1' ELSE
174 time_already_send(2) WHEN data_ready(2) = '1' ELSE
176 time_already_send(2) WHEN data_ready(2) = '1' ELSE
175 time_already_send(3);
177 time_already_send(3);
176
177
178 --send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
179 -- send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
180 -- send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
181 -- send_16_3_time_reg(9) ;
182
183 --all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
184 -- send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
185 -- send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
186 -- send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
187 --END GENERATE all_send_16_3;
188
178
189 -- DMA control
179 -- DMA control
190 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
180 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
191 BEGIN -- PROCESS DMAWriteBurst_p
181 BEGIN -- PROCESS DMAWriteBurst_p
192 IF HRESETn = '0' THEN
182 IF HRESETn = '0' THEN
193 state <= IDLE;
183 state <= IDLE;
194
184
195 sel_data <= "00";
185 sel_data <= "00";
196 update <= "00";
186 update <= "00";
197 time_select <= '0';
187 time_select <= '0';
198 time_fifo_ren <= '1';
188 time_fifo_ren <= '1';
199 data_send <= '0';
189 data_send <= '0';
200 time_send <= '0';
190 time_send <= '0';
201 time_write <= '0';
191 time_write <= '0';
202 --send_16_3_time <= "001";
203 --send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
204 --send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
205 --send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
206 --send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
207
192
208 count_send_time <= 0;
193 count_send_time <= 0;
209 ELSIF HCLK'EVENT AND HCLK = '1' THEN
194 ELSIF HCLK'EVENT AND HCLK = '1' THEN
210
195
211 CASE state IS
196 CASE state IS
212 WHEN IDLE =>
197 WHEN IDLE =>
213 count_send_time <= 0;
198 count_send_time <= 0;
214 sel_data <= "00";
199 sel_data <= "00";
215 update <= "00";
200 update <= "00";
216 time_select <= '0';
201 time_select <= '0';
217 time_fifo_ren <= '1';
202 time_fifo_ren <= '1';
218 data_send <= '0';
203 data_send <= '0';
219 time_send <= '0';
204 time_send <= '0';
220 time_write <= '0';
205 time_write <= '0';
221
206
222 IF data_ready = "0000" THEN
207 IF data_ready = "0000" THEN
223 state <= IDLE;
208 state <= IDLE;
224 ELSE
209 ELSE
225 sel_data <= sel_data_s;
210 sel_data <= sel_data_s;
226 --send_16_3_time_reg <= send_16_3_time_reg_s;
227 --IF send_16_3_time = '1' THEN
228 -- state <= SEND_TIME_0;
229 --ELSE
230 -- state <= SEND_5_TIME;
231 --END IF;
232 state <= SEND_5_TIME;
211 state <= SEND_5_TIME;
233 END IF;
212 END IF;
234
235 --WHEN SEND_TIME_0 =>
236 -- time_select <= '1';
237 -- IF time_already_send_s = '0' THEN
238 -- time_send <= '1';
239 -- state <= WAIT_TIME_0;
240 -- ELSE
241 -- time_send <= '0';
242 -- state <= SEND_TIME_1;
243 -- END IF;
244 -- time_fifo_ren <= '0';
245
246 --WHEN WAIT_TIME_0 =>
247 -- time_fifo_ren <= '1';
248 -- update <= "00";
249 -- time_send <= '0';
250 -- IF time_send_ok = '1' OR time_send_ko = '1' THEN
251 -- update <= "01";
252 -- state <= SEND_TIME_1;
253 -- END IF;
254
255 --WHEN SEND_TIME_1 =>
256 -- time_select <= '1';
257 -- IF time_already_send_s = '0' THEN
258 -- time_send <= '1';
259 -- state <= WAIT_TIME_1;
260 -- ELSE
261 -- time_send <= '0';
262 -- state <= SEND_5_TIME;
263 -- END IF;
264 -- time_fifo_ren <= '0';
265
266 --WHEN WAIT_TIME_1 =>
267 -- time_fifo_ren <= '1';
268 -- update <= "00";
269 -- time_send <= '0';
270 -- IF time_send_ok = '1' OR time_send_ko = '1' THEN
271 -- time_write <= '1';
272 -- update <= "01";
273 -- state <= SEND_5_TIME;
274 -- END IF;
275
213
276 WHEN SEND_5_TIME =>
214 WHEN SEND_5_TIME =>
277 update <= "00";
215 update <= "00";
278 time_select <= '1';
216 time_select <= '1';
279 time_fifo_ren <= '0';
217 time_fifo_ren <= '0';
280 count_send_time <= count_send_time + 1;
218 count_send_time <= count_send_time + 1;
281 IF count_send_time = 10 THEN
219 IF count_send_time = 10 THEN
282 state <= SEND_DATA;
220 state <= SEND_DATA;
283 END IF;
221 END IF;
284
222
285 WHEN SEND_DATA =>
223 WHEN SEND_DATA =>
286 time_fifo_ren <= '1';
224 time_fifo_ren <= '1';
287 time_write <= '0';
225 time_write <= '0';
288 time_send <= '0';
226 time_send <= '0';
289
227
290 time_select <= '0';
228 time_select <= '0';
291 data_send <= '1';
229 data_send <= '1';
292 update <= "00";
230 update <= "00";
293 state <= WAIT_DATA;
231 state <= WAIT_DATA;
294
232
295 WHEN WAIT_DATA =>
233 WHEN WAIT_DATA =>
296 data_send <= '0';
234 data_send <= '0';
297
235
298 IF data_send_ok = '1' OR data_send_ko = '1' THEN
236 IF data_send_ok = '1' OR data_send_ko = '1' THEN
299 state <= IDLE;
237 state <= IDLE;
300 update <= "10";
238 update <= "10";
301 END IF;
239 END IF;
302
240
303 WHEN OTHERS => NULL;
241 WHEN OTHERS => NULL;
304 END CASE;
242 END CASE;
305
243
306 END IF;
244 END IF;
307 END PROCESS DMAWriteFSM_p;
245 END PROCESS DMAWriteFSM_p;
308 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
309
247
310
248
311
249
312 -----------------------------------------------------------------------------
250 -----------------------------------------------------------------------------
313 -- SEND 1 word by DMA
251 -- SEND 1 word by DMA
314 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
315 lpp_dma_send_1word_1 : lpp_dma_send_1word
253 lpp_dma_send_1word_1 : lpp_dma_send_1word
316 PORT MAP (
254 PORT MAP (
317 HCLK => HCLK,
255 HCLK => HCLK,
318 HRESETn => HRESETn,
256 HRESETn => HRESETn,
319 DMAIn => time_dmai,
257 DMAIn => time_dmai,
320 DMAOut => DMAOut,
258 DMAOut => DMAOut,
321
259
322 send => time_send,
260 send => time_send,
323 address => data_address,
261 address => data_address,
324 data => data,
262 data => data,
325 send_ok => time_send_ok,
263 send_ok => time_send_ok,
326 send_ko => time_send_ko
264 send_ko => time_send_ko
327 );
265 );
328
266
329 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
330 -- SEND 16 word by DMA (in burst mode)
268 -- SEND 16 word by DMA (in burst mode)
331 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
270 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
271
332 lpp_dma_send_16word_1 : lpp_dma_send_16word
272 lpp_dma_send_16word_1 : lpp_dma_send_16word
333 PORT MAP (
273 PORT MAP (
334 HCLK => HCLK,
274 HCLK => HCLK,
335 HRESETn => HRESETn,
275 HRESETn => HRESETn,
336 DMAIn => data_dmai,
276 DMAIn => data_dmai,
337 DMAOut => DMAOut,
277 DMAOut => DMAOut,
338
278
339 send => data_send,
279 send => data_send,
340 address => data_address,
280 address => data_address,
341 data => data,
281 data => data_2_halfword,
342 ren => data_fifo_ren,
282 ren => data_fifo_ren,
343 send_ok => data_send_ok,
283 send_ok => data_send_ok,
344 send_ko => data_send_ko);
284 send_ko => data_send_ko);
345
285
346 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
286 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
347 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
287 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
348 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
288 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
349
289
350 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
290 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
351 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
291 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
352 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
292 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
353 END GENERATE all_data_ren;
293 END GENERATE all_data_ren;
354
294
355 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
356 -- SELECT ADDRESS
296 -- SELECT ADDRESS
357 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
297 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
358
298
359 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
299 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
360
300
361 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
301 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
362
302
363 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
303 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
364 GENERIC MAP (
304 GENERIC MAP (
365 nb_burst_available_size => nb_burst_available_size)
305 nb_burst_available_size => nb_burst_available_size)
366 PORT MAP (
306 PORT MAP (
367 HCLK => HCLK,
307 HCLK => HCLK,
368 HRESETn => HRESETn,
308 HRESETn => HRESETn,
369 update => update_and_sel((2*I)+1 DOWNTO 2*I),
309 update => update_and_sel((2*I)+1 DOWNTO 2*I),
370 nb_burst_available => nb_burst_available,
310 nb_burst_available => nb_burst_available,
371 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
311 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
372 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
312 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
373 status_full => status_full(I),
313 status_full => status_full(I),
374 status_full_ack => status_full_ack(I),
314 status_full_ack => status_full_ack(I),
375 status_full_err => status_full_err(I));
315 status_full_err => status_full_err(I));
376
316
377 END GENERATE gen_select_address;
317 END GENERATE gen_select_address;
378
318
379 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
319 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
380 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
320 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
381 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
321 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
382 addr_data_vector(32*3+31 DOWNTO 32*3);
322 addr_data_vector(32*3+31 DOWNTO 32*3);
383 -----------------------------------------------------------------------------
323 -----------------------------------------------------------------------------
384
324
385
325
386 END Behavioral;
326 END Behavioral;
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