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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe Pellion | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | -- jean-christophe.pellion@easii-ic.com | |
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22 | ------------------------------------------------------------------------------- | |
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23 | -- 1.0 - initial version | |
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24 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
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25 | ------------------------------------------------------------------------------- | |
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26 | LIBRARY ieee; | |
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27 | USE ieee.std_logic_1164.ALL; | |
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28 | USE ieee.numeric_std.ALL; | |
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29 | LIBRARY grlib; | |
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30 | USE grlib.amba.ALL; | |
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31 | USE grlib.stdlib.ALL; | |
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32 | USE grlib.devices.ALL; | |
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33 | USE GRLIB.DMA2AHB_Package.ALL; | |
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34 | --USE GRLIB.DMA2AHB_TestPackage.ALL; | |
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35 | LIBRARY lpp; | |
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36 | USE lpp.lpp_amba.ALL; | |
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37 | USE lpp.apb_devices_list.ALL; | |
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38 | USE lpp.lpp_memory.ALL; | |
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39 | USE lpp.lpp_dma_pkg.ALL; | |
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40 | LIBRARY techmap; | |
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41 | USE techmap.gencomp.ALL; | |
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42 | ||
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43 | ||
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44 | ENTITY lpp_dma_ip IS | |
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45 | GENERIC ( | |
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46 | tech : INTEGER := inferred; | |
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47 | hindex : INTEGER := 2; | |
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48 | pindex : INTEGER := 4; | |
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49 | paddr : INTEGER := 4; | |
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50 | pmask : INTEGER := 16#fff#; | |
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51 | pirq : INTEGER := 0); | |
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52 | PORT ( | |
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53 | -- AMBA AHB system signals | |
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54 | HCLK : IN STD_ULOGIC; | |
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55 | HRESETn : IN STD_ULOGIC; | |
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56 | ||
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57 | -- AMBA AHB Master Interface | |
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58 | AHB_Master_In : IN AHB_Mst_In_Type; | |
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59 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
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60 | ||
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61 | -- fifo interface | |
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62 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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63 | fifo_empty : IN STD_LOGIC; | |
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64 | fifo_ren : OUT STD_LOGIC; | |
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65 | ||
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66 | -- header | |
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67 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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68 | header_val : IN STD_LOGIC; | |
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69 | header_ack : OUT STD_LOGIC; | |
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70 | ||
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71 | -- Reg out | |
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72 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
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73 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
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74 | ready_matrix_f1 : OUT STD_LOGIC; | |
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75 | ready_matrix_f2 : OUT STD_LOGIC; | |
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76 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
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77 | error_bad_component_error : OUT STD_LOGIC; | |
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78 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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79 | ||
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80 | -- Reg In | |
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81 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
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82 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
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83 | status_ready_matrix_f1 :IN STD_LOGIC; | |
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84 | status_ready_matrix_f2 :IN STD_LOGIC; | |
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85 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
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86 | status_error_bad_component_error :IN STD_LOGIC; | |
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87 | ||
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88 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
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89 | config_active_interruption_onError : IN STD_LOGIC; | |
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90 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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91 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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92 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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93 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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94 | ); | |
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95 | END; | |
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96 | ||
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97 | ARCHITECTURE Behavioral OF lpp_dma_ip IS | |
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98 | ----------------------------------------------------------------------------- | |
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99 | SIGNAL DMAIn : DMA_In_Type; | |
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100 | SIGNAL header_dmai : DMA_In_Type; | |
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101 | SIGNAL component_dmai : DMA_In_Type; | |
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102 | SIGNAL DMAOut : DMA_OUt_Type; | |
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103 | ----------------------------------------------------------------------------- | |
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104 | ||
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105 | ----------------------------------------------------------------------------- | |
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106 | ----------------------------------------------------------------------------- | |
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107 | TYPE state_DMAWriteBurst IS (IDLE, | |
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108 | TRASH_FIFO, | |
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109 | WAIT_HEADER_ACK, | |
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110 | SEND_DATA, | |
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111 | WAIT_DATA_ACK, | |
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112 | CHECK_LENGTH | |
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113 | ); | |
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114 | SIGNAL state : state_DMAWriteBurst := IDLE; | |
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115 | ||
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116 | SIGNAL nbSend : INTEGER; | |
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117 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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118 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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119 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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120 | SIGNAL header_check_ok : STD_LOGIC; | |
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121 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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122 | SIGNAL send_matrix : STD_LOGIC; | |
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123 | SIGNAL request : STD_LOGIC; | |
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124 | SIGNAL remaining_data_request : INTEGER; | |
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125 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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126 | ----------------------------------------------------------------------------- | |
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127 | ----------------------------------------------------------------------------- | |
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128 | SIGNAL header_select : STD_LOGIC; | |
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129 | ||
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130 | SIGNAL header_send : STD_LOGIC; | |
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131 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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132 | SIGNAL header_send_ok : STD_LOGIC; | |
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133 | SIGNAL header_send_ko : STD_LOGIC; | |
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134 | ||
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135 | SIGNAL component_send : STD_LOGIC; | |
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136 | SIGNAL component_send_ok : STD_LOGIC; | |
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137 | SIGNAL component_send_ko : STD_LOGIC; | |
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138 | ----------------------------------------------------------------------------- | |
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139 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
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140 | SIGNAL component_fifo_ren : STD_LOGIC; | |
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141 | ||
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142 | ----------------------------------------------------------------------------- | |
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143 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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144 | ||
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145 | BEGIN | |
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146 | ||
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147 | ----------------------------------------------------------------------------- | |
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148 | -- DMA to AHB interface | |
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149 | ----------------------------------------------------------------------------- | |
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150 | ||
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151 | DMA2AHB_1 : DMA2AHB | |
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152 | GENERIC MAP ( | |
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153 | hindex => hindex, | |
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154 | vendorid => VENDOR_LPP, | |
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155 | deviceid => 0, | |
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156 | version => 0, | |
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157 | syncrst => 1, | |
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158 | boundary => 1) -- FIX 11/01/2013 | |
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159 | PORT MAP ( | |
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160 | HCLK => HCLK, | |
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161 | HRESETn => HRESETn, | |
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162 | DMAIn => DMAIn, | |
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163 | DMAOut => DMAOut, | |
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164 | AHBIn => AHB_Master_In, | |
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165 | AHBOut => AHB_Master_Out); | |
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166 | ||
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167 | debug_reg <= debug_reg_s; | |
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168 | ||
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169 | debug_info: PROCESS (HCLK, HRESETn) | |
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170 | BEGIN -- PROCESS debug_info | |
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171 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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172 | debug_reg <= (OTHERS => '0'); | |
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173 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
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174 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); | |
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175 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; | |
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176 | IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF; | |
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177 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); | |
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178 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); | |
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179 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); | |
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180 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); | |
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181 | ||
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182 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); | |
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183 | END IF; | |
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184 | END PROCESS debug_info; | |
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185 | ||
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186 | ||
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187 | matrix_type <= header(1 DOWNTO 0); | |
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188 | component_type <= header(5 DOWNTO 2); | |
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189 | ||
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190 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
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191 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
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192 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
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193 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
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194 | '0'; | |
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195 | ||
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196 | header_check_ok <= '0' WHEN component_type = "1111" ELSE | |
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197 | '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE | |
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198 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
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199 | '0'; | |
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200 | ||
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201 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
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202 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
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203 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
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204 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
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205 | (OTHERS => '0'); | |
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206 | ||
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207 | ----------------------------------------------------------------------------- | |
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208 | -- DMA control | |
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209 | ----------------------------------------------------------------------------- | |
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210 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
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211 | BEGIN -- PROCESS DMAWriteBurst_p | |
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212 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
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213 | state <= IDLE; | |
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214 | header_ack <= '0'; | |
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215 | ready_matrix_f0_0 <= '0'; | |
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216 | ready_matrix_f0_1 <= '0'; | |
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217 | ready_matrix_f1 <= '0'; | |
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218 | ready_matrix_f2 <= '0'; | |
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219 | error_anticipating_empty_fifo <= '0'; | |
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220 | error_bad_component_error <= '0'; | |
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221 | component_type_pre <= "1110"; | |
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222 | fifo_ren_trash <= '1'; | |
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223 | component_send <= '0'; | |
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224 | address <= (OTHERS => '0'); | |
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225 | header_select <= '0'; | |
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226 | header_send <= '0'; | |
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227 | header_data <= (OTHERS => '0'); | |
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228 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
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229 | ||
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230 | CASE state IS | |
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231 | WHEN IDLE => | |
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232 | ready_matrix_f0_0 <= '0'; | |
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233 | ready_matrix_f0_1 <= '0'; | |
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234 | ready_matrix_f1 <= '0'; | |
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235 | ready_matrix_f2 <= '0'; | |
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236 | error_bad_component_error <= '0'; | |
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237 | header_select <= '1'; | |
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238 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
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239 | IF header_check_ok = '1' THEN | |
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240 | header_data <= header; | |
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241 | component_type_pre <= header(5 DOWNTO 2); | |
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242 | header_ack <= '1'; | |
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243 | -- | |
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244 | header_send <= '1'; | |
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245 | IF component_type = "0000" THEN | |
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246 | address <= address_matrix; | |
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247 | END IF; | |
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248 | header_data <= header; | |
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249 | -- | |
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250 | state <= WAIT_HEADER_ACK; | |
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251 | ELSE | |
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252 | error_bad_component_error <= '1'; | |
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253 | component_type_pre <= "1110"; | |
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254 | header_ack <= '1'; | |
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255 | state <= TRASH_FIFO; | |
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256 | END IF; | |
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257 | END IF; | |
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258 | ||
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259 | WHEN TRASH_FIFO => | |
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260 | error_bad_component_error <= '0'; | |
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261 | error_anticipating_empty_fifo <= '0'; | |
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262 | IF fifo_empty = '1' THEN | |
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263 | state <= IDLE; | |
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264 | fifo_ren_trash <= '1'; | |
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265 | ELSE | |
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266 | fifo_ren_trash <= '0'; | |
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267 | END IF; | |
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268 | ||
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269 | WHEN WAIT_HEADER_ACK => | |
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270 | header_send <= '0'; | |
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271 | IF header_send_ko = '1' THEN | |
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272 | state <= TRASH_FIFO; | |
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273 | error_anticipating_empty_fifo <= '1'; | |
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274 | -- TODO : error sending header | |
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275 | ELSIF header_send_ok = '1' THEN | |
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276 | header_select <= '0'; | |
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277 | state <= SEND_DATA; | |
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278 | address <= address + 4; | |
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279 | END IF; | |
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280 | ||
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281 | WHEN SEND_DATA => | |
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282 | IF fifo_empty = '1' THEN | |
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283 | state <= IDLE; | |
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284 | IF component_type = "1110" THEN | |
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285 | CASE matrix_type IS | |
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286 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
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287 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
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288 | WHEN "10" => ready_matrix_f1 <= '1'; | |
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289 | WHEN "11" => ready_matrix_f2 <= '1'; | |
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290 | WHEN OTHERS => NULL; | |
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291 | END CASE; | |
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292 | END IF; | |
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293 | ELSE | |
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294 | component_send <= '1'; | |
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295 | address <= address; | |
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296 | state <= WAIT_DATA_ACK; | |
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297 | END IF; | |
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298 | ||
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299 | WHEN WAIT_DATA_ACK => | |
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300 | component_send <= '0'; | |
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301 | IF component_send_ok = '1' THEN | |
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302 | address <= address + 64; | |
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303 | state <= SEND_DATA; | |
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304 | ELSIF component_send_ko = '1' THEN | |
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305 | error_anticipating_empty_fifo <= '0'; | |
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306 | state <= TRASH_FIFO; | |
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307 | END IF; | |
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308 | ||
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309 | WHEN CHECK_LENGTH => | |
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310 | state <= IDLE; | |
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311 | WHEN OTHERS => NULL; | |
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312 | END CASE; | |
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313 | ||
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314 | END IF; | |
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315 | END PROCESS DMAWriteFSM_p; | |
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316 | ||
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317 | ----------------------------------------------------------------------------- | |
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318 | -- SEND 1 word by DMA | |
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319 | ----------------------------------------------------------------------------- | |
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320 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |
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321 | PORT MAP ( | |
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322 | HCLK => HCLK, | |
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323 | HRESETn => HRESETn, | |
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324 | DMAIn => header_dmai, | |
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325 | DMAOut => DMAOut, | |
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326 | ||
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327 | send => header_send, | |
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328 | address => address, | |
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329 | data => header_data, | |
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330 | send_ok => header_send_ok, | |
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331 | send_ko => header_send_ko | |
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332 | ); | |
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333 | ||
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334 | ----------------------------------------------------------------------------- | |
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335 | -- SEND 16 word by DMA (in burst mode) | |
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336 | ----------------------------------------------------------------------------- | |
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337 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
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338 | PORT MAP ( | |
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339 | HCLK => HCLK, | |
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340 | HRESETn => HRESETn, | |
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341 | DMAIn => component_dmai, | |
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342 | DMAOut => DMAOut, | |
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343 | ||
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344 | send => component_send, | |
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345 | address => address, | |
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346 | data => fifo_data, | |
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347 | ren => component_fifo_ren, | |
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348 | send_ok => component_send_ok, | |
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349 | send_ko => component_send_ko); | |
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350 | ||
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351 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; | |
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352 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; | |
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353 | ||
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354 | END Behavioral; |
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