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Fusion avec paul
pellion -
r173:7249d1ac04a3 merge JC
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@@ -1,19 +1,21
1 1 ./amba_lcd_16x2_ctrlr
2 2 ./dsp/iir_filter
3 3 ./dsp/lpp_downsampling
4 4 ./dsp/lpp_fft
5 5 ./general_purpose
6 6 ./general_purpose/lpp_AMR
7 7 ./general_purpose/lpp_balise
8 8 ./general_purpose/lpp_delay
9 ./lfr_time_management
9 10 ./lpp_ad_Conv
10 11 ./lpp_amba
11 12 ./lpp_bootloader
12 13 ./lpp_cna
13 14 ./lpp_demux
14 15 ./lpp_dma
15 16 ./lpp_matrix
16 17 ./lpp_memory
17 18 ./lpp_top_lfr
18 19 ./lpp_uart
19 20 ./lpp_usb
21 ./lpp_waveform
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@@ -1,7 +1,7
1 lpp_dma_pkg.vhd
1 2 fifo_latency_correction.vhd
2 3 lpp_dma.vhd
3 4 lpp_dma_apbreg.vhd
4 5 lpp_dma_ip.vhd
5 lpp_dma_pkg.vhd
6 6 lpp_dma_send_16word.vhd
7 7 lpp_dma_send_1word.vhd
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@@ -1,498 +1,498
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 LIBRARY grlib;
16 16 USE grlib.amba.ALL;
17 17 USE grlib.stdlib.ALL;
18 18 USE grlib.devices.ALL;
19 19 USE GRLIB.DMA2AHB_Package.ALL;
20 20
21 21 ENTITY lpp_top_lfr_wf_picker_ip IS
22 22 GENERIC(
23 23 hindex : INTEGER := 2;
24 24 nb_burst_available_size : INTEGER := 11;
25 25 nb_snapshot_param_size : INTEGER := 11;
26 26 delta_snapshot_size : INTEGER := 16;
27 27 delta_f2_f0_size : INTEGER := 10;
28 28 delta_f2_f1_size : INTEGER := 10;
29 29 tech : INTEGER := 0
30 30 );
31 31 PORT (
32 32 -- ADS7886
33 33 cnv_run : IN STD_LOGIC;
34 34 cnv : OUT STD_LOGIC;
35 35 sck : OUT STD_LOGIC;
36 36 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
37 37 --
38 38 cnv_clk : IN STD_LOGIC;
39 39 cnv_rstn : IN STD_LOGIC;
40 40 --
41 41 clk : IN STD_LOGIC;
42 42 rstn : IN STD_LOGIC;
43 43 --
44 44 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
45 45 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
46 46 --
47 47 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
48 48 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
49 49 --
50 50 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
51 51 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
52 52 --
53 53 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
54 54 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55 55
56 56 -- AMBA AHB Master Interface
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59
60 60 coarse_time_0 : IN STD_LOGIC;
61 61
62 62 --config
63 63 data_shaping_SP0 : IN STD_LOGIC;
64 64 data_shaping_SP1 : IN STD_LOGIC;
65 65 data_shaping_R0 : IN STD_LOGIC;
66 66 data_shaping_R1 : IN STD_LOGIC;
67 67
68 68 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
69 69 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
70 70 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
71 71
72 72 enable_f0 : IN STD_LOGIC;
73 73 enable_f1 : IN STD_LOGIC;
74 74 enable_f2 : IN STD_LOGIC;
75 75 enable_f3 : IN STD_LOGIC;
76 76
77 77 burst_f0 : IN STD_LOGIC;
78 78 burst_f1 : IN STD_LOGIC;
79 79 burst_f2 : IN STD_LOGIC;
80 80
81 81 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
82 82 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
83 83 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
84 84 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 85 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 86 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
87 87
88 88 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 92 );
93 93 END lpp_top_lfr_wf_picker_ip;
94 94
95 95 ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
96 96
97 97 COMPONENT Downsampling
98 98 GENERIC (
99 99 ChanelCount : INTEGER;
100 100 SampleSize : INTEGER;
101 101 DivideParam : INTEGER);
102 102 PORT (
103 103 clk : IN STD_LOGIC;
104 104 rstn : IN STD_LOGIC;
105 105 sample_in_val : IN STD_LOGIC;
106 106 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
107 107 sample_out_val : OUT STD_LOGIC;
108 108 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
109 109 END COMPONENT;
110 110
111 111 -----------------------------------------------------------------------------
112 112 CONSTANT ChanelCount : INTEGER := 8;
113 113 CONSTANT ncycle_cnv_high : INTEGER := 79;
114 114 CONSTANT ncycle_cnv : INTEGER := 500;
115 115
116 116 -----------------------------------------------------------------------------
117 117 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
118 118 SIGNAL sample_val : STD_LOGIC;
119 119 SIGNAL sample_val_delay : STD_LOGIC;
120 120 -----------------------------------------------------------------------------
121 121 CONSTANT Coef_SZ : INTEGER := 9;
122 122 CONSTANT CoefCntPerCel : INTEGER := 6;
123 123 CONSTANT CoefPerCel : INTEGER := 5;
124 124 CONSTANT Cels_count : INTEGER := 5;
125 125
126 126 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
127 127 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
128 128 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
129 129 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
130 130 --
131 131 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
132 132 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
133 133 -----------------------------------------------------------------------------
134 134 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
135 135 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 136 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
137 137 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
138 138 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
139 139 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
140 140 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
141 141 -----------------------------------------------------------------------------
142 142 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
143 143 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
144 144 -----------------------------------------------------------------------------
145 145 SIGNAL sample_f0_val : STD_LOGIC;
146 146 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
147 147 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
148 148 --
149 149 SIGNAL sample_f1_val : STD_LOGIC;
150 150 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
151 151 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
152 152 --
153 153 SIGNAL sample_f2_val : STD_LOGIC;
154 154 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
155 155 --
156 156 SIGNAL sample_f3_val : STD_LOGIC;
157 157 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
158 158
159 159 -----------------------------------------------------------------------------
160 160 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
161 161 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
162 162 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
163 163 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
164 164 -----------------------------------------------------------------------------
165 165
166 166 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 167 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 168 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
169 169 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
170 170 BEGIN
171 171
172 172 -- component instantiation
173 173 -----------------------------------------------------------------------------
174 174 DIGITAL_acquisition : AD7688_drvr
175 175 GENERIC MAP (
176 176 ChanelCount => ChanelCount,
177 177 ncycle_cnv_high => ncycle_cnv_high,
178 178 ncycle_cnv => ncycle_cnv)
179 179 PORT MAP (
180 180 cnv_clk => cnv_clk, --
181 181 cnv_rstn => cnv_rstn, --
182 182 cnv_run => cnv_run, --
183 183 cnv => cnv, --
184 184 clk => clk, --
185 185 rstn => rstn, --
186 186 sck => sck, --
187 187 sdo => sdo(ChanelCount-1 DOWNTO 0), --
188 188 sample => sample,
189 189 sample_val => sample_val);
190 190
191 191 -----------------------------------------------------------------------------
192 192
193 193 PROCESS (clk, rstn)
194 194 BEGIN -- PROCESS
195 195 IF rstn = '0' THEN -- asynchronous reset (active low)
196 196 sample_val_delay <= '0';
197 197 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 198 sample_val_delay <= sample_val;
199 199 END IF;
200 200 END PROCESS;
201 201
202 202 -----------------------------------------------------------------------------
203 203 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
204 204 SampleLoop : FOR j IN 0 TO 15 GENERATE
205 205 sample_filter_in(i, j) <= sample(i)(j);
206 206 END GENERATE;
207 207
208 208 sample_filter_in(i, 16) <= sample(i)(15);
209 209 sample_filter_in(i, 17) <= sample(i)(15);
210 210 END GENERATE;
211 211
212 212 coefs_v2 <= CoefsInitValCst_v2;
213 213
214 214 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 215 GENERIC MAP (
216 216 tech => 0,
217 Mem_use => use_CEL, -- use_RAM
217 Mem_use => use_RAM, -- use_RAM
218 218 Sample_SZ => 18,
219 219 Coef_SZ => Coef_SZ,
220 220 Coef_Nb => 25,
221 221 Coef_sel_SZ => 5,
222 222 Cels_count => Cels_count,
223 223 ChanelsCount => ChanelCount)
224 224 PORT MAP (
225 225 rstn => rstn,
226 226 clk => clk,
227 227 virg_pos => 7,
228 228 coefs => coefs_v2,
229 229 sample_in_val => sample_val_delay,
230 230 sample_in => sample_filter_in,
231 231 sample_out_val => sample_filter_v2_out_val,
232 232 sample_out => sample_filter_v2_out);
233 233
234 234 -----------------------------------------------------------------------------
235 235 -- DATA_SHAPING
236 236 -----------------------------------------------------------------------------
237 237 all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE
238 238 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I);
239 239 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I);
240 240 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I);
241 241 END GENERATE all_data_shaping_in_loop;
242 242
243 243 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
244 244 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
245 245
246 246 PROCESS (clk, rstn)
247 247 BEGIN -- PROCESS
248 248 IF rstn = '0' THEN -- asynchronous reset (active low)
249 249 sample_data_shaping_out_val <= '0';
250 250 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
251 251 sample_data_shaping_out_val <= sample_filter_v2_out_val;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE
256 256 PROCESS (clk, rstn)
257 257 BEGIN
258 258 IF rstn = '0' THEN
259 259 sample_data_shaping_out(0,j) <= '0';
260 260 sample_data_shaping_out(1,j) <= '0';
261 261 sample_data_shaping_out(2,j) <= '0';
262 262 sample_data_shaping_out(3,j) <= '0';
263 263 sample_data_shaping_out(4,j) <= '0';
264 264 sample_data_shaping_out(5,j) <= '0';
265 265 sample_data_shaping_out(6,j) <= '0';
266 266 sample_data_shaping_out(7,j) <= '0';
267 267 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
268 268 sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j);
269 269 IF data_shaping_SP0 = '1' THEN
270 270 sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j);
271 271 ELSE
272 272 sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j);
273 273 END IF;
274 274 IF data_shaping_SP1 = '1' THEN
275 275 sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j);
276 276 ELSE
277 277 sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j);
278 278 END IF;
279 279 sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j);
280 280 sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j);
281 281 sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j);
282 282 sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j);
283 283 END IF;
284 284 END PROCESS;
285 285 END GENERATE;
286 286
287 287 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
288 288 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
289 289 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
290 290 sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j);
291 291 END GENERATE;
292 292 END GENERATE;
293 293 -----------------------------------------------------------------------------
294 294 -- F0 -- @24.576 kHz
295 295 -----------------------------------------------------------------------------
296 296 Downsampling_f0 : Downsampling
297 297 GENERIC MAP (
298 298 ChanelCount => 8,
299 299 SampleSize => 16,
300 300 DivideParam => 4)
301 301 PORT MAP (
302 302 clk => clk,
303 303 rstn => rstn,
304 304 sample_in_val => sample_filter_v2_out_val_s,
305 305 sample_in => sample_filter_v2_out_s,
306 306 sample_out_val => sample_f0_val,
307 307 sample_out => sample_f0);
308 308
309 309 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
310 310 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
311 311 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
312 312 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
313 313 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
314 314 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
315 315 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
316 316 END GENERATE all_bit_sample_f0;
317 317
318 318 sample_f0_wen <= NOT(sample_f0_val) &
319 319 NOT(sample_f0_val) &
320 320 NOT(sample_f0_val) &
321 321 NOT(sample_f0_val) &
322 322 NOT(sample_f0_val) &
323 323 NOT(sample_f0_val);
324 324
325 325 -----------------------------------------------------------------------------
326 326 -- F1 -- @4096 Hz
327 327 -----------------------------------------------------------------------------
328 328 Downsampling_f1 : Downsampling
329 329 GENERIC MAP (
330 330 ChanelCount => 8,
331 331 SampleSize => 16,
332 332 DivideParam => 6)
333 333 PORT MAP (
334 334 clk => clk,
335 335 rstn => rstn,
336 336 sample_in_val => sample_f0_val ,
337 337 sample_in => sample_f0,
338 338 sample_out_val => sample_f1_val,
339 339 sample_out => sample_f1);
340 340
341 341 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
342 342 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
343 343 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
344 344 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
345 345 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
346 346 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
347 347 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
348 348 END GENERATE all_bit_sample_f1;
349 349
350 350 sample_f1_wen <= NOT(sample_f1_val) &
351 351 NOT(sample_f1_val) &
352 352 NOT(sample_f1_val) &
353 353 NOT(sample_f1_val) &
354 354 NOT(sample_f1_val) &
355 355 NOT(sample_f1_val);
356 356
357 357 -----------------------------------------------------------------------------
358 358 -- F2 -- @256 Hz
359 359 -----------------------------------------------------------------------------
360 360 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
361 361 sample_f0_s(0, I) <= sample_f0(0, I); -- V
362 362 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
363 363 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
364 364 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
365 365 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
366 366 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
367 367 END GENERATE all_bit_sample_f0_s;
368 368
369 369 Downsampling_f2 : Downsampling
370 370 GENERIC MAP (
371 371 ChanelCount => 6,
372 372 SampleSize => 16,
373 373 DivideParam => 96)
374 374 PORT MAP (
375 375 clk => clk,
376 376 rstn => rstn,
377 377 sample_in_val => sample_f0_val ,
378 378 sample_in => sample_f0_s,
379 379 sample_out_val => sample_f2_val,
380 380 sample_out => sample_f2);
381 381
382 382 sample_f2_wen <= NOT(sample_f2_val) &
383 383 NOT(sample_f2_val) &
384 384 NOT(sample_f2_val) &
385 385 NOT(sample_f2_val) &
386 386 NOT(sample_f2_val) &
387 387 NOT(sample_f2_val);
388 388
389 389 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
390 390 sample_f2_wdata_s(I) <= sample_f2(0, I);
391 391 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
392 392 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
393 393 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
394 394 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
395 395 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
396 396 END GENERATE all_bit_sample_f2;
397 397
398 398 -----------------------------------------------------------------------------
399 399 -- F3 -- @16 Hz
400 400 -----------------------------------------------------------------------------
401 401 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
402 402 sample_f1_s(0, I) <= sample_f1(0, I); -- V
403 403 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
404 404 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
405 405 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
406 406 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
407 407 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
408 408 END GENERATE all_bit_sample_f1_s;
409 409
410 410 Downsampling_f3 : Downsampling
411 411 GENERIC MAP (
412 412 ChanelCount => 6,
413 413 SampleSize => 16,
414 414 DivideParam => 256)
415 415 PORT MAP (
416 416 clk => clk,
417 417 rstn => rstn,
418 418 sample_in_val => sample_f1_val ,
419 419 sample_in => sample_f1_s,
420 420 sample_out_val => sample_f3_val,
421 421 sample_out => sample_f3);
422 422
423 423 sample_f3_wen <= (NOT sample_f3_val) &
424 424 (NOT sample_f3_val) &
425 425 (NOT sample_f3_val) &
426 426 (NOT sample_f3_val) &
427 427 (NOT sample_f3_val) &
428 428 (NOT sample_f3_val);
429 429
430 430 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
431 431 sample_f3_wdata_s(I) <= sample_f3(0, I);
432 432 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
433 433 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
434 434 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
435 435 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
436 436 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
437 437 END GENERATE all_bit_sample_f3;
438 438
439 439 lpp_waveform_1 : lpp_waveform
440 440 GENERIC MAP (
441 441 hindex => hindex,
442 442 tech => tech,
443 443 data_size => 160,
444 444 nb_burst_available_size => nb_burst_available_size,
445 445 nb_snapshot_param_size => nb_snapshot_param_size,
446 446 delta_snapshot_size => delta_snapshot_size,
447 447 delta_f2_f0_size => delta_f2_f0_size,
448 448 delta_f2_f1_size => delta_f2_f1_size)
449 449 PORT MAP (
450 450 clk => clk,
451 451 rstn => rstn,
452 452
453 453 AHB_Master_In => AHB_Master_In,
454 454 AHB_Master_Out => AHB_Master_Out,
455 455
456 456 coarse_time_0 => coarse_time_0, -- IN
457 457 delta_snapshot => delta_snapshot, -- IN
458 458 delta_f2_f1 => delta_f2_f1, -- IN
459 459 delta_f2_f0 => delta_f2_f0, -- IN
460 460 enable_f0 => enable_f0, -- IN
461 461 enable_f1 => enable_f1, -- IN
462 462 enable_f2 => enable_f2, -- IN
463 463 enable_f3 => enable_f3, -- IN
464 464 burst_f0 => burst_f0, -- IN
465 465 burst_f1 => burst_f1, -- IN
466 466 burst_f2 => burst_f2, -- IN
467 467 nb_burst_available => nb_burst_available,
468 468 nb_snapshot_param => nb_snapshot_param,
469 469 status_full => status_full,
470 470 status_full_ack => status_full_ack, -- IN
471 471 status_full_err => status_full_err,
472 472 status_new_err => status_new_err,
473 473
474 474 addr_data_f0 => addr_data_f0, -- IN
475 475 addr_data_f1 => addr_data_f1, -- IN
476 476 addr_data_f2 => addr_data_f2, -- IN
477 477 addr_data_f3 => addr_data_f3, -- IN
478 478
479 479 data_f0_in => data_f0_in_valid,
480 480 data_f1_in => data_f1_in_valid,
481 481 data_f2_in => data_f2_in_valid,
482 482 data_f3_in => data_f3_in_valid,
483 483 data_f0_in_valid => sample_f0_val,
484 484 data_f1_in_valid => sample_f1_val,
485 485 data_f2_in_valid => sample_f2_val,
486 486 data_f3_in_valid => sample_f3_val);
487 487
488 488 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
489 489 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
490 490 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
491 491 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
492 492
493 493 sample_f0_wdata <= sample_f0_wdata_s;
494 494 sample_f1_wdata <= sample_f1_wdata_s;
495 495 sample_f2_wdata <= sample_f2_wdata_s;
496 496 sample_f3_wdata <= sample_f3_wdata_s;
497 497
498 498 END tb;
Show file before | Show file after | Hide comments
@@ -1,3 +1,4
1 lpp_top_acq.vhd
2 lpp_top_lfr.vhd
3 1 lpp_top_lfr_pkg.vhd
2 lpp_top_apbreg.vhd
3 lpp_top_lfr_wf_picker.vhd
4 lpp_top_lfr_wf_picker_ip.vhd
Show file before | Show file after | Hide comments
@@ -1,9 +1,12
1 1 lpp_waveform_pkg.vhd
2 2 lpp_waveform.vhd
3 lpp_waveform_snapshot_controler.vhd
4 lpp_waveform_snapshot.vhd
5 3 lpp_waveform_burst.vhd
6 4 lpp_waveform_dma.vhd
7 lpp_waveform_dma_send_Nword.vhd
5 lpp_waveform_dma_genvalid.vhd
8 6 lpp_waveform_dma_selectaddress.vhd
9 lpp_waveform_dma_genvalid.vhd
7 lpp_waveform_dma_send_Nword.vhd
8 lpp_waveform_fifo.vhd
9 lpp_waveform_fifo_arbiter.vhd
10 lpp_waveform_fifo_ctrl.vhd
11 lpp_waveform_snapshot.vhd
12 lpp_waveform_snapshot_controler.vhd
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