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(MINI-LFR) WFP_MS-0.1-51
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 --
200 200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202 202
203 203 BEGIN -- beh
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- CLK
207 207 -----------------------------------------------------------------------------
208 208
209 209 --PROCESS(clk_50)
210 210 --BEGIN
211 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 212 -- clk_50_s <= NOT clk_50_s;
213 213 -- END IF;
214 214 --END PROCESS;
215 215
216 216 --PROCESS(clk_50_s)
217 217 --BEGIN
218 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 219 -- clk_25 <= NOT clk_25;
220 220 -- END IF;
221 221 --END PROCESS;
222 222
223 223 --PROCESS(clk_49)
224 224 --BEGIN
225 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 226 -- clk_24 <= NOT clk_24;
227 227 -- END IF;
228 228 --END PROCESS;
229 229
230 230 --PROCESS(clk_25)
231 231 --BEGIN
232 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 233 -- rstn_25 <= reset;
234 234 -- END IF;
235 235 --END PROCESS;
236 236
237 237 PROCESS (clk_50, reset)
238 238 BEGIN -- PROCESS
239 239 IF reset = '0' THEN -- asynchronous reset (active low)
240 240 clk_50_s <= '0';
241 241 rstn_50 <= '0';
242 242 rstn_50_d1 <= '0';
243 243 rstn_50_d2 <= '0';
244 244 rstn_50_d3 <= '0';
245 245
246 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 247 clk_50_s <= NOT clk_50_s;
248 248 rstn_50_d1 <= '1';
249 249 rstn_50_d2 <= rstn_50_d1;
250 250 rstn_50_d3 <= rstn_50_d2;
251 251 rstn_50 <= rstn_50_d3;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 PROCESS (clk_50_s, rstn_50)
256 256 BEGIN -- PROCESS
257 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 258 clk_25 <= '0';
259 259 rstn_25 <= '0';
260 260 rstn_25_d1 <= '0';
261 261 rstn_25_d2 <= '0';
262 262 rstn_25_d3 <= '0';
263 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 264 clk_25 <= NOT clk_25;
265 265 rstn_25_d1 <= '1';
266 266 rstn_25_d2 <= rstn_25_d1;
267 267 rstn_25_d3 <= rstn_25_d2;
268 268 rstn_25 <= rstn_25_d3;
269 269 END IF;
270 270 END PROCESS;
271 271
272 272 PROCESS (clk_49, reset)
273 273 BEGIN -- PROCESS
274 274 IF reset = '0' THEN -- asynchronous reset (active low)
275 275 clk_24 <= '0';
276 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 277 clk_24 <= NOT clk_24;
278 278 END IF;
279 279 END PROCESS;
280 280
281 281 -----------------------------------------------------------------------------
282 282
283 283 PROCESS (clk_25, rstn_25)
284 284 BEGIN -- PROCESS
285 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 286 LED0 <= '0';
287 287 LED1 <= '0';
288 288 LED2 <= '0';
289 289 --IO1 <= '0';
290 290 --IO2 <= '1';
291 291 --IO3 <= '0';
292 292 --IO4 <= '0';
293 293 --IO5 <= '0';
294 294 --IO6 <= '0';
295 295 --IO7 <= '0';
296 296 --IO8 <= '0';
297 297 --IO9 <= '0';
298 298 --IO10 <= '0';
299 299 --IO11 <= '0';
300 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 301 LED0 <= '0';
302 302 LED1 <= '1';
303 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 --IO1 <= '1';
305 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 306 --IO3 <= ADC_SDO(0);
307 307 --IO4 <= ADC_SDO(1);
308 308 --IO5 <= ADC_SDO(2);
309 309 --IO6 <= ADC_SDO(3);
310 310 --IO7 <= ADC_SDO(4);
311 311 --IO8 <= ADC_SDO(5);
312 312 --IO9 <= ADC_SDO(6);
313 313 --IO10 <= ADC_SDO(7);
314 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 PROCESS (clk_24, rstn_25)
319 319 BEGIN -- PROCESS
320 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 321 I00_s <= '0';
322 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 323 I00_s <= NOT I00_s;
324 324 END IF;
325 325 END PROCESS;
326 326 -- IO0 <= I00_s;
327 327
328 328 --UARTs
329 329 nCTS1 <= '1';
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 333 --EXT CONNECTOR
334 334
335 335 --SPACE WIRE
336 336
337 337 leon3_soc_1 : leon3_soc
338 338 GENERIC MAP (
339 339 fabtech => apa3e,
340 340 memtech => apa3e,
341 341 padtech => inferred,
342 342 clktech => inferred,
343 343 disas => 0,
344 344 dbguart => 0,
345 345 pclow => 2,
346 346 clk_freq => 25000,
347 347 NB_CPU => 1,
348 348 ENABLE_FPU => 1,
349 349 FPU_NETLIST => 0,
350 350 ENABLE_DSU => 1,
351 351 ENABLE_AHB_UART => 1,
352 352 ENABLE_APB_UART => 1,
353 353 ENABLE_IRQMP => 1,
354 354 ENABLE_GPT => 1,
355 355 NB_AHB_MASTER => NB_AHB_MASTER,
356 356 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 357 NB_APB_SLAVE => NB_APB_SLAVE,
358 358 ADDRESS_SIZE => 20,
359 359 USES_IAP_MEMCTRLR => 0)
360 360 PORT MAP (
361 361 clk => clk_25,
362 362 reset => rstn_25,
363 363 errorn => errorn,
364 364 ahbrxd => TXD1,
365 365 ahbtxd => RXD1,
366 366 urxd1 => TXD2,
367 367 utxd1 => RXD2,
368 368 address => SRAM_A,
369 369 data => SRAM_DQ,
370 370 nSRAM_BE0 => SRAM_nBE(0),
371 371 nSRAM_BE1 => SRAM_nBE(1),
372 372 nSRAM_BE2 => SRAM_nBE(2),
373 373 nSRAM_BE3 => SRAM_nBE(3),
374 374 nSRAM_WE => SRAM_nWE,
375 375 nSRAM_CE => SRAM_CE_s,
376 376 nSRAM_OE => SRAM_nOE,
377 377 nSRAM_READY => '0',
378 378 SRAM_MBE => OPEN,
379 379 apbi_ext => apbi_ext,
380 380 apbo_ext => apbo_ext,
381 381 ahbi_s_ext => ahbi_s_ext,
382 382 ahbo_s_ext => ahbo_s_ext,
383 383 ahbi_m_ext => ahbi_m_ext,
384 384 ahbo_m_ext => ahbo_m_ext);
385 385
386 386 SRAM_CE <= SRAM_CE_s(0);
387 387 -------------------------------------------------------------------------------
388 388 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
389 389 -------------------------------------------------------------------------------
390 390 apb_lfr_management_1 : apb_lfr_management
391 391 GENERIC MAP (
392 392 pindex => 6,
393 393 paddr => 6,
394 394 pmask => 16#fff#,
395 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 397 PORT MAP (
398 398 clk25MHz => clk_25,
399 399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 400 resetn => rstn_25,
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 404 HK_sample => sample_hk,
405 405 HK_val => sample_val,
406 406 HK_sel => HK_SEL,
407 407 coarse_time => coarse_time,
408 408 fine_time => fine_time,
409 409 LFR_soft_rstn => LFR_soft_rstn
410 410 );
411 411
412 412 -----------------------------------------------------------------------
413 413 --- SpaceWire --------------------------------------------------------
414 414 -----------------------------------------------------------------------
415 415
416 416 SPW_EN <= '1';
417 417
418 418 spw_clk <= clk_50_s;
419 419 spw_rxtxclk <= spw_clk;
420 420 spw_rxclkn <= NOT spw_rxtxclk;
421 421
422 422 -- PADS for SPW1
423 423 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
424 424 PORT MAP (SPW_NOM_DIN, dtmp(0));
425 425 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
426 426 PORT MAP (SPW_NOM_SIN, stmp(0));
427 427 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
428 428 PORT MAP (SPW_NOM_DOUT, swno.d(0));
429 429 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_NOM_SOUT, swno.s(0));
431 431 -- PADS FOR SPW2
432 432 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
433 433 PORT MAP (SPW_RED_SIN, dtmp(1));
434 434 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
435 435 PORT MAP (SPW_RED_DIN, stmp(1));
436 436 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
437 437 PORT MAP (SPW_RED_DOUT, swno.d(1));
438 438 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
439 439 PORT MAP (SPW_RED_SOUT, swno.s(1));
440 440
441 441 -- GRSPW PHY
442 442 --spw1_input: if CFG_SPW_GRSPW = 1 generate
443 443 spw_inputloop : FOR j IN 0 TO 1 GENERATE
444 444 spw_phy0 : grspw_phy
445 445 GENERIC MAP(
446 446 tech => apa3e,
447 447 rxclkbuftype => 1,
448 448 scantest => 0)
449 449 PORT MAP(
450 450 rxrst => swno.rxrst,
451 451 di => dtmp(j),
452 452 si => stmp(j),
453 453 rxclko => spw_rxclk(j),
454 454 do => swni.d(j),
455 455 ndo => swni.nd(j*5+4 DOWNTO j*5),
456 456 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
457 457 END GENERATE spw_inputloop;
458 458
459 459 swni.rmapnodeaddr <= (OTHERS => '0');
460 460
461 461 -- SPW core
462 462 sw0 : grspwm GENERIC MAP(
463 463 tech => apa3e,
464 464 hindex => 1,
465 465 pindex => 5,
466 466 paddr => 5,
467 467 pirq => 11,
468 468 sysfreq => 25000, -- CPU_FREQ
469 469 rmap => 1,
470 470 rmapcrc => 1,
471 471 fifosize1 => 16,
472 472 fifosize2 => 16,
473 473 rxclkbuftype => 1,
474 474 rxunaligned => 0,
475 475 rmapbufs => 4,
476 476 ft => 0,
477 477 netlist => 0,
478 478 ports => 2,
479 479 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
480 480 memtech => apa3e,
481 481 destkey => 2,
482 482 spwcore => 1
483 483 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
484 484 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
485 485 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
486 486 )
487 487 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
488 488 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
489 489 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
490 490 swni, swno);
491 491
492 492 swni.tickin <= '0';
493 493 swni.rmapen <= '1';
494 494 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
495 495 swni.tickinraw <= '0';
496 496 swni.timein <= (OTHERS => '0');
497 497 swni.dcrstval <= (OTHERS => '0');
498 498 swni.timerrstval <= (OTHERS => '0');
499 499
500 500 -------------------------------------------------------------------------------
501 501 -- LFR ------------------------------------------------------------------------
502 502 -------------------------------------------------------------------------------
503 503
504 504
505 505 LFR_rstn <= LFR_soft_rstn AND rstn_25;
506 506 --LFR_rstn <= rstn_25;
507 507
508 508 lpp_lfr_1 : lpp_lfr
509 509 GENERIC MAP (
510 510 Mem_use => use_RAM,
511 511 nb_data_by_buffer_size => 32,
512 512 nb_snapshot_param_size => 32,
513 513 delta_vector_size => 32,
514 514 delta_vector_size_f0_2 => 7, -- log2(96)
515 515 pindex => 15,
516 516 paddr => 15,
517 517 pmask => 16#fff#,
518 518 pirq_ms => 6,
519 519 pirq_wfp => 14,
520 520 hindex => 2,
521 top_lfr_version => X"000131") -- aa.bb.cc version
521 top_lfr_version => X"000133") -- aa.bb.cc version
522 522 PORT MAP (
523 523 clk => clk_25,
524 524 rstn => LFR_rstn,
525 525 sample_B => sample_s(2 DOWNTO 0),
526 526 sample_E => sample_s(7 DOWNTO 3),
527 527 sample_val => sample_val,
528 528 apbi => apbi_ext,
529 529 apbo => apbo_ext(15),
530 530 ahbi => ahbi_m_ext,
531 531 ahbo => ahbo_m_ext(2),
532 532 coarse_time => coarse_time,
533 533 fine_time => fine_time,
534 534 data_shaping_BW => bias_fail_sw_sig,
535 535 debug_vector => lfr_debug_vector,
536 536 debug_vector_ms => lfr_debug_vector_ms
537 537 );
538 538
539 539 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
540 540 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
541 541 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
542 542 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
543 543 IO0 <= rstn_25;
544 544 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
545 545 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
546 546 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
547 547 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
548 548 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
549 549 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
550 550 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
551 551
552 552 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
553 553 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
554 554 END GENERATE all_sample;
555 555
556 556 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
557 557 GENERIC MAP(
558 558 ChannelCount => 8,
559 559 SampleNbBits => 14,
560 560 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
561 561 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
562 562 PORT MAP (
563 563 -- CONV
564 564 cnv_clk => clk_24,
565 565 cnv_rstn => rstn_25,
566 566 cnv => ADC_nCS_sig,
567 567 -- DATA
568 568 clk => clk_25,
569 569 rstn => rstn_25,
570 570 sck => ADC_CLK_sig,
571 571 sdo => ADC_SDO_sig,
572 572 -- SAMPLE
573 573 sample => sample,
574 574 sample_val => sample_val);
575 575
576 576 --IO10 <= ADC_SDO_sig(5);
577 577 --IO9 <= ADC_SDO_sig(4);
578 578 --IO8 <= ADC_SDO_sig(3);
579 579
580 580 ADC_nCS <= ADC_nCS_sig;
581 581 ADC_CLK <= ADC_CLK_sig;
582 582 ADC_SDO_sig <= ADC_SDO;
583 583
584 584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
585 585 "0010001000100010" WHEN HK_SEL = "10" ELSE
586 586 "0100010001000100" WHEN HK_SEL = "10" ELSE
587 587 (OTHERS => '0');
588 588
589 589
590 590 ----------------------------------------------------------------------
591 591 --- GPIO -----------------------------------------------------------
592 592 ----------------------------------------------------------------------
593 593
594 594 grgpio0 : grgpio
595 595 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
596 596 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
597 597
598 598 gpioi.sig_en <= (OTHERS => '0');
599 599 gpioi.sig_in <= (OTHERS => '0');
600 600 gpioi.din <= (OTHERS => '0');
601 601 --pio_pad_0 : iopad
602 602 -- GENERIC MAP (tech => CFG_PADTECH)
603 603 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
604 604 --pio_pad_1 : iopad
605 605 -- GENERIC MAP (tech => CFG_PADTECH)
606 606 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
607 607 --pio_pad_2 : iopad
608 608 -- GENERIC MAP (tech => CFG_PADTECH)
609 609 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
610 610 --pio_pad_3 : iopad
611 611 -- GENERIC MAP (tech => CFG_PADTECH)
612 612 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
613 613 --pio_pad_4 : iopad
614 614 -- GENERIC MAP (tech => CFG_PADTECH)
615 615 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
616 616 --pio_pad_5 : iopad
617 617 -- GENERIC MAP (tech => CFG_PADTECH)
618 618 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
619 619 --pio_pad_6 : iopad
620 620 -- GENERIC MAP (tech => CFG_PADTECH)
621 621 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
622 622 --pio_pad_7 : iopad
623 623 -- GENERIC MAP (tech => CFG_PADTECH)
624 624 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
625 625
626 626 PROCESS (clk_25, rstn_25)
627 627 BEGIN -- PROCESS
628 628 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
629 629 -- --IO0 <= '0';
630 630 -- IO1 <= '0';
631 631 -- IO2 <= '0';
632 632 -- IO3 <= '0';
633 633 -- IO4 <= '0';
634 634 -- IO5 <= '0';
635 635 -- IO6 <= '0';
636 636 -- IO7 <= '0';
637 637 IO8 <= '0';
638 638 IO9 <= '0';
639 639 IO10 <= '0';
640 640 IO11 <= '0';
641 641 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
642 642 CASE gpioo.dout(2 DOWNTO 0) IS
643 643 WHEN "011" =>
644 644 -- --IO0 <= observation_reg(0 );
645 645 -- IO1 <= observation_reg(1 );
646 646 -- IO2 <= observation_reg(2 );
647 647 -- IO3 <= observation_reg(3 );
648 648 -- IO4 <= observation_reg(4 );
649 649 -- IO5 <= observation_reg(5 );
650 650 -- IO6 <= observation_reg(6 );
651 651 -- IO7 <= observation_reg(7 );
652 652 IO8 <= observation_reg(8);
653 653 IO9 <= observation_reg(9);
654 654 IO10 <= observation_reg(10);
655 655 IO11 <= observation_reg(11);
656 656 WHEN "001" =>
657 657 -- --IO0 <= observation_reg(0 + 12);
658 658 -- IO1 <= observation_reg(1 + 12);
659 659 -- IO2 <= observation_reg(2 + 12);
660 660 -- IO3 <= observation_reg(3 + 12);
661 661 -- IO4 <= observation_reg(4 + 12);
662 662 -- IO5 <= observation_reg(5 + 12);
663 663 -- IO6 <= observation_reg(6 + 12);
664 664 -- IO7 <= observation_reg(7 + 12);
665 665 IO8 <= observation_reg(8 + 12);
666 666 IO9 <= observation_reg(9 + 12);
667 667 IO10 <= observation_reg(10 + 12);
668 668 IO11 <= observation_reg(11 + 12);
669 669 WHEN "010" =>
670 670 -- --IO0 <= observation_reg(0 + 12 + 12);
671 671 -- IO1 <= observation_reg(1 + 12 + 12);
672 672 -- IO2 <= observation_reg(2 + 12 + 12);
673 673 -- IO3 <= observation_reg(3 + 12 + 12);
674 674 -- IO4 <= observation_reg(4 + 12 + 12);
675 675 -- IO5 <= observation_reg(5 + 12 + 12);
676 676 -- IO6 <= observation_reg(6 + 12 + 12);
677 677 -- IO7 <= observation_reg(7 + 12 + 12);
678 678 IO8 <= '0';
679 679 IO9 <= '0';
680 680 IO10 <= '0';
681 681 IO11 <= '0';
682 682 WHEN "000" =>
683 683 -- --IO0 <= observation_vector_0(0 );
684 684 -- IO1 <= observation_vector_0(1 );
685 685 -- IO2 <= observation_vector_0(2 );
686 686 -- IO3 <= observation_vector_0(3 );
687 687 -- IO4 <= observation_vector_0(4 );
688 688 -- IO5 <= observation_vector_0(5 );
689 689 -- IO6 <= observation_vector_0(6 );
690 690 -- IO7 <= observation_vector_0(7 );
691 691 IO8 <= observation_vector_0(8);
692 692 IO9 <= observation_vector_0(9);
693 693 IO10 <= observation_vector_0(10);
694 694 IO11 <= observation_vector_0(11);
695 695 WHEN "100" =>
696 696 -- --IO0 <= observation_vector_1(0 );
697 697 -- IO1 <= observation_vector_1(1 );
698 698 -- IO2 <= observation_vector_1(2 );
699 699 -- IO3 <= observation_vector_1(3 );
700 700 -- IO4 <= observation_vector_1(4 );
701 701 -- IO5 <= observation_vector_1(5 );
702 702 -- IO6 <= observation_vector_1(6 );
703 703 -- IO7 <= observation_vector_1(7 );
704 704 IO8 <= observation_vector_1(8);
705 705 IO9 <= observation_vector_1(9);
706 706 IO10 <= observation_vector_1(10);
707 707 IO11 <= observation_vector_1(11);
708 708 WHEN OTHERS => NULL;
709 709 END CASE;
710 710
711 711 END IF;
712 712 END PROCESS;
713 713 -----------------------------------------------------------------------------
714 714 --
715 715 -----------------------------------------------------------------------------
716 716 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
717 717 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
718 718 apbo_ext(I) <= apb_none;
719 719 END GENERATE apbo_ext_not_used;
720 720 END GENERATE all_apbo_ext;
721 721
722 722
723 723 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
724 724 ahbo_s_ext(I) <= ahbs_none;
725 725 END GENERATE all_ahbo_ext;
726 726
727 727 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
728 728 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
729 729 ahbo_m_ext(I) <= ahbm_none;
730 730 END GENERATE ahbo_m_ext_not_used;
731 731 END GENERATE all_ahbo_m_ext;
732 732
733 733 END beh;
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@@ -1,53 +1,53
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 21 CLEAN=soft-clean
22 22
23 23 TECHLIBS = proasic3e
24 24
25 25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 26 tmtc openchip hynix ihp gleichmann micron usbhc
27 27
28 28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 30 ./amba_lcd_16x2_ctrlr \
31 31 ./general_purpose/lpp_AMR \
32 32 ./general_purpose/lpp_balise \
33 33 ./general_purpose/lpp_delay \
34 34 ./lpp_bootloader \
35 35 ./lpp_cna \
36 36 ./lpp_uart \
37 37 ./lpp_usb \
38 38 ./dsp/lpp_fft_rtax \
39 39 ./lpp_sim/CY7C1061DV33 \
40 40
41 41 FILESKIP =i2cmst.vhd \
42 42 APB_MULTI_DIODE.vhd \
43 43 APB_SIMPLE_DIODE.vhd \
44 44 Top_MatrixSpec.vhd \
45 45 APB_FFT.vhd \
46 46 CoreFFT_simu.vhd \
47 47 lpp_lfr_apbreg_simu.vhd
48 48
49 49 include $(GRLIB)/bin/Makefile
50 50 include $(GRLIB)/software/leon3/Makefile
51 51
52 52 ################## project specific targets ##########################
53 53
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@@ -1,258 +1,258
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.iir_filter.ALL;
32 32 USE lpp.general_purpose.ALL;
33 33
34 34 ENTITY IIR_CEL_CTRLR_v2 IS
35 35 GENERIC (
36 tech : INTEGER := apa3;
36 tech : INTEGER := 0;
37 37 Mem_use : INTEGER := use_RAM;
38 38 Sample_SZ : INTEGER := 18;
39 39 Coef_SZ : INTEGER := 9;
40 40 Coef_Nb : INTEGER := 25;
41 41 Coef_sel_SZ : INTEGER := 5;
42 42 Cels_count : INTEGER := 5;
43 43 ChanelsCount : INTEGER := 8);
44 44 PORT (
45 45 rstn : IN STD_LOGIC;
46 46 clk : IN STD_LOGIC;
47 47
48 48 virg_pos : IN INTEGER;
49 49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50 50
51 51 sample_in_val : IN STD_LOGIC;
52 52 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 53
54 54 sample_out_val : OUT STD_LOGIC;
55 55 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
56 56 END IIR_CEL_CTRLR_v2;
57 57
58 58 ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS
59 59
60 60 COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW
61 61 GENERIC (
62 62 tech : INTEGER;
63 63 Mem_use : INTEGER;
64 64 Sample_SZ : INTEGER;
65 65 Coef_SZ : INTEGER;
66 66 Coef_Nb : INTEGER;
67 67 Coef_sel_SZ : INTEGER);
68 68 PORT (
69 69 rstn : IN STD_LOGIC;
70 70 clk : IN STD_LOGIC;
71 71 virg_pos : IN INTEGER;
72 72 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
73 73 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
74 74 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
75 75 ram_write : IN STD_LOGIC;
76 76 ram_read : IN STD_LOGIC;
77 77 raddr_rst : IN STD_LOGIC;
78 78 raddr_add1 : IN STD_LOGIC;
79 79 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
80 80 alu_sel_input : IN STD_LOGIC;
81 81 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
82 82 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
83 83 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
84 84 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
85 85 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
86 86 END COMPONENT;
87 87
88 88 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
89 89 GENERIC (
90 90 Coef_sel_SZ : INTEGER;
91 91 Cels_count : INTEGER;
92 92 ChanelsCount : INTEGER);
93 93 PORT (
94 94 rstn : IN STD_LOGIC;
95 95 clk : IN STD_LOGIC;
96 96 sample_in_val : IN STD_LOGIC;
97 97 sample_in_rot : OUT STD_LOGIC;
98 98 sample_out_val : OUT STD_LOGIC;
99 99 sample_out_rot : OUT STD_LOGIC;
100 100 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 101 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 102 ram_write : OUT STD_LOGIC;
103 103 ram_read : OUT STD_LOGIC;
104 104 raddr_rst : OUT STD_LOGIC;
105 105 raddr_add1 : OUT STD_LOGIC;
106 106 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
107 107 alu_sel_input : OUT STD_LOGIC;
108 108 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
109 109 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
110 110 END COMPONENT;
111 111
112 112 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
113 113 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 114 SIGNAL ram_write : STD_LOGIC;
115 115 SIGNAL ram_read : STD_LOGIC;
116 116 SIGNAL raddr_rst : STD_LOGIC;
117 117 SIGNAL raddr_add1 : STD_LOGIC;
118 118 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 119 SIGNAL alu_sel_input : STD_LOGIC;
120 120 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
121 121 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
122 122
123 123 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
124 124 SIGNAL sample_in_rotate : STD_LOGIC;
125 125 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
126 126 SIGNAL sample_out_val_s : STD_LOGIC;
127 127 SIGNAL sample_out_val_s2 : STD_LOGIC;
128 128 SIGNAL sample_out_rot_s : STD_LOGIC;
129 129 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
130 130
131 131 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
132 132
133 133 BEGIN
134 134
135 135 IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW
136 136 GENERIC MAP (
137 137 tech => tech,
138 138 Mem_use => Mem_use,
139 139 Sample_SZ => Sample_SZ,
140 140 Coef_SZ => Coef_SZ,
141 141 Coef_Nb => Coef_Nb,
142 142 Coef_sel_SZ => Coef_sel_SZ)
143 143 PORT MAP (
144 144 rstn => rstn,
145 145 clk => clk,
146 146 virg_pos => virg_pos,
147 147 coefs => coefs,
148 148 --CTRL
149 149 in_sel_src => in_sel_src,
150 150 ram_sel_Wdata => ram_sel_Wdata,
151 151 ram_write => ram_write,
152 152 ram_read => ram_read,
153 153 raddr_rst => raddr_rst,
154 154 raddr_add1 => raddr_add1,
155 155 waddr_previous => waddr_previous,
156 156 alu_sel_input => alu_sel_input,
157 157 alu_sel_coeff => alu_sel_coeff,
158 158 alu_ctrl => alu_ctrl,
159 159 alu_comp => "00",
160 160 --DATA
161 161 sample_in => sample_in_s,
162 162 sample_out => sample_out_s);
163 163
164 164
165 165 IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
166 166 GENERIC MAP (
167 167 Coef_sel_SZ => Coef_sel_SZ,
168 168 Cels_count => Cels_count,
169 169 ChanelsCount => ChanelsCount)
170 170 PORT MAP (
171 171 rstn => rstn,
172 172 clk => clk,
173 173 sample_in_val => sample_in_val,
174 174 sample_in_rot => sample_in_rotate,
175 175 sample_out_val => sample_out_val_s,
176 176 sample_out_rot => sample_out_rot_s,
177 177
178 178 in_sel_src => in_sel_src,
179 179 ram_sel_Wdata => ram_sel_Wdata,
180 180 ram_write => ram_write,
181 181 ram_read => ram_read,
182 182 raddr_rst => raddr_rst,
183 183 raddr_add1 => raddr_add1,
184 184 waddr_previous => waddr_previous,
185 185 alu_sel_input => alu_sel_input,
186 186 alu_sel_coeff => alu_sel_coeff,
187 187 alu_ctrl => alu_ctrl);
188 188
189 189 -----------------------------------------------------------------------------
190 190 -- SAMPLE IN
191 191 -----------------------------------------------------------------------------
192 192 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
193 193
194 194 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
195 195 PROCESS (clk, rstn)
196 196 BEGIN -- PROCESS
197 197 IF rstn = '0' THEN -- asynchronous reset (active low)
198 198 sample_in_buf(I, J) <= '0';
199 199 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
200 200 IF sample_in_val = '1' THEN
201 201 sample_in_buf(I, J) <= sample_in(I, J);
202 202 ELSIF sample_in_rotate = '1' THEN
203 203 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
204 204 END IF;
205 205 END IF;
206 206 END PROCESS;
207 207 END GENERATE loop_all_chanel;
208 208
209 209 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
210 210
211 211 END GENERATE loop_all_sample;
212 212
213 213 -----------------------------------------------------------------------------
214 214 -- SAMPLE OUT
215 215 -----------------------------------------------------------------------------
216 216 PROCESS (clk, rstn)
217 217 BEGIN -- PROCESS
218 218 IF rstn = '0' THEN -- asynchronous reset (active low)
219 219 sample_out_val <= '0';
220 220 sample_out_val_s2 <= '0';
221 221 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
222 222 sample_out_val <= sample_out_val_s2;
223 223 sample_out_val_s2 <= sample_out_val_s;
224 224 END IF;
225 225 END PROCESS;
226 226
227 227 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
228 228 PROCESS (clk, rstn)
229 229 BEGIN -- PROCESS
230 230 IF rstn = '0' THEN -- asynchronous reset (active low)
231 231 sample_out_s2(ChanelsCount-1, I) <= '0';
232 232 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
233 233 IF sample_out_rot_s = '1' THEN
234 234 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
235 235 END IF;
236 236 END IF;
237 237 END PROCESS;
238 238 END GENERATE chanel_HIGH;
239 239
240 240 chanel_more : IF ChanelsCount > 1 GENERATE
241 241 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
242 242 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
243 243 PROCESS (clk, rstn)
244 244 BEGIN -- PROCESS
245 245 IF rstn = '0' THEN -- asynchronous reset (active low)
246 246 sample_out_s2(J-1, I) <= '0';
247 247 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
248 248 IF sample_out_rot_s = '1' THEN
249 249 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
250 250 END IF;
251 251 END IF;
252 252 END PROCESS;
253 253 END GENERATE all_bit;
254 254 END GENERATE all_chanel;
255 255 END GENERATE chanel_more;
256 256
257 257 sample_out <= sample_out_s2;
258 258 END ar_IIR_CEL_CTRLR_v2;
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@@ -1,419 +1,474
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.lpp_ad_conv.ALL;
29 29 USE lpp.iir_filter.ALL;
30 30 USE lpp.FILTERcfg.ALL;
31 31 USE lpp.lpp_memory.ALL;
32 32 USE lpp.lpp_waveform_pkg.ALL;
33 33 USE lpp.cic_pkg.ALL;
34 34 USE lpp.data_type_pkg.ALL;
35 USE lpp.lpp_lfr_filter_coeff.ALL;
35 36
36 37 LIBRARY techmap;
37 38 USE techmap.gencomp.ALL;
38 39
39 40 LIBRARY grlib;
40 41 USE grlib.amba.ALL;
41 42 USE grlib.stdlib.ALL;
42 43 USE grlib.devices.ALL;
43 44 USE GRLIB.DMA2AHB_Package.ALL;
44 45
45 46 ENTITY lpp_lfr_filter IS
46 47 GENERIC(
47 48 Mem_use : INTEGER := use_RAM
48 49 );
49 50 PORT (
50 51 sample : IN Samples(7 DOWNTO 0);
51 52 sample_val : IN STD_LOGIC;
52 53 --
53 54 clk : IN STD_LOGIC;
54 55 rstn : IN STD_LOGIC;
55 56 --
56 57 data_shaping_SP0 : IN STD_LOGIC;
57 58 data_shaping_SP1 : IN STD_LOGIC;
58 59 data_shaping_R0 : IN STD_LOGIC;
59 60 data_shaping_R1 : IN STD_LOGIC;
60 61 data_shaping_R2 : IN STD_LOGIC;
61 62 --
62 63 sample_f0_val : OUT STD_LOGIC;
63 64 sample_f1_val : OUT STD_LOGIC;
64 65 sample_f2_val : OUT STD_LOGIC;
65 66 sample_f3_val : OUT STD_LOGIC;
66 67 --
67 68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
71 72 );
72 73 END lpp_lfr_filter;
73 74
74 75 ARCHITECTURE tb OF lpp_lfr_filter IS
75 76
76 77 COMPONENT Downsampling
77 78 GENERIC (
78 79 ChanelCount : INTEGER;
79 80 SampleSize : INTEGER;
80 81 DivideParam : INTEGER);
81 82 PORT (
82 83 clk : IN STD_LOGIC;
83 84 rstn : IN STD_LOGIC;
84 85 sample_in_val : IN STD_LOGIC;
85 86 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
86 87 sample_out_val : OUT STD_LOGIC;
87 88 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
88 89 END COMPONENT;
89 90
90 91 -----------------------------------------------------------------------------
91 92 CONSTANT ChanelCount : INTEGER := 8;
92 93
93 94 -----------------------------------------------------------------------------
94 95 SIGNAL sample_val_delay : STD_LOGIC;
95 96 -----------------------------------------------------------------------------
96 97 CONSTANT Coef_SZ : INTEGER := 9;
97 98 CONSTANT CoefCntPerCel : INTEGER := 6;
98 99 CONSTANT CoefPerCel : INTEGER := 5;
99 100 CONSTANT Cels_count : INTEGER := 5;
100 101
101 102 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
102 103 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
103 104 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
104 105 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105 106 --
106 107 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
107 108 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
108 109 -----------------------------------------------------------------------------
109 110 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
110 111 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
111 112 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
112 113 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
113 114 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
114 115 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
115 116 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
116 117 -----------------------------------------------------------------------------
117 118 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
118 119 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
119 120 -----------------------------------------------------------------------------
120 121 -- SIGNAL sample_f0_val : STD_LOGIC;
121 122 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
122 123 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
123 124 --
124 125 -- SIGNAL sample_f1_val : STD_LOGIC;
125 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
126 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
126
127 SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
128 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
129 SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0);
127 130 --
128 131 -- SIGNAL sample_f2_val : STD_LOGIC;
129 132 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
130 133 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
131 134 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
132 135 SIGNAL sample_f2_cic_val : STD_LOGIC;
133 136
134 137 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
135 138 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
136 139 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
137 140 SIGNAL sample_f3_cic_val : STD_LOGIC;
138 141
139 142 -----------------------------------------------------------------------------
140 143 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
141 144 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
142 145 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
143 146 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
144 147 -----------------------------------------------------------------------------
145 148
146 149 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
147 150 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
148 151 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
149 152 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
150 153
151 154 SIGNAL sample_f0_val_s : STD_LOGIC;
152 155 SIGNAL sample_f1_val_s : STD_LOGIC;
156
157 -----------------------------------------------------------------------------
158 -- CONFIG FILTER IIR f0 to f1
159 -----------------------------------------------------------------------------
160 CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5;
161 CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10;
162 CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8;
163
164 CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
165 (
166 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
167 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
168 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
169 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
170 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
171 );
172 CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
173 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
174
175 CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
176 := get_IIR_CEL_FILTER_CONFIG(
177 f0_to_f1_COEFFICIENT_SIZE,
178 f0_to_f1_POINT_POSITION,
179 f0_to_f1_CEL_NUMBER,
180 f0_to_f1_sos,
181 f0_to_f1_gain);
182 -----------------------------------------------------------------------------
183
184
153 185 BEGIN
154 186
155 187 -----------------------------------------------------------------------------
156 188 PROCESS (clk, rstn)
157 189 BEGIN -- PROCESS
158 190 IF rstn = '0' THEN -- asynchronous reset (active low)
159 191 sample_val_delay <= '0';
160 192 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
161 193 sample_val_delay <= sample_val;
162 194 END IF;
163 195 END PROCESS;
164 196
165 197 -----------------------------------------------------------------------------
166 198 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
167 199 SampleLoop : FOR j IN 0 TO 15 GENERATE
168 200 sample_filter_in(i, j) <= sample(i)(j);
169 201 END GENERATE;
170 202
171 203 sample_filter_in(i, 16) <= sample(i)(15);
172 204 sample_filter_in(i, 17) <= sample(i)(15);
173 205 END GENERATE;
174 206
175 207 coefs_v2 <= CoefsInitValCst_v2;
176 208
177 209 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
178 210 GENERIC MAP (
179 211 tech => 0,
180 212 Mem_use => Mem_use, -- use_RAM
181 213 Sample_SZ => 18,
182 214 Coef_SZ => Coef_SZ,
183 215 Coef_Nb => 25,
184 216 Coef_sel_SZ => 5,
185 217 Cels_count => Cels_count,
186 218 ChanelsCount => ChanelCount)
187 219 PORT MAP (
188 220 rstn => rstn,
189 221 clk => clk,
190 222 virg_pos => 7,
191 223 coefs => coefs_v2,
192 224 sample_in_val => sample_val_delay,
193 225 sample_in => sample_filter_in,
194 226 sample_out_val => sample_filter_v2_out_val,
195 227 sample_out => sample_filter_v2_out);
196 228
197 229 -----------------------------------------------------------------------------
198 230 -- DATA_SHAPING
199 231 -----------------------------------------------------------------------------
200 232 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
201 233 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
202 234 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
203 235 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
204 236 END GENERATE all_data_shaping_in_loop;
205 237
206 238 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
207 239 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
208 240
209 241 PROCESS (clk, rstn)
210 242 BEGIN -- PROCESS
211 243 IF rstn = '0' THEN -- asynchronous reset (active low)
212 244 sample_data_shaping_out_val <= '0';
213 245 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
214 246 sample_data_shaping_out_val <= sample_filter_v2_out_val;
215 247 END IF;
216 248 END PROCESS;
217 249
218 250 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
219 251 PROCESS (clk, rstn)
220 252 BEGIN
221 253 IF rstn = '0' THEN
222 254 sample_data_shaping_out(0, j) <= '0';
223 255 sample_data_shaping_out(1, j) <= '0';
224 256 sample_data_shaping_out(2, j) <= '0';
225 257 sample_data_shaping_out(3, j) <= '0';
226 258 sample_data_shaping_out(4, j) <= '0';
227 259 sample_data_shaping_out(5, j) <= '0';
228 260 sample_data_shaping_out(6, j) <= '0';
229 261 sample_data_shaping_out(7, j) <= '0';
230 262 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
231 263 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
232 264 IF data_shaping_SP0 = '1' THEN
233 265 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
234 266 ELSE
235 267 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
236 268 END IF;
237 269 IF data_shaping_SP1 = '1' THEN
238 270 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
239 271 ELSE
240 272 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
241 273 END IF;
242 274 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
243 275 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
244 276 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
245 277 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
246 278 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
247 279 END IF;
248 280 END PROCESS;
249 281 END GENERATE;
250 282
251 283 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
252 284 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
253 285 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
254 286 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
255 287 END GENERATE;
256 288 END GENERATE;
257 289 -----------------------------------------------------------------------------
258 290 -- F0 -- @24.576 kHz
259 291 -----------------------------------------------------------------------------
292
260 293 Downsampling_f0 : Downsampling
261 294 GENERIC MAP (
262 295 ChanelCount => 8,
263 296 SampleSize => 16,
264 297 DivideParam => 4)
265 298 PORT MAP (
266 299 clk => clk,
267 300 rstn => rstn,
268 301 sample_in_val => sample_filter_v2_out_val_s,
269 302 sample_in => sample_filter_v2_out_s,
270 303 sample_out_val => sample_f0_val_s,
271 304 sample_out => sample_f0);
272 305
273 sample_f0_val <= sample_f0_val_s;
306 sample_f0_val <= sample_f0_val_s;
274 307
275 308 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
276 309 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
277 310 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
278 311 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
279 312 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
280 313 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
281 314 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
282 315 END GENERATE all_bit_sample_f0;
283 316
284 --sample_f0_wen <= NOT(sample_f0_val) &
285 -- NOT(sample_f0_val) &
286 -- NOT(sample_f0_val) &
287 -- NOT(sample_f0_val) &
288 -- NOT(sample_f0_val) &
289 -- NOT(sample_f0_val);
290
291 317 -----------------------------------------------------------------------------
292 318 -- F1 -- @4096 Hz
293 319 -----------------------------------------------------------------------------
320
321 all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
322 sample_f0_f1_s(0,I) <= sample_f0(0,I); --V
323 sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
324 sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
325 sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1
326 sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2
327 sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3
328 END GENERATE all_bit_sample_f0_f1;
329 all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
330 sample_f0_f1_s(0,I) <= sample_f0(0,15);
331 sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
332 sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
333 sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1
334 sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2
335 sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3
336 END GENERATE all_bit_sample_f0_f1_extended;
337
338
339 IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
340 GENERIC MAP (
341 tech => 0,
342 Mem_use => Mem_use, -- use_RAM
343 Sample_SZ => 18,
344 Coef_SZ => f0_to_f1_COEFFICIENT_SIZE,
345 Coef_Nb => f0_to_f1_CEL_NUMBER*5,
346 Coef_sel_SZ => 5,
347 Cels_count => f0_to_f1_CEL_NUMBER,
348 ChanelsCount => 6)
349 PORT MAP (
350 rstn => rstn,
351 clk => clk,
352 virg_pos => f0_to_f1_POINT_POSITION,
353 coefs => coefs_iir_cel_f0_to_f1,
354
355 sample_in_val => sample_f0_val_s,
356 sample_in => sample_f0_f1_s,
357
358 sample_out_val => sample_f1_val_s,
359 sample_out => sample_f1_s);
360
294 361 Downsampling_f1 : Downsampling
295 362 GENERIC MAP (
296 ChanelCount => 8,
297 SampleSize => 16,
363 ChanelCount => 6,
364 SampleSize => 18,
298 365 DivideParam => 6)
299 366 PORT MAP (
300 367 clk => clk,
301 368 rstn => rstn,
302 sample_in_val => sample_f0_val_s ,
303 sample_in => sample_f0,
304 sample_out_val => sample_f1_val_s,
305 sample_out => sample_f1);
306
307 sample_f1_val <= sample_f1_val_s;
369 sample_in_val => sample_f1_val_s,
370 sample_in => sample_f1_s,
371 sample_out_val => sample_f1_val,
372 sample_out => sample_f1);
308 373
309 374 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
310 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
311 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
312 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
313 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
314 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
315 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
375 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
376 sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
377 END GENERATE all_channel_sample_f1;
316 378 END GENERATE all_bit_sample_f1;
317 379
318 --sample_f1_wen <= NOT(sample_f1_val) &
319 -- NOT(sample_f1_val) &
320 -- NOT(sample_f1_val) &
321 -- NOT(sample_f1_val) &
322 -- NOT(sample_f1_val) &
323 -- NOT(sample_f1_val);
324
325 380 -----------------------------------------------------------------------------
326 381 -- F2 -- @256 Hz
327 382 -- F3 -- @16 Hz
328 383 -----------------------------------------------------------------------------
329 384 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
330 385 sample_f0_s(0, I) <= sample_f0(0, I); -- V
331 386 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
332 387 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
333 388 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
334 389 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
335 390 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
336 391 END GENERATE all_bit_sample_f0_s;
337 392
338 393
339 394 cic_lfr_1: cic_lfr
340 395 GENERIC MAP (
341 396 tech => 0,
342 397 use_RAM_nCEL => Mem_use)
343 398 PORT MAP (
344 399 clk => clk,
345 400 rstn => rstn,
346 401 run => '1',
347 402
348 403 data_in => sample_f0_s,
349 404 data_in_valid => sample_f0_val_s,
350 405
351 406 data_out_16 => sample_f2_cic,
352 407 data_out_16_valid => sample_f2_cic_val,
353 408
354 409 data_out_256 => sample_f3_cic,
355 410 data_out_256_valid => sample_f3_cic_val);
356 411
357 412 -----------------------------------------------------------------------------
358 413
359 414 all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE
360 415 all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE
361 416 sample_f2_cic_s(J,I) <= sample_f2_cic(J,I);
362 417 END GENERATE all_channel_sample_f2_cic;
363 418 END GENERATE all_bit_sample_f2_cic;
364 419
365 420 Downsampling_f2 : Downsampling
366 421 GENERIC MAP (
367 422 ChanelCount => 6,
368 423 SampleSize => 16,
369 424 DivideParam => 6)
370 425 PORT MAP (
371 426 clk => clk,
372 427 rstn => rstn,
373 428 sample_in_val => sample_f2_cic_val ,
374 429 sample_in => sample_f2_cic_s,
375 430 sample_out_val => sample_f2_val,
376 431 sample_out => sample_f2);
377 432
378 433 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
379 434 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
380 435 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
381 436 END GENERATE all_channel_sample_f2;
382 437 END GENERATE all_bit_sample_f2;
383 438
384 439 -----------------------------------------------------------------------------
385 440
386 441 all_bit_sample_f3_cic : FOR I IN 15 DOWNTO 0 GENERATE
387 442 all_channel_sample_f3_cic : FOR J IN 5 DOWNTO 0 GENERATE
388 443 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
389 444 END GENERATE all_channel_sample_f3_cic;
390 445 END GENERATE all_bit_sample_f3_cic;
391 446
392 447 Downsampling_f3 : Downsampling
393 448 GENERIC MAP (
394 449 ChanelCount => 6,
395 450 SampleSize => 16,
396 451 DivideParam => 6)
397 452 PORT MAP (
398 453 clk => clk,
399 454 rstn => rstn,
400 455 sample_in_val => sample_f3_cic_val ,
401 456 sample_in => sample_f3_cic_s,
402 457 sample_out_val => sample_f3_val,
403 458 sample_out => sample_f3);
404 459
405 460 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
406 461 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
407 462 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
408 463 END GENERATE all_channel_sample_f3;
409 464 END GENERATE all_bit_sample_f3;
410 465
411 466 -----------------------------------------------------------------------------
412 467 --
413 468 -----------------------------------------------------------------------------
414 469 sample_f0_wdata <= sample_f0_wdata_s;
415 470 sample_f1_wdata <= sample_f1_wdata_s;
416 471 sample_f2_wdata <= sample_f2_wdata_s;
417 472 sample_f3_wdata <= sample_f3_wdata_s;
418 473
419 474 END tb;
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@@ -1,11 +1,12
1 1 lpp_top_lfr_pkg.vhd
2 2 lpp_lfr_pkg.vhd
3 3 lpp_lfr_apbreg_pkg.vhd
4 lpp_lfr_filter_coeff.vhd
4 5 lpp_lfr_filter.vhd
5 6 lpp_lfr_apbreg.vhd
6 7 lpp_lfr_apbreg_ms_pointer.vhd
7 8 lpp_lfr_ms_fsmdma.vhd
8 9 lpp_lfr_ms_FFT.vhd
9 10 lpp_lfr_ms.vhd
10 11 lpp_lfr_ms_reg_head.vhd
11 12 lpp_lfr.vhd
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