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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library gaisler;
25 25 use gaisler.misc.all;
26 26 use gaisler.memctrl.all;
27 27 library techmap;
28 28 use techmap.gencomp.all;
29 29 use techmap.allclkgen.all;
30 30
31 31
32 32
33 33
34 34 entity ssram_plugin is
35 35 generic (tech : integer := 0);
36 36 port
37 37 (
38 38 clk : in std_logic;
39 39 mem_ctrlr_o : in memory_out_type;
40 40 SSRAM_CLK : out std_logic;
41 41 nBWa : out std_logic;
42 42 nBWb : out std_logic;
43 43 nBWc : out std_logic;
44 44 nBWd : out std_logic;
45 45 nBWE : out std_logic;
46 46 nADSC : out std_logic;
47 47 nADSP : out std_logic;
48 48 nADV : out std_logic;
49 49 nGW : out std_logic;
50 50 nCE1 : out std_logic;
51 51 CE2 : out std_logic;
52 52 nCE3 : out std_logic;
53 53 nOE : out std_logic;
54 54 MODE : out std_logic;
55 55 ZZ : out std_logic
56 56 );
57 57 end entity;
58 58
59 59
60 60
61 61
62 62
63 63
64 64 architecture ar_ssram_plugin of ssram_plugin is
65 65
66 66
67 67 signal nADSPint : std_logic:='1';
68 68 signal nOEint : std_logic:='1';
69 69 signal RAMSN_reg: std_logic:='1';
70 70 signal OEreg : std_logic:='1';
71 71 signal nBWaint : std_logic:='1';
72 72 signal nBWbint : std_logic:='1';
73 73 signal nBWcint : std_logic:='1';
74 74 signal nBWdint : std_logic:='1';
75 75 signal nBWEint : std_logic:='1';
76 76 signal nCE1int : std_logic:='1';
77 77 signal CE2int : std_logic:='0';
78 78 signal nCE3int : std_logic:='1';
79 79
80 80 Type stateT is (idle,st1,st2,st3,st4);
81 81 signal state : stateT;
82 82
83 SIGNAL nclk : STD_LOGIC;
84
85 83 begin
86 84
87 85 process(clk , mem_ctrlr_o.RAMSN(0))
88 86 begin
89 87 if mem_ctrlr_o.RAMSN(0) ='1' then
90 88 state <= idle;
91 89 elsif clk ='1' and clk'event then
92 90 case state is
93 91 when idle =>
94 92 state <= st1;
95 93 when st1 =>
96 94 state <= st2;
97 95 when st2 =>
98 96 state <= st3;
99 97 when st3 =>
100 98 state <= st4;
101 99 when st4 =>
102 100 state <= st1;
103 101 end case;
104 102 end if;
105 103 end process;
106 104
107 nclk <= NOT clk;
108 105 ssram_clk_pad : outpad generic map (tech => tech)
109 port map (SSRAM_CLK,nclk);
106 port map (SSRAM_CLK,not clk);
110 107
111 108
112 109 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
113 110 nBWa_pad : outpad generic map (tech => tech)
114 111 port map (nBWa,nBWaint);
115 112
116 113 nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
117 114 nBWb_pad : outpad generic map (tech => tech)
118 115 port map (nBWb, nBWbint);
119 116
120 117 nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
121 118 nBWc_pad : outpad generic map (tech => tech)
122 119 port map (nBWc, nBWcint);
123 120
124 121 nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
125 122 nBWd_pad : outpad generic map (tech => tech)
126 123 port map (nBWd, nBWdint);
127 124
128 125 nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
129 126 nBWE_pad : outpad generic map (tech => tech)
130 127 port map (nBWE, nBWEint);
131 128
132 129 nADSC_pad : outpad generic map (tech => tech)
133 130 port map (nADSC, '1');
134 131
135 132 --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
136 133 nADSPint <= '0' when state = st1 else '1';
137 134
138 135 process(clk)
139 136 begin
140 137 if clk'event and clk = '1' then
141 138 RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
142 139 end if;
143 140 end process;
144 141
145 142 nADSP_pad : outpad generic map (tech => tech)
146 143 port map (nADSP, nADSPint);
147 144
148 145 nADV_pad : outpad generic map (tech => tech)
149 146 port map (nADV, '1');
150 147
151 148 nGW_pad : outpad generic map (tech => tech)
152 149 port map (nGW, '1');
153 150
154 151 nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28);
155 152 CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24));
156 153 nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20);
157 154
158 155 nCE1_pad : outpad generic map (tech => tech)
159 156 port map (nCE1, nCE1int);
160 157
161 158 CE2_pad : outpad generic map (tech => tech)
162 159 port map (CE2, CE2int);
163 160
164 161 nCE3_pad : outpad generic map (tech => tech)
165 162 port map (nCE3, nCE3int);
166 163
167 164 nOE_pad : outpad generic map (tech => tech)
168 165 port map (nOE, nOEint);
169 166
170 167 process(clk)
171 168 begin
172 169 if clk'event and clk = '1' then
173 170 OEreg <= mem_ctrlr_o.OEN;
174 171 end if;
175 172 end process;
176 173
177 174
178 175 --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
179 176 nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1';
180 177
181 178 MODE_pad : outpad generic map (tech => tech)
182 179 port map (MODE, '0');
183 180
184 181 ZZ_pad : outpad generic map (tech => tech)
185 182 port map (ZZ, '0');
186 183
187 end architecture;
184 end architecture; No newline at end of file
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