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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library gaisler;
24 library gaisler;
25 use gaisler.misc.all;
25 use gaisler.misc.all;
26 use gaisler.memctrl.all;
26 use gaisler.memctrl.all;
27 library techmap;
27 library techmap;
28 use techmap.gencomp.all;
28 use techmap.gencomp.all;
29 use techmap.allclkgen.all;
29 use techmap.allclkgen.all;
30
30
31
31
32
32
33
33
34 entity ssram_plugin is
34 entity ssram_plugin is
35 generic (tech : integer := 0);
35 generic (tech : integer := 0);
36 port
36 port
37 (
37 (
38 clk : in std_logic;
38 clk : in std_logic;
39 mem_ctrlr_o : in memory_out_type;
39 mem_ctrlr_o : in memory_out_type;
40 SSRAM_CLK : out std_logic;
40 SSRAM_CLK : out std_logic;
41 nBWa : out std_logic;
41 nBWa : out std_logic;
42 nBWb : out std_logic;
42 nBWb : out std_logic;
43 nBWc : out std_logic;
43 nBWc : out std_logic;
44 nBWd : out std_logic;
44 nBWd : out std_logic;
45 nBWE : out std_logic;
45 nBWE : out std_logic;
46 nADSC : out std_logic;
46 nADSC : out std_logic;
47 nADSP : out std_logic;
47 nADSP : out std_logic;
48 nADV : out std_logic;
48 nADV : out std_logic;
49 nGW : out std_logic;
49 nGW : out std_logic;
50 nCE1 : out std_logic;
50 nCE1 : out std_logic;
51 CE2 : out std_logic;
51 CE2 : out std_logic;
52 nCE3 : out std_logic;
52 nCE3 : out std_logic;
53 nOE : out std_logic;
53 nOE : out std_logic;
54 MODE : out std_logic;
54 MODE : out std_logic;
55 ZZ : out std_logic
55 ZZ : out std_logic
56 );
56 );
57 end entity;
57 end entity;
58
58
59
59
60
60
61
61
62
62
63
63
64 architecture ar_ssram_plugin of ssram_plugin is
64 architecture ar_ssram_plugin of ssram_plugin is
65
65
66
66
67 signal nADSPint : std_logic:='1';
67 signal nADSPint : std_logic:='1';
68 signal nOEint : std_logic:='1';
68 signal nOEint : std_logic:='1';
69 signal RAMSN_reg: std_logic:='1';
69 signal RAMSN_reg: std_logic:='1';
70 signal OEreg : std_logic:='1';
70 signal OEreg : std_logic:='1';
71 signal nBWaint : std_logic:='1';
71 signal nBWaint : std_logic:='1';
72 signal nBWbint : std_logic:='1';
72 signal nBWbint : std_logic:='1';
73 signal nBWcint : std_logic:='1';
73 signal nBWcint : std_logic:='1';
74 signal nBWdint : std_logic:='1';
74 signal nBWdint : std_logic:='1';
75 signal nBWEint : std_logic:='1';
75 signal nBWEint : std_logic:='1';
76 signal nCE1int : std_logic:='1';
76 signal nCE1int : std_logic:='1';
77 signal CE2int : std_logic:='0';
77 signal CE2int : std_logic:='0';
78 signal nCE3int : std_logic:='1';
78 signal nCE3int : std_logic:='1';
79
79
80 Type stateT is (idle,st1,st2,st3,st4);
80 Type stateT is (idle,st1,st2,st3,st4);
81 signal state : stateT;
81 signal state : stateT;
82
82
83 SIGNAL nclk : STD_LOGIC;
84
85 begin
83 begin
86
84
87 process(clk , mem_ctrlr_o.RAMSN(0))
85 process(clk , mem_ctrlr_o.RAMSN(0))
88 begin
86 begin
89 if mem_ctrlr_o.RAMSN(0) ='1' then
87 if mem_ctrlr_o.RAMSN(0) ='1' then
90 state <= idle;
88 state <= idle;
91 elsif clk ='1' and clk'event then
89 elsif clk ='1' and clk'event then
92 case state is
90 case state is
93 when idle =>
91 when idle =>
94 state <= st1;
92 state <= st1;
95 when st1 =>
93 when st1 =>
96 state <= st2;
94 state <= st2;
97 when st2 =>
95 when st2 =>
98 state <= st3;
96 state <= st3;
99 when st3 =>
97 when st3 =>
100 state <= st4;
98 state <= st4;
101 when st4 =>
99 when st4 =>
102 state <= st1;
100 state <= st1;
103 end case;
101 end case;
104 end if;
102 end if;
105 end process;
103 end process;
106
104
107 nclk <= NOT clk;
108 ssram_clk_pad : outpad generic map (tech => tech)
105 ssram_clk_pad : outpad generic map (tech => tech)
109 port map (SSRAM_CLK,nclk);
106 port map (SSRAM_CLK,not clk);
110
107
111
108
112 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
109 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
113 nBWa_pad : outpad generic map (tech => tech)
110 nBWa_pad : outpad generic map (tech => tech)
114 port map (nBWa,nBWaint);
111 port map (nBWa,nBWaint);
115
112
116 nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
113 nBWbint <= mem_ctrlr_o.WRN(2)or mem_ctrlr_o.ramsn(0);
117 nBWb_pad : outpad generic map (tech => tech)
114 nBWb_pad : outpad generic map (tech => tech)
118 port map (nBWb, nBWbint);
115 port map (nBWb, nBWbint);
119
116
120 nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
117 nBWcint <= mem_ctrlr_o.WRN(1)or mem_ctrlr_o.ramsn(0);
121 nBWc_pad : outpad generic map (tech => tech)
118 nBWc_pad : outpad generic map (tech => tech)
122 port map (nBWc, nBWcint);
119 port map (nBWc, nBWcint);
123
120
124 nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
121 nBWdint <= mem_ctrlr_o.WRN(0)or mem_ctrlr_o.ramsn(0);
125 nBWd_pad : outpad generic map (tech => tech)
122 nBWd_pad : outpad generic map (tech => tech)
126 port map (nBWd, nBWdint);
123 port map (nBWd, nBWdint);
127
124
128 nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
125 nBWEint <= mem_ctrlr_o.WRITEN or mem_ctrlr_o.ramsn(0);
129 nBWE_pad : outpad generic map (tech => tech)
126 nBWE_pad : outpad generic map (tech => tech)
130 port map (nBWE, nBWEint);
127 port map (nBWE, nBWEint);
131
128
132 nADSC_pad : outpad generic map (tech => tech)
129 nADSC_pad : outpad generic map (tech => tech)
133 port map (nADSC, '1');
130 port map (nADSC, '1');
134
131
135 --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
132 --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
136 nADSPint <= '0' when state = st1 else '1';
133 nADSPint <= '0' when state = st1 else '1';
137
134
138 process(clk)
135 process(clk)
139 begin
136 begin
140 if clk'event and clk = '1' then
137 if clk'event and clk = '1' then
141 RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
138 RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
142 end if;
139 end if;
143 end process;
140 end process;
144
141
145 nADSP_pad : outpad generic map (tech => tech)
142 nADSP_pad : outpad generic map (tech => tech)
146 port map (nADSP, nADSPint);
143 port map (nADSP, nADSPint);
147
144
148 nADV_pad : outpad generic map (tech => tech)
145 nADV_pad : outpad generic map (tech => tech)
149 port map (nADV, '1');
146 port map (nADV, '1');
150
147
151 nGW_pad : outpad generic map (tech => tech)
148 nGW_pad : outpad generic map (tech => tech)
152 port map (nGW, '1');
149 port map (nGW, '1');
153
150
154 nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28);
151 nCE1int <= nADSPint or mem_ctrlr_o.address(31) or (not mem_ctrlr_o.address(30)) or mem_ctrlr_o.address(29) or mem_ctrlr_o.address(28);
155 CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24));
152 CE2int <= (not mem_ctrlr_o.address(27)) and (not mem_ctrlr_o.address(26)) and (not mem_ctrlr_o.address(25)) and (not mem_ctrlr_o.address(24));
156 nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20);
153 nCE3int <= mem_ctrlr_o.address(23) or mem_ctrlr_o.address(22) or mem_ctrlr_o.address(21) or mem_ctrlr_o.address(20);
157
154
158 nCE1_pad : outpad generic map (tech => tech)
155 nCE1_pad : outpad generic map (tech => tech)
159 port map (nCE1, nCE1int);
156 port map (nCE1, nCE1int);
160
157
161 CE2_pad : outpad generic map (tech => tech)
158 CE2_pad : outpad generic map (tech => tech)
162 port map (CE2, CE2int);
159 port map (CE2, CE2int);
163
160
164 nCE3_pad : outpad generic map (tech => tech)
161 nCE3_pad : outpad generic map (tech => tech)
165 port map (nCE3, nCE3int);
162 port map (nCE3, nCE3int);
166
163
167 nOE_pad : outpad generic map (tech => tech)
164 nOE_pad : outpad generic map (tech => tech)
168 port map (nOE, nOEint);
165 port map (nOE, nOEint);
169
166
170 process(clk)
167 process(clk)
171 begin
168 begin
172 if clk'event and clk = '1' then
169 if clk'event and clk = '1' then
173 OEreg <= mem_ctrlr_o.OEN;
170 OEreg <= mem_ctrlr_o.OEN;
174 end if;
171 end if;
175 end process;
172 end process;
176
173
177
174
178 --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
175 --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
179 nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1';
176 nOEint <= '0' when state = st2 or state = st3 or state = st4 else '1';
180
177
181 MODE_pad : outpad generic map (tech => tech)
178 MODE_pad : outpad generic map (tech => tech)
182 port map (MODE, '0');
179 port map (MODE, '0');
183
180
184 ZZ_pad : outpad generic map (tech => tech)
181 ZZ_pad : outpad generic map (tech => tech)
185 port map (ZZ, '0');
182 port map (ZZ, '0');
186
183
187 end architecture;
184 end architecture; No newline at end of file
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