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Updated MINI-LFR Board and design with EM constraint files.
Jeandet Alexis -
r635:6428e5d35e0a simu_with_Leon3
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
42 set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
43 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
44 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
45 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
47 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
48 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
49 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
61 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
62 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
63 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
65 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
66 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
67 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
71 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
72 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
73 address[7] SRAM_A[8] SRAM_A[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
75 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
76 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
77 address[7] SRAM_A[8] SRAM_A[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
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@@ -1,639 +1,639
1 # Actel Physical design constraints file
1 ο»Ώ# Actel Physical design constraints file
2 2 # Generated file
3 3
4 4 # Version: 9.1 SP3 9.1.3.4
5 5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 6 # Date generated: Tue Oct 18 08:21:45 2011
7 7
8 8
9 9 #
10 10 # IO banks setting
11 11 #
12 12
13 13
14 14 #
15 15 # I/O constraints
16 16 #
17 17
18 set_io clk_50 \
18 set_io clk100MHz \
19 19 -pinname F7 \
20 20 -fixed yes \
21 21 -DIRECTION Inout
22 22
23 set_io clk_49 \
23 set_io clk49_152MHz \
24 24 -pinname K14 \
25 25 -fixed yes \
26 26 -DIRECTION Inout
27 27
28 28 set_io reset \
29 29 -pinname T2 \
30 30 -fixed yes \
31 31 -DIRECTION Inout
32 32 #====================================================================
33 33 # BPs
34 34 #====================================================================
35 35 set_io BP0 \
36 36 -pinname L1 \
37 37 -fixed yes \
38 38 -DIRECTION Inout
39 39
40 40 set_io BP1 \
41 41 -pinname R1 \
42 42 -fixed yes \
43 43 -DIRECTION Inout
44 44
45 45 #====================================================================
46 46 # LEDs
47 47 #====================================================================
48 48
49 49 set_io LED0 \
50 50 -pinname V6 \
51 51 -fixed yes \
52 52 -DIRECTION Inout
53 53
54 54 set_io LED1 \
55 55 -pinname V5 \
56 56 -fixed yes \
57 57 -DIRECTION Inout
58 58
59 59 set_io LED2 \
60 60 -pinname T4 \
61 61 -fixed yes \
62 62 -DIRECTION Inout
63 63
64 64 #====================================================================
65 65 # UARTS
66 66 #====================================================================
67 67
68 68 set_io TXD1 \
69 69 -pinname N17 \
70 70 -fixed yes \
71 71 -DIRECTION Inout
72 72
73 73 set_io RXD1 \
74 74 -pinname N18 \
75 75 -fixed yes \
76 76 -DIRECTION Inout
77 77
78 78 set_io nCTS1 \
79 79 -pinname P18 \
80 80 -fixed yes \
81 81 -DIRECTION Inout
82 82
83 83 set_io nRTS1 \
84 84 -pinname P17 \
85 85 -fixed yes \
86 86 -DIRECTION Inout
87 87
88 88
89 89 set_io TXD2 \
90 90 -pinname P13 \
91 91 -fixed yes \
92 92 -DIRECTION Inout
93 93
94 94 set_io RXD2 \
95 95 -pinname T18 \
96 96 -fixed yes \
97 97 -DIRECTION Inout
98 98
99 99 set_io nCTS2 \
100 100 -pinname V17 \
101 101 -fixed yes \
102 102 -DIRECTION Inout
103 103
104 104 set_io nDTR2 \
105 105 -pinname L15 \
106 106 -fixed yes \
107 107 -DIRECTION Inout
108 108
109 109 set_io nRTS2 \
110 110 -pinname M15 \
111 111 -fixed yes \
112 112 -DIRECTION Inout
113 113
114 114 set_io nDCD2 \
115 115 -pinname N15 \
116 116 -fixed yes \
117 117 -DIRECTION Inout
118 118
119 119
120 120 #====================================================================
121 121 # EXT CONNECTOR
122 122 #====================================================================
123 123
124 124 set_io IO0 \
125 125 -pinname E4 \
126 126 -fixed yes \
127 127 -DIRECTION Inout
128 128
129 129 set_io IO1 \
130 130 -pinname D3 \
131 131 -fixed yes \
132 132 -DIRECTION Inout
133 133
134 134 set_io IO2 \
135 135 -pinname C2 \
136 136 -fixed yes \
137 137 -DIRECTION Inout
138 138
139 139 set_io IO3 \
140 140 -pinname D1 \
141 141 -fixed yes \
142 142 -DIRECTION Inout
143 143
144 144 set_io IO4 \
145 145 -pinname F2 \
146 146 -fixed yes \
147 147 -DIRECTION Inout
148 148
149 149 set_io IO5 \
150 150 -pinname F3 \
151 151 -fixed yes \
152 152 -DIRECTION Inout
153 153
154 154 set_io IO6 \
155 155 -pinname G2 \
156 156 -fixed yes \
157 157 -DIRECTION Inout
158 158
159 159 set_io IO7 \
160 160 -pinname H3 \
161 161 -fixed yes \
162 162 -DIRECTION Inout
163 163
164 164 set_io IO8 \
165 165 -pinname H4 \
166 166 -fixed yes \
167 167 -DIRECTION Inout
168 168
169 169 set_io IO9 \
170 170 -pinname J2 \
171 171 -fixed yes \
172 172 -DIRECTION Inout
173 173
174 174 set_io IO10 \
175 175 -pinname P1 \
176 176 -fixed yes \
177 177 -DIRECTION Inout
178 178
179 179 set_io IO11 \
180 180 -pinname N1 \
181 181 -fixed yes \
182 182 -DIRECTION Inout
183 183
184 184 #====================================================================
185 185 # SPACE WIRE
186 186 #====================================================================
187 187
188 188 set_io SPW_EN \
189 189 -pinname R12 \
190 190 -fixed yes \
191 191 -DIRECTION Inout
192 192
193 193 #================================
194 194 # NOMINAL LINK
195 195 #================================
196 196
197 197 set_io SPW_NOM_DIN \
198 198 -pinname R10 \
199 199 -fixed yes \
200 200 -DIRECTION Inout
201 201
202 202 set_io SPW_NOM_SIN \
203 203 -pinname R13 \
204 204 -fixed yes \
205 205 -DIRECTION Inout
206 206
207 207 set_io SPW_NOM_DOUT \
208 208 -pinname T13 \
209 209 -fixed yes \
210 210 -DIRECTION Inout
211 211
212 212 set_io SPW_NOM_SOUT \
213 213 -pinname T10 \
214 214 -fixed yes \
215 215 -DIRECTION Inout
216 216
217 217 #================================
218 218 # REDUNDANT LINK
219 219 #================================
220 220
221 221 set_io SPW_RED_DIN \
222 222 -pinname U18 \
223 223 -fixed yes \
224 224 -DIRECTION Inout
225 225
226 226 set_io SPW_RED_SIN \
227 227 -pinname T12 \
228 228 -fixed yes \
229 229 -DIRECTION Inout
230 230
231 231 set_io SPW_RED_DOUT \
232 232 -pinname U10 \
233 233 -fixed yes \
234 234 -DIRECTION Inout
235 235
236 236 set_io SPW_RED_SOUT \
237 237 -pinname P16 \
238 238 -fixed yes \
239 239 -DIRECTION Inout
240 240
241 241 #====================================================================
242 242 # MINI LFR ADC INPUTS
243 243 #====================================================================
244 244
245 245 set_io ADC_nCS \
246 246 -pinname K1 \
247 247 -fixed yes \
248 248 -DIRECTION Inout
249 249
250 250 set_io ADC_CLK \
251 251 -pinname T1 \
252 252 -fixed yes \
253 253 -DIRECTION Inout
254 254
255 255
256 256 #================================
257 257 # ADC DATA
258 258 #================================
259 259
260 260 set_io ADC_SDO\[0\] \
261 261 -pinname V4 \
262 262 -fixed yes \
263 263 -DIRECTION Inout
264 264
265 265 set_io ADC_SDO\[1\] \
266 266 -pinname V3 \
267 267 -fixed yes \
268 268 -DIRECTION Inout
269 269
270 270 set_io ADC_SDO\[2\] \
271 271 -pinname V2 \
272 272 -fixed yes \
273 273 -DIRECTION Inout
274 274
275 275 set_io ADC_SDO\[3\] \
276 276 -pinname U1 \
277 277 -fixed yes \
278 278 -DIRECTION Inout
279 279
280 280 set_io ADC_SDO\[4\] \
281 281 -pinname J1 \
282 282 -fixed yes \
283 283 -DIRECTION Inout
284 284
285 285 set_io ADC_SDO\[5\] \
286 286 -pinname H1 \
287 287 -fixed yes \
288 288 -DIRECTION Inout
289 289
290 290 set_io ADC_SDO\[6\] \
291 291 -pinname F1 \
292 292 -fixed yes \
293 293 -DIRECTION Inout
294 294
295 295 set_io ADC_SDO\[7\] \
296 296 -pinname E1 \
297 297 -fixed yes \
298 298 -DIRECTION Inout
299 299
300 300
301 301 #====================================================================
302 302 # SRAM
303 303 #====================================================================
304 304
305 305 #================================
306 306 # SRAM CTRL
307 307 #================================
308 308
309 309 set_io SRAM_nWE \
310 310 -pinname C13 \
311 311 -fixed yes \
312 312 -DIRECTION Inout
313 313
314 314 set_io SRAM_CE \
315 315 -pinname J14 \
316 316 -fixed yes \
317 317 -DIRECTION Inout
318 318
319 319 set_io SRAM_nOE \
320 320 -pinname B9 \
321 321 -fixed yes \
322 322 -DIRECTION Inout
323 323
324 324 set_io SRAM_nBE\[0\] \
325 325 -pinname H15 \
326 326 -fixed yes \
327 327 -DIRECTION Inout
328 328
329 329 set_io SRAM_nBE\[1\] \
330 330 -pinname C12 \
331 331 -fixed yes \
332 332 -DIRECTION Inout
333 333
334 334 set_io SRAM_nBE\[2\] \
335 335 -pinname A10 \
336 336 -fixed yes \
337 337 -DIRECTION Inout
338 338
339 339 set_io SRAM_nBE\[3\] \
340 340 -pinname A9 \
341 341 -fixed yes \
342 342 -DIRECTION Inout
343 343
344 344
345 345 #================================
346 346 # SRAM ADDRESS
347 347 #================================
348 348
349 349 set_io SRAM_A\[0\] \
350 350 -pinname C11 \
351 351 -fixed yes \
352 352 -DIRECTION Inout
353 353
354 354 set_io SRAM_A\[1\] \
355 355 -pinname C10 \
356 356 -fixed yes \
357 357 -DIRECTION Inout
358 358
359 359 set_io SRAM_A\[2\] \
360 360 -pinname C9 \
361 361 -fixed yes \
362 362 -DIRECTION Inout
363 363
364 364 set_io SRAM_A\[3\] \
365 365 -pinname C8 \
366 366 -fixed yes \
367 367 -DIRECTION Inout
368 368
369 369 set_io SRAM_A\[4\] \
370 370 -pinname C7 \
371 371 -fixed yes \
372 372 -DIRECTION Inout
373 373
374 374 set_io SRAM_A\[5\] \
375 375 -pinname A5 \
376 376 -fixed yes \
377 377 -DIRECTION Inout
378 378
379 379 set_io SRAM_A\[6\] \
380 380 -pinname A6 \
381 381 -fixed yes \
382 382 -DIRECTION Inout
383 383
384 384 set_io SRAM_A\[7\] \
385 385 -pinname B6 \
386 386 -fixed yes \
387 387 -DIRECTION Inout
388 388
389 389 set_io SRAM_A\[8\] \
390 390 -pinname B7 \
391 391 -fixed yes \
392 392 -DIRECTION Inout
393 393
394 394 set_io SRAM_A\[9\] \
395 395 -pinname A8 \
396 396 -fixed yes \
397 397 -DIRECTION Inout
398 398
399 399 set_io SRAM_A\[10\] \
400 400 -pinname B10 \
401 401 -fixed yes \
402 402 -DIRECTION Inout
403 403
404 404 set_io SRAM_A\[11\] \
405 405 -pinname A11 \
406 406 -fixed yes \
407 407 -DIRECTION Inout
408 408
409 409 set_io SRAM_A\[12\] \
410 410 -pinname B12 \
411 411 -fixed yes \
412 412 -DIRECTION Inout
413 413
414 414 set_io SRAM_A\[13\] \
415 415 -pinname A13 \
416 416 -fixed yes \
417 417 -DIRECTION Inout
418 418
419 419 set_io SRAM_A\[14\] \
420 420 -pinname B13 \
421 421 -fixed yes \
422 422 -DIRECTION Inout
423 423
424 424 set_io SRAM_A\[15\] \
425 425 -pinname C18 \
426 426 -fixed yes \
427 427 -DIRECTION Inout
428 428
429 429 set_io SRAM_A\[16\] \
430 430 -pinname C17 \
431 431 -fixed yes \
432 432 -DIRECTION Inout
433 433
434 434 set_io SRAM_A\[17\] \
435 435 -pinname B18 \
436 436 -fixed yes \
437 437 -DIRECTION Inout
438 438
439 439 set_io SRAM_A\[18\] \
440 440 -pinname C16 \
441 441 -fixed yes \
442 442 -DIRECTION Inout
443 443
444 444 set_io SRAM_A\[19\] \
445 445 -pinname D15 \
446 446 -fixed yes \
447 447 -DIRECTION Inout
448 448
449 449
450 450 #================================
451 451 # SRAM DATA
452 452 #================================
453 453
454 454 set_io SRAM_DQ\[0\] \
455 455 -pinname D16 \
456 456 -fixed yes \
457 457 -DIRECTION Inout
458 458
459 459 set_io SRAM_DQ\[1\] \
460 460 -pinname D18 \
461 461 -fixed yes \
462 462 -DIRECTION Inout
463 463
464 464 set_io SRAM_DQ\[2\] \
465 465 -pinname E15 \
466 466 -fixed yes \
467 467 -DIRECTION Inout
468 468
469 469 set_io SRAM_DQ\[3\] \
470 470 -pinname E18 \
471 471 -fixed yes \
472 472 -DIRECTION Inout
473 473
474 474 set_io SRAM_DQ\[4\] \
475 475 -pinname F15 \
476 476 -fixed yes \
477 477 -DIRECTION Inout
478 478
479 479 set_io SRAM_DQ\[5\] \
480 480 -pinname F18 \
481 481 -fixed yes \
482 482 -DIRECTION Inout
483 483
484 484 set_io SRAM_DQ\[6\] \
485 485 -pinname G15 \
486 486 -fixed yes \
487 487 -DIRECTION Inout
488 488
489 489 set_io SRAM_DQ\[7\] \
490 490 -pinname G17 \
491 491 -fixed yes \
492 492 -DIRECTION Inout
493 493
494 494 set_io SRAM_DQ\[8\] \
495 495 -pinname K15 \
496 496 -fixed yes \
497 497 -DIRECTION Inout
498 498
499 499 set_io SRAM_DQ\[9\] \
500 500 -pinname J18 \
501 501 -fixed yes \
502 502 -DIRECTION Inout
503 503
504 504 set_io SRAM_DQ\[10\] \
505 505 -pinname J15 \
506 506 -fixed yes \
507 507 -DIRECTION Inout
508 508
509 509 set_io SRAM_DQ\[11\] \
510 510 -pinname H18 \
511 511 -fixed yes \
512 512 -DIRECTION Inout
513 513
514 514 set_io SRAM_DQ\[12\] \
515 515 -pinname C3 \
516 516 -fixed yes \
517 517 -DIRECTION Inout
518 518
519 519 set_io SRAM_DQ\[13\] \
520 520 -pinname D4 \
521 521 -fixed yes \
522 522 -DIRECTION Inout
523 523
524 524 set_io SRAM_DQ\[14\] \
525 525 -pinname D5 \
526 526 -fixed yes \
527 527 -DIRECTION Inout
528 528
529 529 set_io SRAM_DQ\[15\] \
530 530 -pinname C6 \
531 531 -fixed yes \
532 532 -DIRECTION Inout
533 533
534 534 set_io SRAM_DQ\[16\] \
535 535 -pinname D14 \
536 536 -fixed yes \
537 537 -DIRECTION Inout
538 538
539 539 set_io SRAM_DQ\[17\] \
540 540 -pinname A15 \
541 541 -fixed yes \
542 542 -DIRECTION Inout
543 543
544 544 set_io SRAM_DQ\[18\] \
545 545 -pinname C15 \
546 546 -fixed yes \
547 547 -DIRECTION Inout
548 548
549 549 set_io SRAM_DQ\[19\] \
550 550 -pinname B17 \
551 551 -fixed yes \
552 552 -DIRECTION Inout
553 553
554 554 set_io SRAM_DQ\[20\] \
555 555 -pinname A17 \
556 556 -fixed yes \
557 557 -DIRECTION Inout
558 558
559 559 set_io SRAM_DQ\[21\] \
560 560 -pinname B16 \
561 561 -fixed yes \
562 562 -DIRECTION Inout
563 563
564 564 set_io SRAM_DQ\[22\] \
565 565 -pinname A16 \
566 566 -fixed yes \
567 567 -DIRECTION Inout
568 568
569 569 set_io SRAM_DQ\[23\] \
570 570 -pinname A14 \
571 571 -fixed yes \
572 572 -DIRECTION Inout
573 573
574 574 set_io SRAM_DQ\[24\] \
575 575 -pinname A4 \
576 576 -fixed yes \
577 577 -DIRECTION Inout
578 578
579 579 set_io SRAM_DQ\[25\] \
580 580 -pinname A3 \
581 581 -fixed yes \
582 582 -DIRECTION Inout
583 583
584 584 set_io SRAM_DQ\[26\] \
585 585 -pinname A2 \
586 586 -fixed yes \
587 587 -DIRECTION Inout
588 588
589 589 set_io SRAM_DQ\[27\] \
590 590 -pinname B1 \
591 591 -fixed yes \
592 592 -DIRECTION Inout
593 593
594 594 set_io SRAM_DQ\[28\] \
595 595 -pinname C1 \
596 596 -fixed yes \
597 597 -DIRECTION Inout
598 598
599 599 set_io SRAM_DQ\[29\] \
600 600 -pinname B2 \
601 601 -fixed yes \
602 602 -DIRECTION Inout
603 603
604 604 set_io SRAM_DQ\[30\] \
605 605 -pinname B3 \
606 606 -fixed yes \
607 607 -DIRECTION Inout
608 608
609 609 set_io SRAM_DQ\[31\] \
610 610 -pinname C4 \
611 611 -fixed yes \
612 612 -DIRECTION Inout
613 613
614 614
615 615
616 616
617 617
618 618
619 619
620 620
621 621
622 622
623 623
624 624
625 625
626 626
627 627
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629 629
630 630
631 631
632 632
633 633
634 634
635 635
636 636
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639 639
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@@ -1,114 +1,114
1 1 ################################################################################
2 2 # SDC WRITER VERSION "3.1";
3 3 # DESIGN "LFR_EQM";
4 4 # Timing constraints scenario: "Primary";
5 5 # DATE "Fri Apr 24 16:02:16 2015";
6 6 # VENDOR "Actel";
7 7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 9 ################################################################################
10 10
11 11
12 12 set sdc_version 1.7
13 13
14 14
15 15 ######## Clock Constraints ########
16 16
17 17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18 18
19 19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20 20
21 21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22 22
23 23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24 24
25 25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26 26
27 27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28 28
29 29
30 30
31 31 ######## Generated Clock Constraints ########
32 32
33 33
34 34
35 35 ######## Clock Source Latency Constraints #########
36 36
37 37
38 38
39 39 ######## Input Delay Constraints ########
40 40
41 41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50 50
51 51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 54
55 55
56 56
57 57 ######## Output Delay Constraints ########
58 58
59 59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68 68
69 69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 72 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
73 73 address[7] address[8] address[9] }]
74 74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 76 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
77 77 address[7] address[8] address[9] }]
78 78
79 79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
82 82
83 83
84 84 ######## Delay Constraints ########
85 85
86 86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87 87
88 88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89 89
90 90
91 91 ######## Delay Constraints ########
92 92
93 93
94 94
95 95 ######## Multicycle Constraints ########
96 96
97 97
98 98
99 99 ######## False Path Constraints ########
100 100
101 101
102 102
103 103 ######## Output load Constraints ########
104 104
105 105
106 106
107 107 ######## Disable Timing Constraints #########
108 108
109 109
110 110
111 111 ######## Clock Uncertainty Constraints #########
112 112
113 113
114 114
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@@ -1,656 +1,653
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 -----------------------------------------------------------------------------
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
53 -- clk_50 frequency is 100 Mhz !
54 clk_50 : IN STD_LOGIC;
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
56 -----------------------------------------------------------------------------
57 clk_49 : IN STD_LOGIC;
51 clk100MHz : IN STD_LOGIC;
52 clk49_152MHz : IN STD_LOGIC;
58 53 reset : IN STD_LOGIC;
59 54 --BPs
60 55 BP0 : IN STD_LOGIC;
61 56 BP1 : IN STD_LOGIC;
62 57 --LEDs
63 58 LED0 : OUT STD_LOGIC;
64 59 LED1 : OUT STD_LOGIC;
65 60 LED2 : OUT STD_LOGIC;
66 61 --UARTs
67 62 TXD1 : IN STD_LOGIC;
68 63 RXD1 : OUT STD_LOGIC;
69 64 nCTS1 : OUT STD_LOGIC;
70 65 nRTS1 : IN STD_LOGIC;
71 66
72 67 TXD2 : IN STD_LOGIC;
73 68 RXD2 : OUT STD_LOGIC;
74 69 nCTS2 : OUT STD_LOGIC;
75 70 nDTR2 : IN STD_LOGIC;
76 71 nRTS2 : IN STD_LOGIC;
77 72 nDCD2 : OUT STD_LOGIC;
78 73
79 74 --EXT CONNECTOR
80 75 IO0 : INOUT STD_LOGIC;
81 76 IO1 : INOUT STD_LOGIC;
82 77 IO2 : INOUT STD_LOGIC;
83 78 IO3 : INOUT STD_LOGIC;
84 79 IO4 : INOUT STD_LOGIC;
85 80 IO5 : INOUT STD_LOGIC;
86 81 IO6 : INOUT STD_LOGIC;
87 82 IO7 : INOUT STD_LOGIC;
88 83 IO8 : INOUT STD_LOGIC;
89 84 IO9 : INOUT STD_LOGIC;
90 85 IO10 : INOUT STD_LOGIC;
91 86 IO11 : INOUT STD_LOGIC;
92 87
93 88 --SPACE WIRE
94 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
95 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
96 91 SPW_NOM_SIN : IN STD_LOGIC;
97 92 SPW_NOM_DOUT : OUT STD_LOGIC;
98 93 SPW_NOM_SOUT : OUT STD_LOGIC;
99 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
100 95 SPW_RED_SIN : IN STD_LOGIC;
101 96 SPW_RED_DOUT : OUT STD_LOGIC;
102 97 SPW_RED_SOUT : OUT STD_LOGIC;
103 98 -- MINI LFR ADC INPUTS
104 99 ADC_nCS : OUT STD_LOGIC;
105 100 ADC_CLK : OUT STD_LOGIC;
106 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
107 102
108 103 -- SRAM
109 104 SRAM_nWE : OUT STD_LOGIC;
110 105 SRAM_CE : OUT STD_LOGIC;
111 106 SRAM_nOE : OUT STD_LOGIC;
112 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
113 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
114 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
115 110 );
116 111
117 112 END MINI_LFR_top;
118 113
119 114
120 115 ARCHITECTURE beh OF MINI_LFR_top IS
121 116
122 117 --==========================================================================
123 118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
124 119 -- when enabled, chip enable polarity should be reversed and bank size also
125 120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
126 121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
127 122 --==========================================================================
128 123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
129 124 --==========================================================================
130 125
131 126 SIGNAL clk_50_s : STD_LOGIC := '0';
132 127 SIGNAL clk_25 : STD_LOGIC := '0';
133 128 SIGNAL clk_24 : STD_LOGIC := '0';
134 129 -----------------------------------------------------------------------------
135 130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
137 132 --
138 133 SIGNAL errorn : STD_LOGIC;
139 134 -- UART AHB ---------------------------------------------------------------
140 135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
141 136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
142 137
143 138 -- UART APB ---------------------------------------------------------------
144 139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
145 140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
146 141 --
147 142 SIGNAL I00_s : STD_LOGIC;
148 143
149 144 -- CONSTANTS
150 145 CONSTANT CFG_PADTECH : INTEGER := inferred;
151 146 --
152 147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
153 148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
154 149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
155 150
156 151 SIGNAL apbi_ext : apb_slv_in_type;
157 152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
158 153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
159 154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
160 155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
161 156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
162 157
163 158 -- Spacewire signals
164 159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
167 162 SIGNAL spw_rxtxclk : STD_ULOGIC;
168 163 SIGNAL spw_rxclkn : STD_ULOGIC;
169 164 SIGNAL spw_clk : STD_LOGIC;
170 165 SIGNAL swni : grspw_in_type;
171 166 SIGNAL swno : grspw_out_type;
172 167 -- SIGNAL clkmn : STD_ULOGIC;
173 168 -- SIGNAL txclk : STD_ULOGIC;
174 169
175 170 --GPIO
176 171 SIGNAL gpioi : gpio_in_type;
177 172 SIGNAL gpioo : gpio_out_type;
178 173
179 174 -- AD Converter ADS7886
180 175 SIGNAL sample : Samples14v(7 DOWNTO 0);
181 176 SIGNAL sample_s : Samples(7 DOWNTO 0);
182 177 SIGNAL sample_val : STD_LOGIC;
183 178 SIGNAL ADC_nCS_sig : STD_LOGIC;
184 179 SIGNAL ADC_CLK_sig : STD_LOGIC;
185 180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
186 181
187 182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
188 183
189 184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
191 186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
192 187 -----------------------------------------------------------------------------
193 188
194 189 SIGNAL LFR_soft_rstn : STD_LOGIC;
195 190 SIGNAL LFR_rstn : STD_LOGIC;
196 191
197 192
198 193 SIGNAL rstn_25 : STD_LOGIC;
199 194 SIGNAL rstn_25_d1 : STD_LOGIC;
200 195 SIGNAL rstn_25_d2 : STD_LOGIC;
201 196 SIGNAL rstn_25_d3 : STD_LOGIC;
202 197
203 198 SIGNAL rstn_24 : STD_LOGIC;
204 199 SIGNAL rstn_24_d1 : STD_LOGIC;
205 200 SIGNAL rstn_24_d2 : STD_LOGIC;
206 201 SIGNAL rstn_24_d3 : STD_LOGIC;
207 202
208 203 SIGNAL rstn_50 : STD_LOGIC;
209 204 SIGNAL rstn_50_d1 : STD_LOGIC;
210 205 SIGNAL rstn_50_d2 : STD_LOGIC;
211 206 SIGNAL rstn_50_d3 : STD_LOGIC;
212 207
213 208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
214 209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
215 210
216 211 --
217 212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
218 213
219 214 --
220 215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
221 216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
222 217
223 218 SIGNAL nSRAM_READY : STD_LOGIC;
224 219
225 220 BEGIN -- beh
226 221
227 222 -----------------------------------------------------------------------------
228 223 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
229 224 -- clk_50 frequency is 100 Mhz !
230 PROCESS (clk_50, reset)
225 PROCESS (clk100MHz, reset)
231 226 BEGIN -- PROCESS
232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
227 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
233 228 clk_50_s <= NOT clk_50_s;
234 229 END IF;
235 230 END PROCESS;
236 231 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
237 232 -----------------------------------------------------------------------------
238 233
239 234 PROCESS (clk_50_s, reset)
240 235 BEGIN -- PROCESS
241 236 IF reset = '0' THEN -- asynchronous reset (active low)
242 237 clk_25 <= '0';
243 238 rstn_25 <= '0';
244 239 rstn_25_d1 <= '0';
245 240 rstn_25_d2 <= '0';
246 241 rstn_25_d3 <= '0';
247 242 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
248 243 clk_25 <= NOT clk_25;
249 244 rstn_25_d1 <= '1';
250 245 rstn_25_d2 <= rstn_25_d1;
251 246 rstn_25_d3 <= rstn_25_d2;
252 247 rstn_25 <= rstn_25_d3;
253 248 END IF;
254 249 END PROCESS;
255 250
256 PROCESS (clk_49, reset)
251 PROCESS (clk49_152MHz, reset)
257 252 BEGIN -- PROCESS
258 253 IF reset = '0' THEN -- asynchronous reset (active low)
259 254 clk_24 <= '0';
260 255 rstn_24_d1 <= '0';
261 256 rstn_24_d2 <= '0';
262 257 rstn_24_d3 <= '0';
263 258 rstn_24 <= '0';
264 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
259 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
265 260 clk_24 <= NOT clk_24;
266 261 rstn_24_d1 <= '1';
267 262 rstn_24_d2 <= rstn_24_d1;
268 263 rstn_24_d3 <= rstn_24_d2;
269 264 rstn_24 <= rstn_24_d3;
270 265 END IF;
271 266 END PROCESS;
272 267
273 268 -----------------------------------------------------------------------------
274 269
275 270 PROCESS (clk_25, rstn_25)
276 271 BEGIN -- PROCESS
277 272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 273 LED0 <= '0';
279 274 LED1 <= '0';
280 275 LED2 <= '0';
281 276 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
282 277 LED0 <= '0';
283 278 LED1 <= '1';
284 279 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
285 280 END IF;
286 281 END PROCESS;
287 282
288 PROCESS (clk_24, rstn_24)
283 PROCESS (clk49_152MHz, rstn_24)
289 284 BEGIN -- PROCESS
290 285 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
291 286 I00_s <= '0';
292 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
287 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
293 288 I00_s <= NOT I00_s;
294 289 END IF;
295 290 END PROCESS;
296 291
297 292 --UARTs
298 293 nCTS1 <= '1';
299 294 nCTS2 <= '1';
300 295 nDCD2 <= '1';
296 -- No AHB UART
297 RXD1 <= TXD1;
301 298
302 299 --
303 300
304 301 leon3_soc_1 : leon3_soc
305 302 GENERIC MAP (
306 303 fabtech => apa3e,
307 304 memtech => apa3e,
308 305 padtech => inferred,
309 306 clktech => inferred,
310 307 disas => 0,
311 308 dbguart => 0,
312 309 pclow => 2,
313 310 clk_freq => 25000,
314 311 IS_RADHARD => 0,
315 312 NB_CPU => 1,
316 313 ENABLE_FPU => 1,
317 314 FPU_NETLIST => 0,
318 315 ENABLE_DSU => 1,
319 316 ENABLE_AHB_UART => 0,
320 317 ENABLE_APB_UART => 1,
321 318 ENABLE_IRQMP => 1,
322 319 ENABLE_GPT => 1,
323 320 NB_AHB_MASTER => NB_AHB_MASTER,
324 321 NB_AHB_SLAVE => NB_AHB_SLAVE,
325 322 NB_APB_SLAVE => NB_APB_SLAVE,
326 323 ADDRESS_SIZE => 20,
327 324 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
328 325 BYPASS_EDAC_MEMCTRLR => '0',
329 326 SRBANKSZ => 9)
330 327 PORT MAP (
331 328 clk => clk_25,
332 329 reset => rstn_25,
333 330 errorn => errorn,
334 331 ahbrxd => OPEN,--TXD1,
335 332 ahbtxd => OPEN,--RXD1,
336 333 urxd1 => TXD2,
337 334 utxd1 => RXD2,
338 335 address => SRAM_A,
339 336 data => SRAM_DQ,
340 337 nSRAM_BE0 => SRAM_nBE(0),
341 338 nSRAM_BE1 => SRAM_nBE(1),
342 339 nSRAM_BE2 => SRAM_nBE(2),
343 340 nSRAM_BE3 => SRAM_nBE(3),
344 341 nSRAM_WE => SRAM_nWE,
345 342 nSRAM_CE => SRAM_CE_s,
346 343 nSRAM_OE => SRAM_nOE,
347 344 nSRAM_READY => nSRAM_READY,
348 345 SRAM_MBE => OPEN,
349 346 apbi_ext => apbi_ext,
350 347 apbo_ext => apbo_ext,
351 348 ahbi_s_ext => ahbi_s_ext,
352 349 ahbo_s_ext => ahbo_s_ext,
353 350 ahbi_m_ext => ahbi_m_ext,
354 351 ahbo_m_ext => ahbo_m_ext);
355 352
356 353 PROCESS (clk_25, rstn_25)
357 354 BEGIN -- PROCESS
358 355 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
359 356 nSRAM_READY <= '1';
360 357 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
361 358 nSRAM_READY <= '1';
362 359 IF IO0 = '1' THEN
363 360 nSRAM_READY <= '0';
364 361 END IF;
365 362 END IF;
366 363 END PROCESS;
367 364
368 365
369 366
370 367 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
371 368 SRAM_CE <= not SRAM_CE_s(0);
372 369 END GENERATE;
373 370
374 371 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
375 372 SRAM_CE <= SRAM_CE_s(0);
376 373 END GENERATE;
377 374 -------------------------------------------------------------------------------
378 375 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
379 376 -------------------------------------------------------------------------------
380 377 apb_lfr_management_1 : apb_lfr_management
381 378 GENERIC MAP (
382 379 tech => apa3e,
383 380 pindex => 6,
384 381 paddr => 6,
385 382 pmask => 16#fff#,
386 383 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
387 384 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
388 385 PORT MAP (
389 386 clk25MHz => clk_25,
390 387 resetn_25MHz => rstn_25, -- TODO
391 388 -- clk24_576MHz => clk_24, -- 49.152MHz/2
392 389 -- resetn_24_576MHz => rstn_24, -- TODO
393 390 grspw_tick => swno.tickout,
394 391 apbi => apbi_ext,
395 392 apbo => apbo_ext(6),
396 393 HK_sample => sample_hk,
397 394 HK_val => sample_val,
398 395 HK_sel => HK_SEL,
399 396 DAC_SDO => OPEN,
400 397 DAC_SCK => OPEN,
401 398 DAC_SYNC => OPEN,
402 399 DAC_CAL_EN => OPEN,
403 400 coarse_time => coarse_time,
404 401 fine_time => fine_time,
405 402 LFR_soft_rstn => LFR_soft_rstn
406 403 );
407 404
408 405 -----------------------------------------------------------------------
409 406 --- SpaceWire --------------------------------------------------------
410 407 -----------------------------------------------------------------------
411 408
412 409 SPW_EN <= '1';
413 410
414 411 spw_clk <= clk_50_s;
415 412 spw_rxtxclk <= spw_clk;
416 413 spw_rxclkn <= NOT spw_rxtxclk;
417 414
418 415 -- PADS for SPW1
419 416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
420 417 PORT MAP (SPW_NOM_DIN, dtmp(0));
421 418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
422 419 PORT MAP (SPW_NOM_SIN, stmp(0));
423 420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
424 421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
425 422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
426 423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
427 424 -- PADS FOR SPW2
428 425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
429 426 PORT MAP (SPW_RED_SIN, dtmp(1));
430 427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
431 428 PORT MAP (SPW_RED_DIN, stmp(1));
432 429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
433 430 PORT MAP (SPW_RED_DOUT, swno.d(1));
434 431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
435 432 PORT MAP (SPW_RED_SOUT, swno.s(1));
436 433
437 434 -- GRSPW PHY
438 435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
439 436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
440 437 spw_phy0 : grspw_phy
441 438 GENERIC MAP(
442 439 tech => apa3e,
443 440 rxclkbuftype => 1,
444 441 scantest => 0)
445 442 PORT MAP(
446 443 rxrst => swno.rxrst,
447 444 di => dtmp(j),
448 445 si => stmp(j),
449 446 rxclko => spw_rxclk(j),
450 447 do => swni.d(j),
451 448 ndo => swni.nd(j*5+4 DOWNTO j*5),
452 449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
453 450 END GENERATE spw_inputloop;
454 451
455 452 swni.rmapnodeaddr <= (OTHERS => '0');
456 453
457 454 -- SPW core
458 455 sw0 : grspwm GENERIC MAP(
459 456 tech => apa3e,
460 457 hindex => 1,
461 458 pindex => 5,
462 459 paddr => 5,
463 460 pirq => 11,
464 461 sysfreq => 25000, -- CPU_FREQ
465 462 rmap => 1,
466 463 rmapcrc => 1,
467 464 fifosize1 => 16,
468 465 fifosize2 => 16,
469 466 rxclkbuftype => 1,
470 467 rxunaligned => 0,
471 468 rmapbufs => 4,
472 469 ft => 0,
473 470 netlist => 0,
474 471 ports => 2,
475 472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
476 473 memtech => apa3e,
477 474 destkey => 2,
478 475 spwcore => 1
479 476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
480 477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
481 478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
482 479 )
483 480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
484 481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
485 482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
486 483 swni, swno);
487 484
488 485 swni.tickin <= '0';
489 486 swni.rmapen <= '1';
490 487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
491 488 swni.tickinraw <= '0';
492 489 swni.timein <= (OTHERS => '0');
493 490 swni.dcrstval <= (OTHERS => '0');
494 491 swni.timerrstval <= (OTHERS => '0');
495 492
496 493 -------------------------------------------------------------------------------
497 494 -- LFR ------------------------------------------------------------------------
498 495 -------------------------------------------------------------------------------
499 496
500 497
501 498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
502 499 --LFR_rstn <= rstn_25;
503 500
504 501 lpp_lfr_1 : lpp_lfr
505 502 GENERIC MAP (
506 503 Mem_use => use_RAM,
507 504 nb_data_by_buffer_size => 32,
508 505 nb_snapshot_param_size => 32,
509 506 delta_vector_size => 32,
510 507 delta_vector_size_f0_2 => 7, -- log2(96)
511 508 pindex => 15,
512 509 paddr => 15,
513 510 pmask => 16#fff#,
514 511 pirq_ms => 6,
515 512 pirq_wfp => 14,
516 513 hindex => 2,
517 514 top_lfr_version => X"000159") -- aa.bb.cc version
518 515 PORT MAP (
519 516 clk => clk_25,
520 517 rstn => LFR_rstn,
521 518 sample_B => sample_s(2 DOWNTO 0),
522 519 sample_E => sample_s(7 DOWNTO 3),
523 520 sample_val => sample_val,
524 521 apbi => apbi_ext,
525 522 apbo => apbo_ext(15),
526 523 ahbi => ahbi_m_ext,
527 524 ahbo => ahbo_m_ext(2),
528 525 coarse_time => coarse_time,
529 526 fine_time => fine_time,
530 527 data_shaping_BW => bias_fail_sw_sig,
531 528 debug_vector => lfr_debug_vector,
532 529 debug_vector_ms => lfr_debug_vector_ms
533 530 );
534 531
535 532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
536 533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
537 534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
538 535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
539 536 -- IO0 <= rstn_25;
540 537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
541 538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
542 539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
543 540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
544 541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
545 542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
546 543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
547 544
548 545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
549 546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
550 547 END GENERATE all_sample;
551 548
552 549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
553 550 GENERIC MAP(
554 551 ChannelCount => 8,
555 552 SampleNbBits => 14,
556 553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
557 554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
558 555 PORT MAP (
559 556 -- CONV
560 557 cnv_clk => clk_24,
561 558 cnv_rstn => rstn_24,
562 559 cnv => ADC_nCS_sig,
563 560 -- DATA
564 561 clk => clk_25,
565 562 rstn => rstn_25,
566 563 sck => ADC_CLK_sig,
567 564 sdo => ADC_SDO_sig,
568 565 -- SAMPLE
569 566 sample => sample,
570 567 sample_val => sample_val);
571 568
572 569 --IO10 <= ADC_SDO_sig(5);
573 570 --IO9 <= ADC_SDO_sig(4);
574 571 --IO8 <= ADC_SDO_sig(3);
575 572
576 573 ADC_nCS <= ADC_nCS_sig;
577 574 ADC_CLK <= ADC_CLK_sig;
578 575 ADC_SDO_sig <= ADC_SDO;
579 576
580 577 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
581 578 "0010001000100010" WHEN HK_SEL = "01" ELSE
582 579 "0100010001000100" WHEN HK_SEL = "10" ELSE
583 580 (OTHERS => '0');
584 581
585 582
586 583 ----------------------------------------------------------------------
587 584 --- GPIO -----------------------------------------------------------
588 585 ----------------------------------------------------------------------
589 586
590 587 grgpio0 : grgpio
591 588 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
592 589 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
593 590
594 591 gpioi.sig_en <= (OTHERS => '0');
595 592 gpioi.sig_in <= (OTHERS => '0');
596 593 gpioi.din <= (OTHERS => '0');
597 594 PROCESS (clk_25, rstn_25)
598 595 BEGIN -- PROCESS
599 596 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
600 597 IO8 <= '0';
601 598 IO9 <= '0';
602 599 IO10 <= '0';
603 600 IO11 <= '0';
604 601 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
605 602 CASE gpioo.dout(2 DOWNTO 0) IS
606 603 WHEN "011" =>
607 604 IO8 <= observation_reg(8);
608 605 IO9 <= observation_reg(9);
609 606 IO10 <= observation_reg(10);
610 607 IO11 <= observation_reg(11);
611 608 WHEN "001" =>
612 609 IO8 <= observation_reg(8 + 12);
613 610 IO9 <= observation_reg(9 + 12);
614 611 IO10 <= observation_reg(10 + 12);
615 612 IO11 <= observation_reg(11 + 12);
616 613 WHEN "010" =>
617 614 IO8 <= '0';
618 615 IO9 <= '0';
619 616 IO10 <= '0';
620 617 IO11 <= '0';
621 618 WHEN "000" =>
622 619 IO8 <= observation_vector_0(8);
623 620 IO9 <= observation_vector_0(9);
624 621 IO10 <= observation_vector_0(10);
625 622 IO11 <= observation_vector_0(11);
626 623 WHEN "100" =>
627 624 IO8 <= observation_vector_1(8);
628 625 IO9 <= observation_vector_1(9);
629 626 IO10 <= observation_vector_1(10);
630 627 IO11 <= observation_vector_1(11);
631 628 WHEN OTHERS => NULL;
632 629 END CASE;
633 630
634 631 END IF;
635 632 END PROCESS;
636 633 -----------------------------------------------------------------------------
637 634 --
638 635 -----------------------------------------------------------------------------
639 636 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
640 637 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
641 638 apbo_ext(I) <= apb_none;
642 639 END GENERATE apbo_ext_not_used;
643 640 END GENERATE all_apbo_ext;
644 641
645 642
646 643 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
647 644 ahbo_s_ext(I) <= ahbs_none;
648 645 END GENERATE all_ahbo_ext;
649 646
650 647 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
651 648 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
652 649 ahbo_m_ext(I) <= ahbm_none;
653 650 END GENERATE ahbo_m_ext_not_used;
654 651 END GENERATE all_ahbo_m_ext;
655 652
656 653 END beh;
Show file before | Show file after | Hide comments
@@ -1,53 +1,51
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 ##PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 PDC=$(VHDLIB)/boards/$(BOARD)/no_uart.pdc
19 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
21 19 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 20 CLEAN=soft-clean
23 21
24 22 TECHLIBS = proasic3e
25 23
26 24 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 25 tmtc openchip hynix ihp gleichmann micron usbhc
28 26
29 27 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 28 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 29 ./amba_lcd_16x2_ctrlr \
32 30 ./general_purpose/lpp_AMR \
33 31 ./general_purpose/lpp_balise \
34 32 ./general_purpose/lpp_delay \
35 33 ./lpp_bootloader \
36 34 ./lpp_uart \
37 35 ./lpp_usb \
38 36 ./dsp/lpp_fft_rtax \
39 37 ./lpp_sim/CY7C1061DV33 \
40 38
41 39 FILESKIP =i2cmst.vhd \
42 40 APB_MULTI_DIODE.vhd \
43 41 APB_SIMPLE_DIODE.vhd \
44 42 Top_MatrixSpec.vhd \
45 43 APB_FFT.vhd \
46 44 CoreFFT_simu.vhd \
47 45 lpp_lfr_apbreg_simu.vhd
48 46
49 47 include $(GRLIB)/bin/Makefile
50 48 include $(GRLIB)/software/leon3/Makefile
51 49
52 50 ################## project specific targets ##########################
53 51
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