@@ -0,0 +1,90 | |||||
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1 | -- FillFifo.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | ||||
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6 | entity FillFifo is | |||
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7 | generic( | |||
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8 | Data_sz : integer range 1 to 32 := 16; | |||
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9 | Fifo_cnt : integer range 1 to 8 := 5 | |||
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10 | ); | |||
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11 | port( | |||
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12 | clk : in std_logic; | |||
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13 | raz : in std_logic; | |||
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14 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |||
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15 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |||
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16 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |||
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17 | ); | |||
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18 | end entity; | |||
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19 | ||||
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20 | ||||
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21 | architecture ar_FillFifo of FillFifo is | |||
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22 | ||||
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23 | signal i : integer := 0; | |||
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24 | ||||
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25 | type etat is (eX,e0,e00); | |||
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26 | signal ect : etat; | |||
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27 | ||||
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28 | type Tbl is array(natural range <>) of std_logic_vector(Data_sz-1 downto 0); | |||
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29 | ||||
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30 | --constant TblA : Tbl (0 to 255) := (X"FFFF",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE",X"0000",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B", | |||
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31 | --X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE"); | |||
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32 | ||||
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33 | constant TblA : Tbl (0 to 255) := (X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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34 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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35 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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36 | ||||
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37 | constant TblB : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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38 | X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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39 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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40 | ||||
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41 | constant TblC : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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42 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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43 | X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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44 | ||||
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45 | constant TblD : Tbl (0 to 255) := (X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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46 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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47 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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48 | ||||
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49 | constant TblE : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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50 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001", | |||
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51 | X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001"); | |||
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52 | ||||
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53 | begin | |||
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54 | ||||
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55 | process(clk,raz) | |||
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56 | begin | |||
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57 | if(raz='0')then | |||
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58 | i <= 0; | |||
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59 | Write <= (others => '1'); | |||
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60 | Reuse <= (others => '0'); | |||
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61 | ect <= e00; | |||
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62 | ||||
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63 | elsif(clk'event and clk='1')then | |||
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64 | ||||
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65 | case ect is | |||
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66 | ||||
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67 | when e00 => | |||
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68 | Write <= (others => '0'); | |||
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69 | ect <= e0; | |||
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70 | ||||
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71 | when e0 => | |||
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72 | if(i=255)then | |||
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73 | Write <= (others => '1'); | |||
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74 | Reuse <= (others => '1'); | |||
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75 | ect <= eX; | |||
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76 | else | |||
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77 | i <= i+1; | |||
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78 | ect <= e0; | |||
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79 | end if; | |||
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80 | ||||
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81 | when eX => | |||
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82 | null; | |||
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83 | ||||
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84 | end case; | |||
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85 | end if; | |||
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86 | end process; | |||
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87 | ||||
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88 | data <= TblE(i) & TblD(i) & TblC(i) & TblB(i) & TblA(i); | |||
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89 | ||||
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90 | end architecture; No newline at end of file |
@@ -1,93 +1,100 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 |
------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 |
|
25 | |||
26 | entity RAM_CEL is |
|
26 | entity RAM_CEL is | |
27 | port( WD : in std_logic_vector(15 downto 0); RD : out |
|
27 | generic(DataSz : integer range 1 to 32 := 8; | |
28 | std_logic_vector(15 downto 0);WEN, REN : in std_logic; |
|
28 | abits : integer range 2 to 12 := 8); | |
29 |
|
|
29 | port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out | |
30 |
std_logic_vector( |
|
30 | std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; | |
|
31 | WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in | |||
|
32 | std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic | |||
31 | ) ; |
|
33 | ) ; | |
32 | end RAM_CEL; |
|
34 | end RAM_CEL; | |
33 |
|
35 | |||
34 |
|
36 | |||
35 |
|
37 | |||
36 | architecture ar_RAM_CEL of RAM_CEL is |
|
38 | architecture ar_RAM_CEL of RAM_CEL is | |
37 | type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0); |
|
39 | ||
38 | signal RAMarray : RAMarrayT:=(others => X"0000"); |
|
40 | constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0'); | |
39 | signal RD_int : std_logic_vector(15 downto 0); |
|
41 | constant MAX : integer := 2**(abits); | |
|
42 | ||||
|
43 | type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0); | |||
|
44 | ||||
|
45 | signal RAMarray : RAMarrayT:=(others => VectInit); | |||
|
46 | signal RD_int : std_logic_vector(DataSz-1 downto 0); | |||
40 |
|
47 | |||
41 | begin |
|
48 | begin | |
42 |
|
49 | |||
43 | RD_int <= RAMarray(to_integer(unsigned(RADDR))); |
|
50 | RD_int <= RAMarray(to_integer(unsigned(RADDR))); | |
44 |
|
51 | |||
45 |
|
52 | |||
46 | process(RWclk,reset) |
|
53 | process(RWclk,reset) | |
47 | begin |
|
54 | begin | |
48 | if reset = '0' then |
|
55 | if reset = '0' then | |
49 | RD <= (X"0000"); |
|
56 | RD <= VectInit; | |
50 |
rst:for i in 0 to |
|
57 | rst:for i in 0 to MAX-1 loop | |
51 | RAMarray(i) <= (others => '0'); |
|
58 | RAMarray(i) <= (others => '0'); | |
52 | end loop; |
|
59 | end loop; | |
53 |
|
60 | |||
54 | elsif RWclk'event and RWclk = '1' then |
|
61 | elsif RWclk'event and RWclk = '1' then | |
55 | if REN = '0' then |
|
62 | if REN = '0' then | |
56 | RD <= RD_int; |
|
63 | RD <= RD_int; | |
57 | end if; |
|
64 | end if; | |
58 |
|
65 | |||
59 | if WEN = '0' then |
|
66 | if WEN = '0' then | |
60 | RAMarray(to_integer(unsigned(WADDR))) <= WD; |
|
67 | RAMarray(to_integer(unsigned(WADDR))) <= WD; | |
61 | end if; |
|
68 | end if; | |
62 |
|
69 | |||
63 | end if; |
|
70 | end if; | |
64 | end process; |
|
71 | end process; | |
65 | end ar_RAM_CEL; |
|
72 | end ar_RAM_CEL; | |
66 |
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73 | |||
67 |
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74 | |||
68 |
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75 | |||
69 |
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76 | |||
70 |
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83 |
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84 |
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86 |
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87 |
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93 |
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100 |
@@ -1,301 +1,299 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
22 | LIBRARY ieee; |
|
22 | LIBRARY ieee; | |
23 | USE ieee.std_logic_1164.ALL; |
|
23 | USE ieee.std_logic_1164.ALL; | |
24 | LIBRARY grlib; |
|
24 | LIBRARY grlib; | |
25 | USE grlib.amba.ALL; |
|
25 | USE grlib.amba.ALL; | |
26 | USE grlib.stdlib.ALL; |
|
26 | USE grlib.stdlib.ALL; | |
27 | USE grlib.devices.ALL; |
|
27 | USE grlib.devices.ALL; | |
28 |
|
28 | |||
29 |
|
29 | |||
30 |
|
30 | |||
31 |
|
31 | |||
32 | PACKAGE iir_filter IS |
|
32 | PACKAGE iir_filter IS | |
33 |
|
33 | |||
34 |
|
34 | |||
35 | --===========================================================| |
|
35 | --===========================================================| | |
36 | --================A L U C O N T R O L======================| |
|
36 | --================A L U C O N T R O L======================| | |
37 | --===========================================================| |
|
37 | --===========================================================| | |
38 | CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; |
|
38 | CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; | |
39 | CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; |
|
39 | CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; | |
40 | CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; |
|
40 | CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; | |
41 | CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; |
|
41 | CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; | |
42 | CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; |
|
42 | CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; | |
43 | CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; |
|
43 | CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; | |
44 |
|
44 | |||
45 | --____ |
|
45 | --____ | |
46 | --RAM | |
|
46 | --RAM | | |
47 | --____| |
|
47 | --____| | |
48 | CONSTANT use_RAM : INTEGER := 1; |
|
48 | CONSTANT use_RAM : INTEGER := 1; | |
49 | CONSTANT use_CEL : INTEGER := 0; |
|
49 | CONSTANT use_CEL : INTEGER := 0; | |
50 |
|
50 | |||
51 |
|
51 | |||
52 | --===========================================================| |
|
52 | --===========================================================| | |
53 | --=============C O E F S ====================================| |
|
53 | --=============C O E F S ====================================| | |
54 | --===========================================================| |
|
54 | --===========================================================| | |
55 | -- create a specific type of data for coefs to avoid errors | |
|
55 | -- create a specific type of data for coefs to avoid errors | | |
56 | --===========================================================| |
|
56 | --===========================================================| | |
57 |
|
57 | |||
58 | TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER; |
|
58 | TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER; | |
59 |
|
59 | |||
60 | TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
60 | TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
61 |
|
61 | |||
62 | TYPE in_IIR_CEL_reg IS RECORD |
|
62 | TYPE in_IIR_CEL_reg IS RECORD | |
63 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
63 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
64 | virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
65 | END RECORD; |
|
65 | END RECORD; | |
66 |
|
66 | |||
67 | TYPE out_IIR_CEL_reg IS RECORD |
|
67 | TYPE out_IIR_CEL_reg IS RECORD | |
68 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
68 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
69 | status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | status : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
70 | END RECORD; |
|
70 | END RECORD; | |
71 |
|
71 | |||
72 |
|
72 | |||
73 | COMPONENT APB_IIR_CEL IS |
|
73 | COMPONENT APB_IIR_CEL IS | |
74 | GENERIC ( |
|
74 | GENERIC ( | |
75 | tech : INTEGER := 0; |
|
75 | tech : INTEGER := 0; | |
76 | pindex : INTEGER := 0; |
|
76 | pindex : INTEGER := 0; | |
77 | paddr : INTEGER := 0; |
|
77 | paddr : INTEGER := 0; | |
78 | pmask : INTEGER := 16#fff#; |
|
78 | pmask : INTEGER := 16#fff#; | |
79 | pirq : INTEGER := 0; |
|
79 | pirq : INTEGER := 0; | |
80 | abits : INTEGER := 8; |
|
80 | abits : INTEGER := 8; | |
81 | Sample_SZ : INTEGER := 16; |
|
81 | Sample_SZ : INTEGER := 16; | |
82 | ChanelsCount : INTEGER := 6; |
|
82 | ChanelsCount : INTEGER := 6; | |
83 | Coef_SZ : INTEGER := 9; |
|
83 | Coef_SZ : INTEGER := 9; | |
84 | CoefCntPerCel : INTEGER := 6; |
|
84 | CoefCntPerCel : INTEGER := 6; | |
85 | Cels_count : INTEGER := 5; |
|
85 | Cels_count : INTEGER := 5; | |
86 | virgPos : INTEGER := 7; |
|
86 | virgPos : INTEGER := 7; | |
87 | Mem_use : INTEGER := use_RAM |
|
87 | Mem_use : INTEGER := use_RAM | |
88 | ); |
|
88 | ); | |
89 | PORT ( |
|
89 | PORT ( | |
90 | rst : IN STD_LOGIC; |
|
90 | rst : IN STD_LOGIC; | |
91 | clk : IN STD_LOGIC; |
|
91 | clk : IN STD_LOGIC; | |
92 | apbi : IN apb_slv_in_type; |
|
92 | apbi : IN apb_slv_in_type; | |
93 | apbo : OUT apb_slv_out_type; |
|
93 | apbo : OUT apb_slv_out_type; | |
94 | sample_clk : IN STD_LOGIC; |
|
94 | sample_clk : IN STD_LOGIC; | |
95 | sample_clk_out : OUT STD_LOGIC; |
|
95 | sample_clk_out : OUT STD_LOGIC; | |
96 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
96 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
97 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
97 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
98 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') |
|
98 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') | |
99 | ); |
|
99 | ); | |
100 | END COMPONENT; |
|
100 | END COMPONENT; | |
101 |
|
101 | |||
102 |
|
102 | |||
103 | COMPONENT Top_IIR IS |
|
103 | COMPONENT Top_IIR IS | |
104 | GENERIC( |
|
104 | GENERIC( | |
105 | Sample_SZ : INTEGER := 18; |
|
105 | Sample_SZ : INTEGER := 18; | |
106 | ChanelsCount : INTEGER := 1; |
|
106 | ChanelsCount : INTEGER := 1; | |
107 | Coef_SZ : INTEGER := 9; |
|
107 | Coef_SZ : INTEGER := 9; | |
108 | CoefCntPerCel : INTEGER := 6; |
|
108 | CoefCntPerCel : INTEGER := 6; | |
109 | Cels_count : INTEGER := 5); |
|
109 | Cels_count : INTEGER := 5); | |
110 | PORT( |
|
110 | PORT( | |
111 | reset : IN STD_LOGIC; |
|
111 | reset : IN STD_LOGIC; | |
112 | clk : IN STD_LOGIC; |
|
112 | clk : IN STD_LOGIC; | |
113 | sample_clk : IN STD_LOGIC; |
|
113 | sample_clk : IN STD_LOGIC; | |
114 | -- BP : in std_logic; |
|
114 | -- BP : in std_logic; | |
115 | -- BPinput : in std_logic_vector(3 downto 0); |
|
115 | -- BPinput : in std_logic_vector(3 downto 0); | |
116 | LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
116 | LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
117 | INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
117 | INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
118 | OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0) |
|
118 | OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0) | |
119 | ); |
|
119 | ); | |
120 | END COMPONENT; |
|
120 | END COMPONENT; | |
121 |
|
121 | |||
122 | COMPONENT IIR_CEL_CTRLR_v2 |
|
122 | COMPONENT IIR_CEL_CTRLR_v2 | |
123 | GENERIC ( |
|
123 | GENERIC ( | |
124 | tech : INTEGER; |
|
124 | tech : INTEGER; | |
125 | Mem_use : INTEGER; |
|
125 | Mem_use : INTEGER; | |
126 | Sample_SZ : INTEGER; |
|
126 | Sample_SZ : INTEGER; | |
127 | Coef_SZ : INTEGER; |
|
127 | Coef_SZ : INTEGER; | |
128 | Coef_Nb : INTEGER; |
|
128 | Coef_Nb : INTEGER; | |
129 | Coef_sel_SZ : INTEGER; |
|
129 | Coef_sel_SZ : INTEGER; | |
130 | Cels_count : INTEGER; |
|
130 | Cels_count : INTEGER; | |
131 | ChanelsCount : INTEGER); |
|
131 | ChanelsCount : INTEGER); | |
132 | PORT ( |
|
132 | PORT ( | |
133 | rstn : IN STD_LOGIC; |
|
133 | rstn : IN STD_LOGIC; | |
134 | clk : IN STD_LOGIC; |
|
134 | clk : IN STD_LOGIC; | |
135 | virg_pos : IN INTEGER; |
|
135 | virg_pos : IN INTEGER; | |
136 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); |
|
136 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
137 | sample_in_val : IN STD_LOGIC; |
|
137 | sample_in_val : IN STD_LOGIC; | |
138 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
138 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
139 | sample_out_val : OUT STD_LOGIC; |
|
139 | sample_out_val : OUT STD_LOGIC; | |
140 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); |
|
140 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |
141 | END COMPONENT; |
|
141 | END COMPONENT; | |
142 |
|
142 | |||
143 |
|
143 | |||
144 | --component FilterCTRLR is |
|
144 | --component FilterCTRLR is | |
145 | --port( |
|
145 | --port( | |
146 | -- reset : in std_logic; |
|
146 | -- reset : in std_logic; | |
147 | -- clk : in std_logic; |
|
147 | -- clk : in std_logic; | |
148 | -- sample_clk : in std_logic; |
|
148 | -- sample_clk : in std_logic; | |
149 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); |
|
149 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); | |
150 | -- sample_in : in samplT; |
|
150 | -- sample_in : in samplT; | |
151 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); |
|
151 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); | |
152 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
152 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) | |
153 | --); |
|
153 | --); | |
154 | --end component; |
|
154 | --end component; | |
155 |
|
155 | |||
156 |
|
156 | |||
157 | --component FILTER_RAM_CTRLR is |
|
157 | --component FILTER_RAM_CTRLR is | |
158 | --port( |
|
158 | --port( | |
159 | -- reset : in std_logic; |
|
159 | -- reset : in std_logic; | |
160 | -- clk : in std_logic; |
|
160 | -- clk : in std_logic; | |
161 | -- run : in std_logic; |
|
161 | -- run : in std_logic; | |
162 | -- GO_0 : in std_logic; |
|
162 | -- GO_0 : in std_logic; | |
163 | -- B_A : in std_logic; |
|
163 | -- B_A : in std_logic; | |
164 | -- writeForce : in std_logic; |
|
164 | -- writeForce : in std_logic; | |
165 | -- next_blk : in std_logic; |
|
165 | -- next_blk : in std_logic; | |
166 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); |
|
166 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); | |
167 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
167 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) | |
168 | --); |
|
168 | --); | |
169 | --end component; |
|
169 | --end component; | |
170 |
|
170 | |||
171 |
|
171 | |||
172 | COMPONENT IIR_CEL_CTRLR IS |
|
172 | COMPONENT IIR_CEL_CTRLR IS | |
173 | GENERIC( |
|
173 | GENERIC( | |
174 | tech : INTEGER := 0; |
|
174 | tech : INTEGER := 0; | |
175 | Sample_SZ : INTEGER := 16; |
|
175 | Sample_SZ : INTEGER := 16; | |
176 | ChanelsCount : INTEGER := 1; |
|
176 | ChanelsCount : INTEGER := 1; | |
177 | Coef_SZ : INTEGER := 9; |
|
177 | Coef_SZ : INTEGER := 9; | |
178 | CoefCntPerCel : INTEGER := 3; |
|
178 | CoefCntPerCel : INTEGER := 3; | |
179 | Cels_count : INTEGER := 5; |
|
179 | Cels_count : INTEGER := 5; | |
180 | Mem_use : INTEGER := use_RAM |
|
180 | Mem_use : INTEGER := use_RAM | |
181 | ); |
|
181 | ); | |
182 | PORT( |
|
182 | PORT( | |
183 | reset : IN STD_LOGIC; |
|
183 | reset : IN STD_LOGIC; | |
184 | clk : IN STD_LOGIC; |
|
184 | clk : IN STD_LOGIC; | |
185 | sample_clk : IN STD_LOGIC; |
|
185 | sample_clk : IN STD_LOGIC; | |
186 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
186 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
187 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
187 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
188 | virg_pos : IN INTEGER; |
|
188 | virg_pos : IN INTEGER; | |
189 | GOtest : OUT STD_LOGIC; |
|
189 | GOtest : OUT STD_LOGIC; | |
190 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) |
|
190 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) | |
191 | ); |
|
191 | ); | |
192 | END COMPONENT; |
|
192 | END COMPONENT; | |
193 |
|
193 | |||
194 |
|
194 | |||
195 | COMPONENT RAM IS |
|
195 | COMPONENT RAM IS | |
196 | GENERIC( |
|
196 | GENERIC( | |
197 | Input_SZ_1 : INTEGER := 8 |
|
197 | Input_SZ_1 : INTEGER := 8 | |
198 | ); |
|
198 | ); | |
199 | PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT |
|
199 | PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT | |
200 | STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC; |
|
200 | STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC; | |
201 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN |
|
201 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN | |
202 | STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC |
|
202 | STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC | |
203 | ) ; |
|
203 | ) ; | |
204 | END COMPONENT; |
|
204 | END COMPONENT; | |
205 |
|
205 | |||
206 |
|
|
206 | COMPONENT RAM_CEL is | |
207 | GENERIC ( |
|
207 | generic(DataSz : integer range 1 to 32 := 8; | |
208 | Sample_SZ : INTEGER); |
|
208 | abits : integer range 2 to 12 := 8); | |
209 | PORT ( |
|
209 | port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out | |
210 | WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
210 | std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; | |
211 | RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
211 | WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in | |
212 | WEN, REN : IN STD_LOGIC; |
|
212 | std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic | |
213 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
213 | ) ; | |
214 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
214 | end COMPONENT; | |
215 | RWCLK, RESET : IN STD_LOGIC); |
|
|||
216 | END COMPONENT; |
|
|||
217 |
|
215 | |||
218 | COMPONENT RAM_CEL_N |
|
216 | COMPONENT RAM_CEL_N | |
219 | GENERIC ( |
|
217 | GENERIC ( | |
220 | size : INTEGER); |
|
218 | size : INTEGER); | |
221 | PORT ( |
|
219 | PORT ( | |
222 | WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
220 | WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
223 | RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
221 | RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
224 | WEN, REN : IN STD_LOGIC; |
|
222 | WEN, REN : IN STD_LOGIC; | |
225 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
223 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
226 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
224 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
227 | RWCLK, RESET : IN STD_LOGIC); |
|
225 | RWCLK, RESET : IN STD_LOGIC); | |
228 | END COMPONENT; |
|
226 | END COMPONENT; | |
229 |
|
227 | |||
230 | COMPONENT IIR_CEL_FILTER IS |
|
228 | COMPONENT IIR_CEL_FILTER IS | |
231 | GENERIC( |
|
229 | GENERIC( | |
232 | tech : INTEGER := 0; |
|
230 | tech : INTEGER := 0; | |
233 | Sample_SZ : INTEGER := 16; |
|
231 | Sample_SZ : INTEGER := 16; | |
234 | ChanelsCount : INTEGER := 1; |
|
232 | ChanelsCount : INTEGER := 1; | |
235 | Coef_SZ : INTEGER := 9; |
|
233 | Coef_SZ : INTEGER := 9; | |
236 | CoefCntPerCel : INTEGER := 3; |
|
234 | CoefCntPerCel : INTEGER := 3; | |
237 | Cels_count : INTEGER := 5; |
|
235 | Cels_count : INTEGER := 5; | |
238 | Mem_use : INTEGER := use_RAM); |
|
236 | Mem_use : INTEGER := use_RAM); | |
239 | PORT( |
|
237 | PORT( | |
240 | reset : IN STD_LOGIC; |
|
238 | reset : IN STD_LOGIC; | |
241 | clk : IN STD_LOGIC; |
|
239 | clk : IN STD_LOGIC; | |
242 | sample_clk : IN STD_LOGIC; |
|
240 | sample_clk : IN STD_LOGIC; | |
243 | regs_in : IN in_IIR_CEL_reg; |
|
241 | regs_in : IN in_IIR_CEL_reg; | |
244 | regs_out : IN out_IIR_CEL_reg; |
|
242 | regs_out : IN out_IIR_CEL_reg; | |
245 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
243 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
246 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
244 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
247 | GOtest : OUT STD_LOGIC; |
|
245 | GOtest : OUT STD_LOGIC; | |
248 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) |
|
246 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) | |
249 |
|
247 | |||
250 | ); |
|
248 | ); | |
251 | END COMPONENT; |
|
249 | END COMPONENT; | |
252 |
|
250 | |||
253 |
|
251 | |||
254 | COMPONENT RAM_CTRLR2 IS |
|
252 | COMPONENT RAM_CTRLR2 IS | |
255 | GENERIC( |
|
253 | GENERIC( | |
256 | tech : INTEGER := 0; |
|
254 | tech : INTEGER := 0; | |
257 | Input_SZ_1 : INTEGER := 16; |
|
255 | Input_SZ_1 : INTEGER := 16; | |
258 | Mem_use : INTEGER := use_RAM |
|
256 | Mem_use : INTEGER := use_RAM | |
259 | ); |
|
257 | ); | |
260 | PORT( |
|
258 | PORT( | |
261 | reset : IN STD_LOGIC; |
|
259 | reset : IN STD_LOGIC; | |
262 | clk : IN STD_LOGIC; |
|
260 | clk : IN STD_LOGIC; | |
263 | WD_sel : IN STD_LOGIC; |
|
261 | WD_sel : IN STD_LOGIC; | |
264 | Read : IN STD_LOGIC; |
|
262 | Read : IN STD_LOGIC; | |
265 | WADDR_sel : IN STD_LOGIC; |
|
263 | WADDR_sel : IN STD_LOGIC; | |
266 | count : IN STD_LOGIC; |
|
264 | count : IN STD_LOGIC; | |
267 | SVG_ADDR : IN STD_LOGIC; |
|
265 | SVG_ADDR : IN STD_LOGIC; | |
268 | Write : IN STD_LOGIC; |
|
266 | Write : IN STD_LOGIC; | |
269 | GO_0 : IN STD_LOGIC; |
|
267 | GO_0 : IN STD_LOGIC; | |
270 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
268 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
271 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
|
269 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
272 | ); |
|
270 | ); | |
273 | END COMPONENT; |
|
271 | END COMPONENT; | |
274 |
|
272 | |||
275 | COMPONENT APB_IIR_Filter IS |
|
273 | COMPONENT APB_IIR_Filter IS | |
276 | GENERIC ( |
|
274 | GENERIC ( | |
277 | tech : INTEGER := 0; |
|
275 | tech : INTEGER := 0; | |
278 | pindex : INTEGER := 0; |
|
276 | pindex : INTEGER := 0; | |
279 | paddr : INTEGER := 0; |
|
277 | paddr : INTEGER := 0; | |
280 | pmask : INTEGER := 16#fff#; |
|
278 | pmask : INTEGER := 16#fff#; | |
281 | pirq : INTEGER := 0; |
|
279 | pirq : INTEGER := 0; | |
282 | abits : INTEGER := 8; |
|
280 | abits : INTEGER := 8; | |
283 | Sample_SZ : INTEGER := 16; |
|
281 | Sample_SZ : INTEGER := 16; | |
284 | ChanelsCount : INTEGER := 1; |
|
282 | ChanelsCount : INTEGER := 1; | |
285 | Coef_SZ : INTEGER := 9; |
|
283 | Coef_SZ : INTEGER := 9; | |
286 | CoefCntPerCel : INTEGER := 6; |
|
284 | CoefCntPerCel : INTEGER := 6; | |
287 | Cels_count : INTEGER := 5; |
|
285 | Cels_count : INTEGER := 5; | |
288 | virgPos : INTEGER := 3; |
|
286 | virgPos : INTEGER := 3; | |
289 | Mem_use : INTEGER := use_RAM |
|
287 | Mem_use : INTEGER := use_RAM | |
290 | ); |
|
288 | ); | |
291 | PORT ( |
|
289 | PORT ( | |
292 | rst : IN STD_LOGIC; |
|
290 | rst : IN STD_LOGIC; | |
293 | clk : IN STD_LOGIC; |
|
291 | clk : IN STD_LOGIC; | |
294 | apbi : IN apb_slv_in_type; |
|
292 | apbi : IN apb_slv_in_type; | |
295 | apbo : OUT apb_slv_out_type; |
|
293 | apbo : OUT apb_slv_out_type; | |
296 | sample_clk_out : OUT STD_LOGIC; |
|
294 | sample_clk_out : OUT STD_LOGIC; | |
297 | GOtest : OUT STD_LOGIC; |
|
295 | GOtest : OUT STD_LOGIC; | |
298 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') |
|
296 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') | |
299 | ); |
|
297 | ); | |
300 | END COMPONENT; |
|
298 | END COMPONENT; | |
301 | END; |
|
299 | END; |
@@ -1,111 +1,188 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 |
|
25 | |||
26 | entity HeaderBuilder is |
|
26 | entity HeaderBuilder is | |
27 | generic( |
|
27 | generic( | |
28 | Data_sz : integer := 32); |
|
28 | Data_sz : integer := 32); | |
29 | port( |
|
29 | port( | |
30 | clkm : in std_logic; |
|
30 | clkm : in std_logic; | |
31 | rstn : in std_logic; |
|
31 | rstn : in std_logic; | |
32 |
|
32 | |||
33 | pong : in std_logic; |
|
33 | pong : in std_logic; | |
34 | Statu : in std_logic_vector(3 downto 0); |
|
34 | Statu : in std_logic_vector(3 downto 0); | |
35 | Matrix_Type : in std_logic_vector(1 downto 0); |
|
35 | Matrix_Type : in std_logic_vector(1 downto 0); | |
36 | Matrix_Write : in std_logic; |
|
36 | Matrix_Write : in std_logic; | |
37 | Valid : out std_logic; |
|
37 | Valid : out std_logic; | |
38 |
|
38 | |||
39 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); |
|
39 | dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); | |
40 | emptyIN : in std_logic_vector(1 downto 0); |
|
40 | emptyIN : in std_logic_vector(1 downto 0); | |
41 | RenOUT : out std_logic_vector(1 downto 0); |
|
41 | RenOUT : out std_logic_vector(1 downto 0); | |
42 |
|
42 | |||
43 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); |
|
43 | dataOUT : out std_logic_vector(Data_sz-1 downto 0); | |
44 | emptyOUT : out std_logic; |
|
44 | emptyOUT : out std_logic; | |
45 | RenIN : in std_logic; |
|
45 | RenIN : in std_logic; | |
46 |
|
46 | |||
47 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); |
|
47 | header : out std_logic_vector(Data_sz-1 DOWNTO 0); | |
48 | header_val : out std_logic; |
|
48 | header_val : out std_logic; | |
49 | header_ack : in std_logic |
|
49 | header_ack : in std_logic | |
50 | ); |
|
50 | ); | |
51 | end entity; |
|
51 | end entity; | |
52 |
|
52 | |||
53 |
|
53 | |||
54 | architecture ar_HeaderBuilder of HeaderBuilder is |
|
54 | architecture ar_HeaderBuilder of HeaderBuilder is | |
55 |
|
55 | |||
56 | signal Matrix_Param : std_logic_vector(3 downto 0); |
|
56 | signal Matrix_Param : std_logic_vector(3 downto 0); | |
57 | signal Write_reg : std_logic; |
|
57 | signal Write_reg : std_logic; | |
58 | signal Data_cpt : integer; |
|
58 | signal Data_cpt : integer; | |
59 | signal MAX : integer; |
|
59 | signal MAX : integer; | |
|
60 | signal pong_reg : std_logic; | |||
60 |
|
61 | |||
|
62 | type etat is (idle0,idle1,pong0,pong1); | |||
|
63 | signal ect : etat; | |||
61 |
|
64 | |||
62 | begin |
|
65 | begin | |
63 |
|
66 | |||
64 | process (clkm,rstn) |
|
67 | process (clkm,rstn) | |
65 | begin |
|
68 | begin | |
66 | if(rstn='0')then |
|
69 | if(rstn='0')then | |
|
70 | ect <= idle0; | |||
67 | Valid <= '0'; |
|
71 | Valid <= '0'; | |
|
72 | pong_reg <= '0'; | |||
|
73 | header_val <= '0'; | |||
|
74 | header(5 downto 0) <= (others => '0'); | |||
68 | Write_reg <= '0'; |
|
75 | Write_reg <= '0'; | |
69 | Data_cpt <= 0; |
|
76 | Data_cpt <= 0; | |
70 |
MAX <= |
|
77 | MAX <= 128; | |
71 |
|
78 | |||
72 |
|
79 | |||
73 | elsif(clkm' event and clkm='1')then |
|
80 | elsif(clkm' event and clkm='1')then | |
74 | Write_reg <= Matrix_Write; |
|
81 | Write_reg <= Matrix_Write; | |
|
82 | pong_reg <= pong; | |||
75 |
|
83 | |||
76 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then |
|
84 | if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then | |
77 | MAX <= 128; |
|
85 | MAX <= 128; | |
78 | else |
|
86 | else | |
79 | MAX <= 256; |
|
87 | MAX <= 256; | |
80 | end if; |
|
88 | end if; | |
81 |
|
89 | |||
|
90 | -- if(Write_reg = '0' and Matrix_Write = '1')then | |||
|
91 | -- if(Data_cpt = MAX)then | |||
|
92 | -- Data_cpt <= 0; | |||
|
93 | -- Valid <= '1'; | |||
|
94 | -- header_val <= '1'; | |||
|
95 | -- else | |||
|
96 | -- Data_cpt <= Data_cpt + 1; | |||
|
97 | -- Valid <= '0'; | |||
|
98 | -- end if; | |||
|
99 | -- end if; | |||
|
100 | ||||
82 | if(Write_reg = '0' and Matrix_Write = '1')then |
|
101 | if(Write_reg = '0' and Matrix_Write = '1')then | |
83 |
|
|
102 | Data_cpt <= Data_cpt + 1; | |
|
103 | Valid <= '0'; | |||
|
104 | elsif(Data_cpt = MAX)then | |||
84 |
|
|
105 | Data_cpt <= 0; | |
85 |
|
|
106 | Valid <= '1'; | |
86 |
|
|
107 | header_val <= '1'; | |
87 |
|
|
108 | else | |
88 | Data_cpt <= Data_cpt + 1; |
|
|||
89 |
|
|
109 | Valid <= '0'; | |
90 |
|
|
110 | end if; | |
91 | end if; |
|
|||
92 |
|
111 | |||
|
112 | -- if(header_ack = '1')then | |||
|
113 | -- header_val <= '0'; | |||
|
114 | -- end if; | |||
|
115 | ||||
|
116 | -- if(emptyIN = "10")then | |||
|
117 | -- ping <= '0'; | |||
|
118 | -- elsif(emptyIN = "01")then | |||
|
119 | -- ping <= '1'; | |||
|
120 | -- else | |||
|
121 | -- ping <= ping; | |||
|
122 | -- end if; | |||
|
123 | ||||
|
124 | ||||
|
125 | case ect is | |||
|
126 | ||||
|
127 | when idle0 => | |||
93 | if(header_ack = '1')then |
|
128 | if(header_ack = '1')then | |
94 | header_val <= '0'; |
|
129 | header_val <= '0'; | |
|
130 | --if(pong = '1')then | |||
|
131 | ect <= pong0; | |||
|
132 | --elsif(pong = '0')then | |||
|
133 | --ect <= pong1; | |||
|
134 | --end if; | |||
|
135 | end if; | |||
|
136 | ||||
|
137 | when pong0 => | |||
|
138 | header(1 downto 0) <= Matrix_Type; | |||
|
139 | header(5 downto 2) <= Matrix_Param; | |||
|
140 | if(emptyIN(0) = '1')then | |||
|
141 | ect <= idle1; | |||
95 | end if; |
|
142 | end if; | |
96 |
|
143 | |||
|
144 | when idle1 => | |||
|
145 | if(header_ack = '1')then | |||
|
146 | header_val <= '0'; | |||
|
147 | ect <= pong1; | |||
|
148 | end if; | |||
|
149 | ||||
|
150 | when pong1 => | |||
|
151 | header(1 downto 0) <= Matrix_Type; | |||
|
152 | header(5 downto 2) <= Matrix_Param; | |||
|
153 | if(emptyIN(1) = '1')then | |||
|
154 | ect <= idle0; | |||
|
155 | end if; | |||
|
156 | ||||
|
157 | end case; | |||
97 | end if; |
|
158 | end if; | |
98 | end process; |
|
159 | end process; | |
99 |
|
160 | |||
100 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); |
|
161 | Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); | |
101 |
|
162 | |||
102 | header(1 downto 0) <= Matrix_Type; |
|
163 | --header(1 downto 0) <= Matrix_Type; | |
103 | header(5 downto 2) <= Matrix_Param; |
|
164 | --header(5 downto 2) <= Matrix_Param; | |
104 | header(31 downto 6) <= (others => '0'); |
|
165 | header(31 downto 6) <= (others => '0'); | |
105 |
|
166 | |||
106 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz); |
|
167 | with ect select | |
107 | emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1); |
|
168 | dataOUT <= dataIN(Data_sz-1 downto 0) when pong0, | |
|
169 | dataIN(Data_sz-1 downto 0) when idle0, | |||
|
170 | dataIN((2*Data_sz)-1 downto Data_sz) when pong1, | |||
|
171 | dataIN((2*Data_sz)-1 downto Data_sz) when idle1, | |||
|
172 | (others => '0') when others; | |||
108 |
|
173 | |||
109 | RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1'; |
|
174 | with ect select | |
|
175 | emptyOUT <= emptyIN(0) when pong0, | |||
|
176 | emptyIN(0) when idle0, | |||
|
177 | emptyIN(1) when pong1, | |||
|
178 | emptyIN(1) when idle1, | |||
|
179 | '1' when others; | |||
|
180 | ||||
|
181 | with ect select | |||
|
182 | RenOUT <= '1' & RenIN when pong0, | |||
|
183 | '1' & RenIN when idle0, | |||
|
184 | RenIN & '1' when pong1, | |||
|
185 | RenIN & '1' when idle1, | |||
|
186 | "11" when others; | |||
110 |
|
187 | |||
111 | end architecture; |
|
188 | end architecture; |
@@ -1,352 +1,365 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
27 | LIBRARY ieee; |
|
27 | LIBRARY ieee; | |
28 | USE ieee.std_logic_1164.ALL; |
|
28 | USE ieee.std_logic_1164.ALL; | |
29 | USE ieee.numeric_std.ALL; |
|
29 | USE ieee.numeric_std.ALL; | |
30 | LIBRARY grlib; |
|
30 | LIBRARY grlib; | |
31 | USE grlib.amba.ALL; |
|
31 | USE grlib.amba.ALL; | |
32 | USE grlib.stdlib.ALL; |
|
32 | USE grlib.stdlib.ALL; | |
33 | USE grlib.devices.ALL; |
|
33 | USE grlib.devices.ALL; | |
34 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |
35 | --USE GRLIB.DMA2AHB_TestPackage.ALL; |
|
35 | --USE GRLIB.DMA2AHB_TestPackage.ALL; | |
36 | LIBRARY lpp; |
|
36 | LIBRARY lpp; | |
37 | USE lpp.lpp_amba.ALL; |
|
37 | USE lpp.lpp_amba.ALL; | |
38 | USE lpp.apb_devices_list.ALL; |
|
38 | USE lpp.apb_devices_list.ALL; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_dma_pkg.ALL; |
|
40 | USE lpp.lpp_dma_pkg.ALL; | |
41 | LIBRARY techmap; |
|
41 | LIBRARY techmap; | |
42 | USE techmap.gencomp.ALL; |
|
42 | USE techmap.gencomp.ALL; | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | ENTITY lpp_dma_ip IS |
|
45 | ENTITY lpp_dma_ip IS | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | tech : INTEGER := inferred; |
|
47 | tech : INTEGER := inferred; | |
48 | hindex : INTEGER := 2 |
|
48 | hindex : INTEGER := 2 | |
49 | ); |
|
49 | ); | |
50 | PORT ( |
|
50 | PORT ( | |
51 | -- AMBA AHB system signals |
|
51 | -- AMBA AHB system signals | |
52 | HCLK : IN STD_ULOGIC; |
|
52 | HCLK : IN STD_ULOGIC; | |
53 | HRESETn : IN STD_ULOGIC; |
|
53 | HRESETn : IN STD_ULOGIC; | |
54 |
|
54 | |||
55 | -- AMBA AHB Master Interface |
|
55 | -- AMBA AHB Master Interface | |
56 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
56 | AHB_Master_In : IN AHB_Mst_In_Type; | |
57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
58 |
|
58 | |||
59 | -- fifo interface |
|
59 | -- fifo interface | |
60 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
61 | fifo_empty : IN STD_LOGIC; |
|
61 | fifo_empty : IN STD_LOGIC; | |
62 | fifo_ren : OUT STD_LOGIC; |
|
62 | fifo_ren : OUT STD_LOGIC; | |
63 |
|
63 | |||
64 | -- header |
|
64 | -- header | |
65 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
66 | header_val : IN STD_LOGIC; |
|
66 | header_val : IN STD_LOGIC; | |
67 | header_ack : OUT STD_LOGIC; |
|
67 | header_ack : OUT STD_LOGIC; | |
68 |
|
68 | |||
69 | -- Reg out |
|
69 | -- Reg out | |
70 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
70 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
71 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
71 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
72 | ready_matrix_f1 : OUT STD_LOGIC; |
|
72 | ready_matrix_f1 : OUT STD_LOGIC; | |
73 | ready_matrix_f2 : OUT STD_LOGIC; |
|
73 | ready_matrix_f2 : OUT STD_LOGIC; | |
74 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
74 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
75 | error_bad_component_error : OUT STD_LOGIC; |
|
75 | error_bad_component_error : OUT STD_LOGIC; | |
76 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 |
|
77 | |||
78 | -- Reg In |
|
78 | -- Reg In | |
79 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
|
79 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
80 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
|
80 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
81 | status_ready_matrix_f1 :IN STD_LOGIC; |
|
81 | status_ready_matrix_f1 :IN STD_LOGIC; | |
82 | status_ready_matrix_f2 :IN STD_LOGIC; |
|
82 | status_ready_matrix_f2 :IN STD_LOGIC; | |
83 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
|
83 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
84 | status_error_bad_component_error :IN STD_LOGIC; |
|
84 | status_error_bad_component_error :IN STD_LOGIC; | |
85 |
|
85 | |||
86 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
86 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
87 | config_active_interruption_onError : IN STD_LOGIC; |
|
87 | config_active_interruption_onError : IN STD_LOGIC; | |
88 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
89 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
91 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
92 | ); |
|
92 | ); | |
93 | END; |
|
93 | END; | |
94 |
|
94 | |||
95 | ARCHITECTURE Behavioral OF lpp_dma_ip IS |
|
95 | ARCHITECTURE Behavioral OF lpp_dma_ip IS | |
96 | ----------------------------------------------------------------------------- |
|
96 | ----------------------------------------------------------------------------- | |
97 | SIGNAL DMAIn : DMA_In_Type; |
|
97 | SIGNAL DMAIn : DMA_In_Type; | |
98 | SIGNAL header_dmai : DMA_In_Type; |
|
98 | SIGNAL header_dmai : DMA_In_Type; | |
99 | SIGNAL component_dmai : DMA_In_Type; |
|
99 | SIGNAL component_dmai : DMA_In_Type; | |
100 | SIGNAL DMAOut : DMA_OUt_Type; |
|
100 | SIGNAL DMAOut : DMA_OUt_Type; | |
101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
102 |
|
102 | |||
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | ----------------------------------------------------------------------------- |
|
104 | ----------------------------------------------------------------------------- | |
105 | TYPE state_DMAWriteBurst IS (IDLE, |
|
105 | TYPE state_DMAWriteBurst IS (IDLE, | |
|
106 | CHECK_COMPONENT_TYPE, | |||
106 | TRASH_FIFO, |
|
107 | TRASH_FIFO, | |
107 | WAIT_HEADER_ACK, |
|
108 | WAIT_HEADER_ACK, | |
108 | SEND_DATA, |
|
109 | SEND_DATA, | |
109 | WAIT_DATA_ACK, |
|
110 | WAIT_DATA_ACK, | |
110 | CHECK_LENGTH |
|
111 | CHECK_LENGTH | |
111 | ); |
|
112 | ); | |
112 | SIGNAL state : state_DMAWriteBurst := IDLE; |
|
113 | SIGNAL state : state_DMAWriteBurst := IDLE; | |
113 |
|
114 | |||
114 | SIGNAL nbSend : INTEGER; |
|
115 | SIGNAL nbSend : INTEGER; | |
115 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
116 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
116 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
117 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
117 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
118 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
118 | SIGNAL header_check_ok : STD_LOGIC; |
|
119 | SIGNAL header_check_ok : STD_LOGIC; | |
119 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
120 | SIGNAL send_matrix : STD_LOGIC; |
|
121 | SIGNAL send_matrix : STD_LOGIC; | |
121 | SIGNAL request : STD_LOGIC; |
|
122 | SIGNAL request : STD_LOGIC; | |
122 | SIGNAL remaining_data_request : INTEGER; |
|
123 | SIGNAL remaining_data_request : INTEGER; | |
123 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
124 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
124 | ----------------------------------------------------------------------------- |
|
125 | ----------------------------------------------------------------------------- | |
125 | ----------------------------------------------------------------------------- |
|
126 | ----------------------------------------------------------------------------- | |
126 | SIGNAL header_select : STD_LOGIC; |
|
127 | SIGNAL header_select : STD_LOGIC; | |
127 |
|
128 | |||
128 | SIGNAL header_send : STD_LOGIC; |
|
129 | SIGNAL header_send : STD_LOGIC; | |
129 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 | SIGNAL header_send_ok : STD_LOGIC; |
|
131 | SIGNAL header_send_ok : STD_LOGIC; | |
131 | SIGNAL header_send_ko : STD_LOGIC; |
|
132 | SIGNAL header_send_ko : STD_LOGIC; | |
132 |
|
133 | |||
133 | SIGNAL component_send : STD_LOGIC; |
|
134 | SIGNAL component_send : STD_LOGIC; | |
134 | SIGNAL component_send_ok : STD_LOGIC; |
|
135 | SIGNAL component_send_ok : STD_LOGIC; | |
135 | SIGNAL component_send_ko : STD_LOGIC; |
|
136 | SIGNAL component_send_ko : STD_LOGIC; | |
136 | ----------------------------------------------------------------------------- |
|
137 | ----------------------------------------------------------------------------- | |
137 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
138 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
138 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
139 | SIGNAL component_fifo_ren : STD_LOGIC; | |
139 |
|
140 | |||
140 | ----------------------------------------------------------------------------- |
|
141 | ----------------------------------------------------------------------------- | |
141 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
142 |
|
143 | |||
143 | BEGIN |
|
144 | BEGIN | |
144 |
|
145 | |||
145 | ----------------------------------------------------------------------------- |
|
146 | ----------------------------------------------------------------------------- | |
146 | -- DMA to AHB interface |
|
147 | -- DMA to AHB interface | |
147 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
148 |
|
149 | |||
149 | DMA2AHB_1 : DMA2AHB |
|
150 | DMA2AHB_1 : DMA2AHB | |
150 | GENERIC MAP ( |
|
151 | GENERIC MAP ( | |
151 | hindex => hindex, |
|
152 | hindex => hindex, | |
152 | vendorid => VENDOR_LPP, |
|
153 | vendorid => VENDOR_LPP, | |
153 | deviceid => 0, |
|
154 | deviceid => 0, | |
154 | version => 0, |
|
155 | version => 0, | |
155 | syncrst => 1, |
|
156 | syncrst => 1, | |
156 | boundary => 1) -- FIX 11/01/2013 |
|
157 | boundary => 1) -- FIX 11/01/2013 | |
157 | PORT MAP ( |
|
158 | PORT MAP ( | |
158 | HCLK => HCLK, |
|
159 | HCLK => HCLK, | |
159 | HRESETn => HRESETn, |
|
160 | HRESETn => HRESETn, | |
160 | DMAIn => DMAIn, |
|
161 | DMAIn => DMAIn, | |
161 | DMAOut => DMAOut, |
|
162 | DMAOut => DMAOut, | |
162 | AHBIn => AHB_Master_In, |
|
163 | AHBIn => AHB_Master_In, | |
163 | AHBOut => AHB_Master_Out); |
|
164 | AHBOut => AHB_Master_Out); | |
164 |
|
165 | |||
165 | debug_reg <= debug_reg_s; |
|
166 | debug_reg <= debug_reg_s; | |
166 |
|
167 | |||
167 | debug_info: PROCESS (HCLK, HRESETn) |
|
168 | debug_info: PROCESS (HCLK, HRESETn) | |
168 | BEGIN -- PROCESS debug_info |
|
169 | BEGIN -- PROCESS debug_info | |
169 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
170 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
170 | debug_reg_s <= (OTHERS => '0'); |
|
171 | debug_reg_s <= (OTHERS => '0'); | |
171 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
172 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
172 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); |
|
173 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); | |
173 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; |
|
174 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; | |
174 | IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF; |
|
175 | IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF; | |
175 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); |
|
176 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); | |
176 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); |
|
177 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); | |
177 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); |
|
178 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); | |
178 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); |
|
179 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); | |
179 |
|
180 | |||
180 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); |
|
181 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); | |
181 | END IF; |
|
182 | END IF; | |
182 | END PROCESS debug_info; |
|
183 | END PROCESS debug_info; | |
183 |
|
184 | |||
184 |
|
185 | |||
185 | matrix_type <= header(1 DOWNTO 0); |
|
186 | ||
186 | component_type <= header(5 DOWNTO 2); |
|
|||
187 |
|
|
187 | ||
188 |
|
|
188 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
189 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
189 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
190 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
190 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
191 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
191 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
192 | '0'; |
|
192 | '0'; | |
193 |
|
193 | |||
194 | header_check_ok <= '0' WHEN component_type = "1111" ELSE |
|
194 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
195 |
'1' WHEN component_type = "0000" AND component_type_pre = " |
|
195 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE | |
196 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
196 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
197 | '0'; |
|
197 | '0'; | |
198 |
|
198 | |||
199 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
199 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
200 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
200 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
201 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
201 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
202 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
202 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
203 | (OTHERS => '0'); |
|
203 | (OTHERS => '0'); | |
204 |
|
204 | |||
205 | ----------------------------------------------------------------------------- |
|
205 | ----------------------------------------------------------------------------- | |
206 | -- DMA control |
|
206 | -- DMA control | |
207 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
208 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
208 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
209 | BEGIN -- PROCESS DMAWriteBurst_p |
|
209 | BEGIN -- PROCESS DMAWriteBurst_p | |
210 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
210 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
211 | matrix_type <= (others => '0'); | |||
|
212 | component_type <= (others => '0'); | |||
211 | state <= IDLE; |
|
213 | state <= IDLE; | |
212 | header_ack <= '0'; |
|
214 | header_ack <= '0'; | |
213 | ready_matrix_f0_0 <= '0'; |
|
215 | ready_matrix_f0_0 <= '0'; | |
214 | ready_matrix_f0_1 <= '0'; |
|
216 | ready_matrix_f0_1 <= '0'; | |
215 | ready_matrix_f1 <= '0'; |
|
217 | ready_matrix_f1 <= '0'; | |
216 | ready_matrix_f2 <= '0'; |
|
218 | ready_matrix_f2 <= '0'; | |
217 | error_anticipating_empty_fifo <= '0'; |
|
219 | error_anticipating_empty_fifo <= '0'; | |
218 | error_bad_component_error <= '0'; |
|
220 | error_bad_component_error <= '0'; | |
219 |
component_type_pre <= " |
|
221 | component_type_pre <= "0000"; | |
220 | fifo_ren_trash <= '1'; |
|
222 | fifo_ren_trash <= '1'; | |
221 | component_send <= '0'; |
|
223 | component_send <= '0'; | |
222 | address <= (OTHERS => '0'); |
|
224 | address <= (OTHERS => '0'); | |
223 | header_select <= '0'; |
|
225 | header_select <= '0'; | |
224 | header_send <= '0'; |
|
226 | header_send <= '0'; | |
225 | header_data <= (OTHERS => '0'); |
|
227 | header_data <= (OTHERS => '0'); | |
226 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
228 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
227 |
|
229 | |||
228 | CASE state IS |
|
230 | CASE state IS | |
229 | WHEN IDLE => |
|
231 | WHEN IDLE => | |
|
232 | matrix_type <= header(1 DOWNTO 0); | |||
|
233 | --component_type <= header(5 DOWNTO 2); | |||
|
234 | ||||
230 | ready_matrix_f0_0 <= '0'; |
|
235 | ready_matrix_f0_0 <= '0'; | |
231 | ready_matrix_f0_1 <= '0'; |
|
236 | ready_matrix_f0_1 <= '0'; | |
232 | ready_matrix_f1 <= '0'; |
|
237 | ready_matrix_f1 <= '0'; | |
233 | ready_matrix_f2 <= '0'; |
|
238 | ready_matrix_f2 <= '0'; | |
234 | error_bad_component_error <= '0'; |
|
239 | error_bad_component_error <= '0'; | |
235 | header_select <= '1'; |
|
240 | header_select <= '1'; | |
236 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
241 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
|
242 | matrix_type <= header(1 DOWNTO 0); | |||
|
243 | component_type <= header(5 DOWNTO 2); | |||
|
244 | component_type_pre <= component_type; | |||
|
245 | state <= CHECK_COMPONENT_TYPE; | |||
|
246 | END IF; | |||
|
247 | ||||
|
248 | WHEN CHECK_COMPONENT_TYPE => | |||
237 | IF header_check_ok = '1' THEN |
|
249 | IF header_check_ok = '1' THEN | |
238 | header_data <= header; |
|
|||
239 | component_type_pre <= header(5 DOWNTO 2); |
|
|||
240 | header_ack <= '1'; |
|
250 | header_ack <= '1'; | |
241 | -- |
|
251 | -- | |
242 | header_send <= '1'; |
|
252 | header_send <= '1'; | |
243 | IF component_type = "0000" THEN |
|
253 | IF component_type = "0000" THEN | |
244 | address <= address_matrix; |
|
254 | address <= address_matrix; | |
245 | END IF; |
|
255 | END IF; | |
246 | header_data <= header; |
|
256 | header_data <= header; | |
247 | -- |
|
257 | -- | |
248 | state <= WAIT_HEADER_ACK; |
|
258 | state <= WAIT_HEADER_ACK; | |
249 | ELSE |
|
259 | ELSE | |
250 | error_bad_component_error <= '1'; |
|
260 | error_bad_component_error <= '1'; | |
251 |
component_type_pre <= " |
|
261 | component_type_pre <= "0000"; | |
252 | header_ack <= '1'; |
|
262 | header_ack <= '1'; | |
253 | state <= TRASH_FIFO; |
|
263 | state <= TRASH_FIFO; | |
254 | END IF; |
|
264 | END IF; | |
255 | END IF; |
|
265 | ||
256 |
|
266 | |||
257 | WHEN TRASH_FIFO => |
|
267 | WHEN TRASH_FIFO => | |
|
268 | header_ack <= '0'; | |||
258 | error_bad_component_error <= '0'; |
|
269 | error_bad_component_error <= '0'; | |
259 | error_anticipating_empty_fifo <= '0'; |
|
270 | error_anticipating_empty_fifo <= '0'; | |
260 | IF fifo_empty = '1' THEN |
|
271 | IF fifo_empty = '1' THEN | |
261 | state <= IDLE; |
|
272 | state <= IDLE; | |
262 | fifo_ren_trash <= '1'; |
|
273 | fifo_ren_trash <= '1'; | |
263 | ELSE |
|
274 | ELSE | |
264 | fifo_ren_trash <= '0'; |
|
275 | fifo_ren_trash <= '0'; | |
265 | END IF; |
|
276 | END IF; | |
266 |
|
277 | |||
267 | WHEN WAIT_HEADER_ACK => |
|
278 | WHEN WAIT_HEADER_ACK => | |
|
279 | header_ack <= '0'; | |||
268 | header_send <= '0'; |
|
280 | header_send <= '0'; | |
269 | IF header_send_ko = '1' THEN |
|
281 | IF header_send_ko = '1' THEN | |
270 | state <= TRASH_FIFO; |
|
282 | state <= TRASH_FIFO; | |
271 | error_anticipating_empty_fifo <= '1'; |
|
283 | error_anticipating_empty_fifo <= '1'; | |
272 | -- TODO : error sending header |
|
284 | -- TODO : error sending header | |
273 | ELSIF header_send_ok = '1' THEN |
|
285 | ELSIF header_send_ok = '1' THEN | |
274 | header_select <= '0'; |
|
286 | header_select <= '0'; | |
275 | state <= SEND_DATA; |
|
287 | state <= SEND_DATA; | |
276 | address <= address + 4; |
|
288 | address <= address + 4; | |
277 | END IF; |
|
289 | END IF; | |
278 |
|
290 | |||
279 | WHEN SEND_DATA => |
|
291 | WHEN SEND_DATA => | |
280 | IF fifo_empty = '1' THEN |
|
292 | IF fifo_empty = '1' THEN | |
281 | state <= IDLE; |
|
293 | state <= IDLE; | |
282 | IF component_type = "1110" THEN |
|
294 | IF component_type = "1110" THEN --"1110" -- JC | |
283 | CASE matrix_type IS |
|
295 | CASE matrix_type IS | |
284 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
296 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
285 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
297 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
286 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
298 | WHEN "10" => ready_matrix_f1 <= '1'; | |
287 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
299 | WHEN "11" => ready_matrix_f2 <= '1'; | |
288 | WHEN OTHERS => NULL; |
|
300 | WHEN OTHERS => NULL; | |
289 | END CASE; |
|
301 | END CASE; | |
|
302 | ||||
290 | END IF; |
|
303 | END IF; | |
291 | ELSE |
|
304 | ELSE | |
292 | component_send <= '1'; |
|
305 | component_send <= '1'; | |
293 | address <= address; |
|
306 | address <= address; | |
294 | state <= WAIT_DATA_ACK; |
|
307 | state <= WAIT_DATA_ACK; | |
295 | END IF; |
|
308 | END IF; | |
296 |
|
309 | |||
297 | WHEN WAIT_DATA_ACK => |
|
310 | WHEN WAIT_DATA_ACK => | |
298 | component_send <= '0'; |
|
311 | component_send <= '0'; | |
299 | IF component_send_ok = '1' THEN |
|
312 | IF component_send_ok = '1' THEN | |
300 | address <= address + 64; |
|
313 | address <= address + 64; | |
301 | state <= SEND_DATA; |
|
314 | state <= SEND_DATA; | |
302 | ELSIF component_send_ko = '1' THEN |
|
315 | ELSIF component_send_ko = '1' THEN | |
303 | error_anticipating_empty_fifo <= '0'; |
|
316 | error_anticipating_empty_fifo <= '0'; | |
304 | state <= TRASH_FIFO; |
|
317 | state <= TRASH_FIFO; | |
305 | END IF; |
|
318 | END IF; | |
306 |
|
319 | |||
307 | WHEN CHECK_LENGTH => |
|
320 | WHEN CHECK_LENGTH => | |
308 | state <= IDLE; |
|
321 | state <= IDLE; | |
309 | WHEN OTHERS => NULL; |
|
322 | WHEN OTHERS => NULL; | |
310 | END CASE; |
|
323 | END CASE; | |
311 |
|
324 | |||
312 | END IF; |
|
325 | END IF; | |
313 | END PROCESS DMAWriteFSM_p; |
|
326 | END PROCESS DMAWriteFSM_p; | |
314 |
|
327 | |||
315 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- | |
316 | -- SEND 1 word by DMA |
|
329 | -- SEND 1 word by DMA | |
317 | ----------------------------------------------------------------------------- |
|
330 | ----------------------------------------------------------------------------- | |
318 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
|
331 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |
319 | PORT MAP ( |
|
332 | PORT MAP ( | |
320 | HCLK => HCLK, |
|
333 | HCLK => HCLK, | |
321 | HRESETn => HRESETn, |
|
334 | HRESETn => HRESETn, | |
322 | DMAIn => header_dmai, |
|
335 | DMAIn => header_dmai, | |
323 | DMAOut => DMAOut, |
|
336 | DMAOut => DMAOut, | |
324 |
|
337 | |||
325 | send => header_send, |
|
338 | send => header_send, | |
326 | address => address, |
|
339 | address => address, | |
327 | data => header_data, |
|
340 | data => header_data, | |
328 | send_ok => header_send_ok, |
|
341 | send_ok => header_send_ok, | |
329 | send_ko => header_send_ko |
|
342 | send_ko => header_send_ko | |
330 | ); |
|
343 | ); | |
331 |
|
344 | |||
332 | ----------------------------------------------------------------------------- |
|
345 | ----------------------------------------------------------------------------- | |
333 | -- SEND 16 word by DMA (in burst mode) |
|
346 | -- SEND 16 word by DMA (in burst mode) | |
334 | ----------------------------------------------------------------------------- |
|
347 | ----------------------------------------------------------------------------- | |
335 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
|
348 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
336 | PORT MAP ( |
|
349 | PORT MAP ( | |
337 | HCLK => HCLK, |
|
350 | HCLK => HCLK, | |
338 | HRESETn => HRESETn, |
|
351 | HRESETn => HRESETn, | |
339 | DMAIn => component_dmai, |
|
352 | DMAIn => component_dmai, | |
340 | DMAOut => DMAOut, |
|
353 | DMAOut => DMAOut, | |
341 |
|
354 | |||
342 | send => component_send, |
|
355 | send => component_send, | |
343 | address => address, |
|
356 | address => address, | |
344 | data => fifo_data, |
|
357 | data => fifo_data, | |
345 | ren => component_fifo_ren, |
|
358 | ren => component_fifo_ren, | |
346 | send_ok => component_send_ok, |
|
359 | send_ok => component_send_ok, | |
347 | send_ko => component_send_ko); |
|
360 | send_ko => component_send_ko); | |
348 |
|
361 | |||
349 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; |
|
362 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; | |
350 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; |
|
363 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; | |
351 |
|
364 | |||
352 | END Behavioral; No newline at end of file |
|
365 | END Behavioral; |
@@ -1,263 +1,264 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | -- APB_FIFO.vhd |
|
22 | -- APB_FIFO.vhd | |
23 | library ieee; |
|
23 | library ieee; | |
24 | use ieee.std_logic_1164.all; |
|
24 | use ieee.std_logic_1164.all; | |
25 | use IEEE.numeric_std.all; |
|
25 | use IEEE.numeric_std.all; | |
26 | library techmap; |
|
26 | library techmap; | |
27 | use techmap.gencomp.all; |
|
27 | use techmap.gencomp.all; | |
28 | library grlib; |
|
28 | library grlib; | |
29 | use grlib.amba.all; |
|
29 | use grlib.amba.all; | |
30 | use grlib.stdlib.all; |
|
30 | use grlib.stdlib.all; | |
31 | use grlib.devices.all; |
|
31 | use grlib.devices.all; | |
32 | library lpp; |
|
32 | library lpp; | |
33 | use lpp.lpp_amba.all; |
|
33 | use lpp.lpp_amba.all; | |
34 | use lpp.apb_devices_list.all; |
|
34 | use lpp.apb_devices_list.all; | |
35 | use lpp.lpp_memory.all; |
|
35 | use lpp.lpp_memory.all; | |
36 |
|
36 | use lpp.iir_filter.all; | ||
37 |
|
37 | |||
38 | entity APB_FIFO is |
|
38 | entity APB_FIFO is | |
39 | generic ( |
|
39 | generic ( | |
40 | tech : integer := apa3; |
|
40 | tech : integer := apa3; | |
41 | pindex : integer := 0; |
|
41 | pindex : integer := 0; | |
42 | paddr : integer := 0; |
|
42 | paddr : integer := 0; | |
43 | pmask : integer := 16#fff#; |
|
43 | pmask : integer := 16#fff#; | |
44 | pirq : integer := 0; |
|
44 | pirq : integer := 0; | |
45 | abits : integer := 8; |
|
45 | abits : integer := 8; | |
46 | FifoCnt : integer := 2; |
|
46 | FifoCnt : integer := 2; | |
47 | Data_sz : integer := 16; |
|
47 | Data_sz : integer := 16; | |
48 | Addr_sz : integer := 9; |
|
48 | Addr_sz : integer := 9; | |
49 | Enable_ReUse : std_logic := '0'; |
|
49 | Enable_ReUse : std_logic := '0'; | |
|
50 | Mem_use : integer := use_RAM; | |||
50 | R : integer := 1; |
|
51 | R : integer := 1; | |
51 | W : integer := 1 |
|
52 | W : integer := 1 | |
52 | ); |
|
53 | ); | |
53 | port ( |
|
54 | port ( | |
54 | clk : in std_logic; --! Horloge du composant |
|
55 | clk : in std_logic; --! Horloge du composant | |
55 | rst : in std_logic; --! Reset general du composant |
|
56 | rst : in std_logic; --! Reset general du composant | |
56 | rclk : in std_logic; |
|
57 | rclk : in std_logic; | |
57 | wclk : in std_logic; |
|
58 | wclk : in std_logic; | |
58 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
59 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
59 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire |
|
60 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |
60 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire |
|
61 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |
61 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide |
|
62 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide | |
62 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine |
|
63 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine | |
63 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e |
|
64 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e | |
64 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie |
|
65 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |
65 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) |
|
66 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) | |
66 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) |
|
67 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
67 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
68 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
68 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
69 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
69 | ); |
|
70 | ); | |
70 | end entity; |
|
71 | end entity; | |
71 |
|
72 | |||
72 | architecture ar_APB_FIFO of APB_FIFO is |
|
73 | architecture ar_APB_FIFO of APB_FIFO is | |
73 |
|
74 | |||
74 | constant REVISION : integer := 1; |
|
75 | constant REVISION : integer := 1; | |
75 |
|
76 | |||
76 | constant pconfig : apb_config_type := ( |
|
77 | constant pconfig : apb_config_type := ( | |
77 | 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0), |
|
78 | 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0), | |
78 | 1 => apb_iobar(paddr, pmask)); |
|
79 | 1 => apb_iobar(paddr, pmask)); | |
79 |
|
80 | |||
80 | type FIFO_ctrlr_Reg is record |
|
81 | type FIFO_ctrlr_Reg is record | |
81 | FIFO_Ctrl : std_logic_vector(31 downto 0); |
|
82 | FIFO_Ctrl : std_logic_vector(31 downto 0); | |
82 | FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0); |
|
83 | FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0); | |
83 | FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0); |
|
84 | FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0); | |
84 | end record; |
|
85 | end record; | |
85 |
|
86 | |||
86 | type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg; |
|
87 | type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg; | |
87 | type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); |
|
88 | type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); | |
88 | type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); |
|
89 | type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); | |
89 |
|
90 | |||
90 | signal Rec : FIFO_ctrlr_Reg_Vec; |
|
91 | signal Rec : FIFO_ctrlr_Reg_Vec; | |
91 | signal PRdata : std_logic_vector(31 downto 0); |
|
92 | signal PRdata : std_logic_vector(31 downto 0); | |
92 | signal FIFO_ID : std_logic_vector(31 downto 0); |
|
93 | signal FIFO_ID : std_logic_vector(31 downto 0); | |
93 | signal autoloaded : std_logic_vector(FifoCnt-1 downto 0); |
|
94 | signal autoloaded : std_logic_vector(FifoCnt-1 downto 0); | |
94 | signal sFull : std_logic_vector(FifoCnt-1 downto 0); |
|
95 | signal sFull : std_logic_vector(FifoCnt-1 downto 0); | |
95 | signal sEmpty : std_logic_vector(FifoCnt-1 downto 0); |
|
96 | signal sEmpty : std_logic_vector(FifoCnt-1 downto 0); | |
96 | signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0); |
|
97 | signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0); | |
97 | signal sWen : std_logic_vector(FifoCnt-1 downto 0); |
|
98 | signal sWen : std_logic_vector(FifoCnt-1 downto 0); | |
98 | signal sRen : std_logic_vector(FifoCnt-1 downto 0); |
|
99 | signal sRen : std_logic_vector(FifoCnt-1 downto 0); | |
99 | signal sRclk : std_logic; |
|
100 | signal sRclk : std_logic; | |
100 | signal sWclk : std_logic; |
|
101 | signal sWclk : std_logic; | |
101 | signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0); |
|
102 | signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0); | |
102 | signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0); |
|
103 | signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0); | |
103 | signal sRDATA : fifodatabus; |
|
104 | signal sRDATA : fifodatabus; | |
104 | signal sWDATA : fifodatabus; |
|
105 | signal sWDATA : fifodatabus; | |
105 | signal sWADDR : fifoaddressbus; |
|
106 | signal sWADDR : fifoaddressbus; | |
106 | signal sRADDR : fifoaddressbus; |
|
107 | signal sRADDR : fifoaddressbus; | |
107 | signal sReUse : std_logic_vector(FifoCnt-1 downto 0); |
|
108 | signal sReUse : std_logic_vector(FifoCnt-1 downto 0); | |
108 | signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); |
|
109 | signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); | |
109 |
|
110 | |||
110 | signal regDataValid : std_logic_vector(FifoCnt-1 downto 0); |
|
111 | signal regDataValid : std_logic_vector(FifoCnt-1 downto 0); | |
111 | signal regData : fifodatabus; |
|
112 | signal regData : fifodatabus; | |
112 | signal regREN : std_logic_vector(FifoCnt-1 downto 0); |
|
113 | signal regREN : std_logic_vector(FifoCnt-1 downto 0); | |
113 |
|
114 | |||
114 | type state_t is (idle,Read); |
|
115 | type state_t is (idle,Read); | |
115 | signal fiforeadfsmst : state_t; |
|
116 | signal fiforeadfsmst : state_t; | |
116 |
|
117 | |||
117 | begin |
|
118 | begin | |
118 |
|
119 | |||
119 | FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4)); |
|
120 | FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4)); | |
120 | FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8)); |
|
121 | FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8)); | |
121 | FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8)); |
|
122 | FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8)); | |
122 |
|
123 | |||
123 |
|
124 | |||
124 | Writeint : if W /= 0 generate |
|
125 | Writeint : if W /= 0 generate | |
125 | FIFO_ID(4) <= '1'; |
|
126 | FIFO_ID(4) <= '1'; | |
126 | sWen <= sWen_APB; |
|
127 | sWen <= sWen_APB; | |
127 | sReUse <= sReUse_APB; |
|
128 | sReUse <= sReUse_APB; | |
128 | sWclk <= clk; |
|
129 | sWclk <= clk; | |
129 | Wrapb: for i in 0 to FifoCnt-1 generate |
|
130 | Wrapb: for i in 0 to FifoCnt-1 generate | |
130 | sWDATA(i) <= Rec(i).FIFO_Wdata; |
|
131 | sWDATA(i) <= Rec(i).FIFO_Wdata; | |
131 | end generate; |
|
132 | end generate; | |
132 | end generate; |
|
133 | end generate; | |
133 |
|
134 | |||
134 | Writeext : if W = 0 generate |
|
135 | Writeext : if W = 0 generate | |
135 | FIFO_ID(4) <= '0'; |
|
136 | FIFO_ID(4) <= '0'; | |
136 | sWen <= WEN; |
|
137 | sWen <= WEN; | |
137 | sReUse <= ReUse; |
|
138 | sReUse <= ReUse; | |
138 | sWclk <= Wclk; |
|
139 | sWclk <= Wclk; | |
139 | Wrext: for i in 0 to FifoCnt-1 generate |
|
140 | Wrext: for i in 0 to FifoCnt-1 generate | |
140 | sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); |
|
141 | sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); | |
141 | end generate; |
|
142 | end generate; | |
142 | end generate; |
|
143 | end generate; | |
143 |
|
144 | |||
144 | Readint : if R /= 0 generate |
|
145 | Readint : if R /= 0 generate | |
145 | FIFO_ID(5) <= '1'; |
|
146 | FIFO_ID(5) <= '1'; | |
146 | sRen <= sRen_APB; |
|
147 | sRen <= sRen_APB; | |
147 | srclk <= clk; |
|
148 | srclk <= clk; | |
148 | Rdapb: for i in 0 to FifoCnt-1 generate |
|
149 | Rdapb: for i in 0 to FifoCnt-1 generate | |
149 | Rec(i).FIFO_Rdata <= sRDATA(i); |
|
150 | Rec(i).FIFO_Rdata <= sRDATA(i); | |
150 | end generate; |
|
151 | end generate; | |
151 | end generate; |
|
152 | end generate; | |
152 |
|
153 | |||
153 | Readext : if R = 0 generate |
|
154 | Readext : if R = 0 generate | |
154 | FIFO_ID(5) <= '0'; |
|
155 | FIFO_ID(5) <= '0'; | |
155 | sRen <= REN; |
|
156 | sRen <= REN; | |
156 | srclk <= rclk; |
|
157 | srclk <= rclk; | |
157 | Drext: for i in 0 to FifoCnt-1 generate |
|
158 | Drext: for i in 0 to FifoCnt-1 generate | |
158 | RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i); |
|
159 | RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i); | |
159 | end generate; |
|
160 | end generate; | |
160 | end generate; |
|
161 | end generate; | |
161 |
|
162 | |||
162 | ctrlregs: for i in 0 to FifoCnt-1 generate |
|
163 | ctrlregs: for i in 0 to FifoCnt-1 generate | |
163 | RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); |
|
164 | RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); | |
164 | WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); |
|
165 | WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); | |
165 | Rec(i).FIFO_Ctrl(16) <= sFull(i); |
|
166 | Rec(i).FIFO_Ctrl(16) <= sFull(i); | |
166 | sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); |
|
167 | sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); | |
167 | Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; |
|
168 | Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; | |
168 | Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; |
|
169 | Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; | |
169 | Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i); |
|
170 | Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i); | |
170 | Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); |
|
171 | Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); | |
171 | end generate; |
|
172 | end generate; | |
172 |
|
173 | |||
173 | Empty <= sEmpty; |
|
174 | Empty <= sEmpty; | |
174 | Full <= sFull; |
|
175 | Full <= sFull; | |
175 |
|
176 | |||
176 | fifos: for i in 0 to FifoCnt-1 generate |
|
177 | fifos: for i in 0 to FifoCnt-1 generate | |
177 | FIFO0 : lpp_fifo |
|
178 | FIFO0 : lpp_fifo | |
178 | generic map (tech,Enable_ReUse,Data_sz,Addr_sz) |
|
179 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
179 | port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); |
|
180 | port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); | |
180 | end generate; |
|
181 | end generate; | |
181 |
|
182 | |||
182 | process(rst,clk) |
|
183 | process(rst,clk) | |
183 | begin |
|
184 | begin | |
184 | if(rst='0')then |
|
185 | if(rst='0')then | |
185 | rstloop1: for i in 0 to FifoCnt-1 loop |
|
186 | rstloop1: for i in 0 to FifoCnt-1 loop | |
186 | Rec(i).FIFO_Wdata <= (others => '0'); |
|
187 | Rec(i).FIFO_Wdata <= (others => '0'); | |
187 | Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse |
|
188 | Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse | |
188 | sWen_APB(i) <= '1'; |
|
189 | sWen_APB(i) <= '1'; | |
189 | end loop; |
|
190 | end loop; | |
190 | elsif(clk'event and clk='1')then |
|
191 | elsif(clk'event and clk='1')then | |
191 |
|
192 | |||
192 | --APB Write OP |
|
193 | --APB Write OP | |
193 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
194 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
194 | writelp: for i in 0 to FifoCnt-1 loop |
|
195 | writelp: for i in 0 to FifoCnt-1 loop | |
195 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then |
|
196 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then | |
196 | Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1); |
|
197 | Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1); | |
197 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then |
|
198 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then | |
198 | Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); |
|
199 | Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); | |
199 | sWen_APB(i) <= '0'; |
|
200 | sWen_APB(i) <= '0'; | |
200 | end if; |
|
201 | end if; | |
201 | end loop; |
|
202 | end loop; | |
202 | else |
|
203 | else | |
203 | sWen_APB <= (others =>'1'); |
|
204 | sWen_APB <= (others =>'1'); | |
204 | end if; |
|
205 | end if; | |
205 |
|
206 | |||
206 | --APB Read OP |
|
207 | --APB Read OP | |
207 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
208 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
208 | if(apbi.paddr(abits-1 downto 2)="000000") then |
|
209 | if(apbi.paddr(abits-1 downto 2)="000000") then | |
209 | PRdata <= FIFO_ID; |
|
210 | PRdata <= FIFO_ID; | |
210 | else |
|
211 | else | |
211 | readlp: for i in 0 to FifoCnt-1 loop |
|
212 | readlp: for i in 0 to FifoCnt-1 loop | |
212 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then |
|
213 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then | |
213 | PRdata <= Rec(i).FIFO_Ctrl; |
|
214 | PRdata <= Rec(i).FIFO_Ctrl; | |
214 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then |
|
215 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then | |
215 | PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; |
|
216 | PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; | |
216 | end if; |
|
217 | end if; | |
217 | end loop; |
|
218 | end loop; | |
218 | end if; |
|
219 | end if; | |
219 | end if; |
|
220 | end if; | |
220 | end if; |
|
221 | end if; | |
221 |
|
222 | |||
222 | apbo.pconfig <= pconfig; |
|
223 | apbo.pconfig <= pconfig; | |
223 |
|
224 | |||
224 | end process; |
|
225 | end process; | |
225 | apbo.prdata <= PRdata when apbi.penable = '1'; |
|
226 | apbo.prdata <= PRdata when apbi.penable = '1'; | |
226 |
|
227 | |||
227 | process(rst,clk) |
|
228 | process(rst,clk) | |
228 | begin |
|
229 | begin | |
229 | if(rst='0')then |
|
230 | if(rst='0')then | |
230 | fiforeadfsmst <= idle; |
|
231 | fiforeadfsmst <= idle; | |
231 | rstloop: for i in 0 to FifoCnt-1 loop |
|
232 | rstloop: for i in 0 to FifoCnt-1 loop | |
232 | sRen_APB(i) <= '1'; |
|
233 | sRen_APB(i) <= '1'; | |
233 | autoloaded(i) <= '1'; |
|
234 | autoloaded(i) <= '1'; | |
234 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); |
|
235 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); | |
235 | end loop; |
|
236 | end loop; | |
236 | elsif clk'event and clk = '1' then |
|
237 | elsif clk'event and clk = '1' then | |
237 | sEmpty_d <= sEmpty; |
|
238 | sEmpty_d <= sEmpty; | |
238 | case fiforeadfsmst is |
|
239 | case fiforeadfsmst is | |
239 | when idle => |
|
240 | when idle => | |
240 | idlelp: for i in 0 to FifoCnt-1 loop |
|
241 | idlelp: for i in 0 to FifoCnt-1 loop | |
241 | if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then |
|
242 | if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then | |
242 | if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then |
|
243 | if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then | |
243 | autoloaded(i) <= '0'; |
|
244 | autoloaded(i) <= '0'; | |
244 | else |
|
245 | else | |
245 | autoloaded(i) <= '1'; |
|
246 | autoloaded(i) <= '1'; | |
246 | end if; |
|
247 | end if; | |
247 | sRen_APB(i) <= '0'; |
|
248 | sRen_APB(i) <= '0'; | |
248 | fiforeadfsmst <= read; |
|
249 | fiforeadfsmst <= read; | |
249 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); |
|
250 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); | |
250 | else |
|
251 | else | |
251 | sRen_APB(i) <= '1'; |
|
252 | sRen_APB(i) <= '1'; | |
252 | end if; |
|
253 | end if; | |
253 | end loop; |
|
254 | end loop; | |
254 | when read => |
|
255 | when read => | |
255 | sRen_APB <= (others => '1'); |
|
256 | sRen_APB <= (others => '1'); | |
256 | fiforeadfsmst <= idle; |
|
257 | fiforeadfsmst <= idle; | |
257 | when others => |
|
258 | when others => | |
258 | fiforeadfsmst <= idle; |
|
259 | fiforeadfsmst <= idle; | |
259 | end case; |
|
260 | end case; | |
260 | end if; |
|
261 | end if; | |
261 | end process; |
|
262 | end process; | |
262 |
|
263 | |||
263 | end ar_APB_FIFO; No newline at end of file |
|
264 | end ar_APB_FIFO; |
@@ -1,64 +1,66 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.lpp_memory.all; |
|
26 | use lpp.lpp_memory.all; | |
|
27 | use lpp.iir_filter.all; | |||
27 | library techmap; |
|
28 | library techmap; | |
28 | use techmap.gencomp.all; |
|
29 | use techmap.gencomp.all; | |
29 |
|
30 | |||
30 | entity lppFIFOxN is |
|
31 | entity lppFIFOxN is | |
31 | generic( |
|
32 | generic( | |
32 | tech : integer := 0; |
|
33 | tech : integer := 0; | |
|
34 | Mem_use : integer := use_RAM; | |||
33 | Data_sz : integer range 1 to 32 := 8; |
|
35 | Data_sz : integer range 1 to 32 := 8; | |
34 | Addr_sz : integer range 1 to 32 := 8; |
|
36 | Addr_sz : integer range 1 to 32 := 8; | |
35 | FifoCnt : integer := 1; |
|
37 | FifoCnt : integer := 1; | |
36 | Enable_ReUse : std_logic := '0' |
|
38 | Enable_ReUse : std_logic := '0' | |
37 | ); |
|
39 | ); | |
38 | port( |
|
40 | port( | |
39 | rst : in std_logic; |
|
41 | rst : in std_logic; | |
40 | wclk : in std_logic; |
|
42 | wclk : in std_logic; | |
41 | rclk : in std_logic; |
|
43 | rclk : in std_logic; | |
42 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
44 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
43 | wen : in std_logic_vector(FifoCnt-1 downto 0); |
|
45 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
44 | ren : in std_logic_vector(FifoCnt-1 downto 0); |
|
46 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
45 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
|
47 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
46 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
|
48 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
47 | full : out std_logic_vector(FifoCnt-1 downto 0); |
|
49 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
48 | empty : out std_logic_vector(FifoCnt-1 downto 0) |
|
50 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
49 | ); |
|
51 | ); | |
50 | end entity; |
|
52 | end entity; | |
51 |
|
53 | |||
52 |
|
54 | |||
53 | architecture ar_lppFIFOxN of lppFIFOxN is |
|
55 | architecture ar_lppFIFOxN of lppFIFOxN is | |
54 |
|
56 | |||
55 | begin |
|
57 | begin | |
56 |
|
58 | |||
57 | fifos: for i in 0 to FifoCnt-1 generate |
|
59 | fifos: for i in 0 to FifoCnt-1 generate | |
58 | FIFO0 : lpp_fifo |
|
60 | FIFO0 : lpp_fifo | |
59 | generic map (tech,Enable_ReUse,Data_sz,Addr_sz) |
|
61 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
60 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); |
|
62 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |
61 | end generate; |
|
63 | end generate; | |
62 |
|
64 | |||
63 | end architecture; |
|
65 | end architecture; | |
64 |
|
66 |
@@ -1,174 +1,180 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.lpp_memory.all; |
|
26 | use lpp.lpp_memory.all; | |
27 | use lpp.iir_filter.all; |
|
27 | use lpp.iir_filter.all; | |
28 | library techmap; |
|
28 | library techmap; | |
29 | use techmap.gencomp.all; |
|
29 | use techmap.gencomp.all; | |
30 |
|
30 | |||
31 | entity lpp_fifo is |
|
31 | entity lpp_fifo is | |
32 | generic( |
|
32 | generic( | |
33 | tech : integer := 0; |
|
33 | tech : integer := 0; | |
|
34 | Mem_use : integer := use_RAM; | |||
34 | Enable_ReUse : std_logic := '0'; |
|
35 | Enable_ReUse : std_logic := '0'; | |
35 | DataSz : integer range 1 to 32 := 8; |
|
36 | DataSz : integer range 1 to 32 := 8; | |
36 | abits : integer range 2 to 12 := 8 |
|
37 | abits : integer range 2 to 12 := 8 | |
37 | ); |
|
38 | ); | |
38 | port( |
|
39 | port( | |
39 | rstn : in std_logic; |
|
40 | rstn : in std_logic; | |
40 | ReUse : in std_logic; |
|
41 | ReUse : in std_logic; | |
41 | rclk : in std_logic; |
|
42 | rclk : in std_logic; | |
42 | ren : in std_logic; |
|
43 | ren : in std_logic; | |
43 | rdata : out std_logic_vector(DataSz-1 downto 0); |
|
44 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
44 | empty : out std_logic; |
|
45 | empty : out std_logic; | |
45 | raddr : out std_logic_vector(abits-1 downto 0); |
|
46 | raddr : out std_logic_vector(abits-1 downto 0); | |
46 | wclk : in std_logic; |
|
47 | wclk : in std_logic; | |
47 | wen : in std_logic; |
|
48 | wen : in std_logic; | |
48 | wdata : in std_logic_vector(DataSz-1 downto 0); |
|
49 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
49 | full : out std_logic; |
|
50 | full : out std_logic; | |
50 | waddr : out std_logic_vector(abits-1 downto 0) |
|
51 | waddr : out std_logic_vector(abits-1 downto 0) | |
51 | ); |
|
52 | ); | |
52 | end entity; |
|
53 | end entity; | |
53 |
|
54 | |||
54 |
|
55 | |||
55 | architecture ar_lpp_fifo of lpp_fifo is |
|
56 | architecture ar_lpp_fifo of lpp_fifo is | |
56 |
|
57 | |||
57 | signal sFull : std_logic; |
|
58 | signal sFull : std_logic; | |
58 | signal sFull_s : std_logic; |
|
59 | signal sFull_s : std_logic; | |
59 | signal sEmpty_s : std_logic; |
|
60 | signal sEmpty_s : std_logic; | |
60 |
|
61 | |||
61 | signal sEmpty : std_logic; |
|
62 | signal sEmpty : std_logic; | |
62 | signal sREN : std_logic; |
|
63 | signal sREN : std_logic; | |
63 | signal sWEN : std_logic; |
|
64 | signal sWEN : std_logic; | |
64 | signal sRE : std_logic; |
|
65 | signal sRE : std_logic; | |
65 | signal sWE : std_logic; |
|
66 | signal sWE : std_logic; | |
66 |
|
67 | |||
67 | signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); |
|
68 | signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |
68 | signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); |
|
69 | signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |
69 | signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); |
|
70 | signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |
70 | signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); |
|
71 | signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); | |
71 |
|
72 | |||
72 | begin |
|
73 | begin | |
73 |
|
74 | |||
74 | --================================================================================== |
|
75 | --================================================================================== | |
75 | -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\ |
|
76 | -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\ | |
76 | -- A l'inverse de RAM_CEL !!! |
|
77 | -- A l'inverse de RAM_CEL !!! | |
77 | --================================================================================== |
|
78 | --================================================================================== | |
|
79 | memRAM : IF Mem_use = use_RAM GENERATE | |||
78 | SRAM : syncram_2p |
|
80 | SRAM : syncram_2p | |
79 | generic map(tech,abits,DataSz) |
|
81 | generic map(tech,abits,DataSz) | |
80 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); |
|
82 | port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); | |
|
83 | END GENERATE; | |||
81 | --================================================================================== |
|
84 | --================================================================================== | |
82 | --RAM0: entity work.RAM_CEL |
|
85 | memCEL : IF Mem_use = use_CEL GENERATE | |
83 | -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); |
|
86 | CRAM : RAM_CEL | |
|
87 | generic map(DataSz,abits) | |||
|
88 | port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); | |||
|
89 | END GENERATE; | |||
84 | --================================================================================== |
|
90 | --================================================================================== | |
85 |
|
91 | |||
86 | --============================= |
|
92 | --============================= | |
87 | -- Read section |
|
93 | -- Read section | |
88 | --============================= |
|
94 | --============================= | |
89 | sREN <= REN or sEmpty; |
|
95 | sREN <= REN or sEmpty; | |
90 | sRE <= not sREN; |
|
96 | sRE <= not sREN; | |
91 |
|
97 | |||
92 | sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else |
|
98 | sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else | |
93 | '1' when sEmpty = '1' and Wen = '1' else |
|
99 | '1' when sEmpty = '1' and Wen = '1' else | |
94 | '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else |
|
100 | '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else | |
95 | '0'; |
|
101 | '0'; | |
96 |
|
102 | |||
97 | Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1); |
|
103 | Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1); | |
98 |
|
104 | |||
99 | process (rclk,rstn) |
|
105 | process (rclk,rstn) | |
100 | begin |
|
106 | begin | |
101 | if(rstn='0')then |
|
107 | if(rstn='0')then | |
102 | Raddr_vect <= (others =>'0'); |
|
108 | Raddr_vect <= (others =>'0'); | |
103 | sempty <= '1'; |
|
109 | sempty <= '1'; | |
104 | elsif(rclk'event and rclk='1')then |
|
110 | elsif(rclk'event and rclk='1')then | |
105 | sEmpty <= sempty_s; |
|
111 | sEmpty <= sempty_s; | |
106 |
|
112 | |||
107 | if(sREN='0' and sempty = '0')then |
|
113 | if(sREN='0' and sempty = '0')then | |
108 | Raddr_vect <= Raddr_vect_s; |
|
114 | Raddr_vect <= Raddr_vect_s; | |
109 | end if; |
|
115 | end if; | |
110 |
|
116 | |||
111 | end if; |
|
117 | end if; | |
112 | end process; |
|
118 | end process; | |
113 |
|
119 | |||
114 | --============================= |
|
120 | --============================= | |
115 | -- Write section |
|
121 | -- Write section | |
116 | --============================= |
|
122 | --============================= | |
117 | sWEN <= WEN or sFull; |
|
123 | sWEN <= WEN or sFull; | |
118 | sWE <= not sWEN; |
|
124 | sWE <= not sWEN; | |
119 |
|
125 | |||
120 | sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else |
|
126 | sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else | |
121 | '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else |
|
127 | '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else | |
122 | '1' when sFull = '1' and REN = '1' else |
|
128 | '1' when sFull = '1' and REN = '1' else | |
123 | '0'; |
|
129 | '0'; | |
124 |
|
130 | |||
125 | Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1); |
|
131 | Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1); | |
126 |
|
132 | |||
127 | process (wclk,rstn) |
|
133 | process (wclk,rstn) | |
128 | begin |
|
134 | begin | |
129 | if(rstn='0')then |
|
135 | if(rstn='0')then | |
130 | Waddr_vect <= (others =>'0'); |
|
136 | Waddr_vect <= (others =>'0'); | |
131 | sfull <= '0'; |
|
137 | sfull <= '0'; | |
132 | elsif(wclk'event and wclk='1')then |
|
138 | elsif(wclk'event and wclk='1')then | |
133 | sfull <= sfull_s; |
|
139 | sfull <= sfull_s; | |
134 |
|
140 | |||
135 | if(sWEN='0' and sfull='0')then |
|
141 | if(sWEN='0' and sfull='0')then | |
136 | Waddr_vect <= Waddr_vect_s; |
|
142 | Waddr_vect <= Waddr_vect_s; | |
137 | end if; |
|
143 | end if; | |
138 |
|
144 | |||
139 | end if; |
|
145 | end if; | |
140 | end process; |
|
146 | end process; | |
141 |
|
147 | |||
142 |
|
148 | |||
143 | full <= sFull_s; |
|
149 | full <= sFull_s; | |
144 | empty <= sEmpty_s; |
|
150 | empty <= sEmpty_s; | |
145 | waddr <= Waddr_vect; |
|
151 | waddr <= Waddr_vect; | |
146 | raddr <= Raddr_vect; |
|
152 | raddr <= Raddr_vect; | |
147 |
|
153 | |||
148 | end architecture; |
|
154 | end architecture; | |
149 |
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155 | |||
150 |
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@@ -1,177 +1,163 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
|
29 | use lpp.iir_filter.all; | |||
29 | library gaisler; |
|
30 | library gaisler; | |
30 | use gaisler.misc.all; |
|
31 | use gaisler.misc.all; | |
31 | use gaisler.memctrl.all; |
|
32 | use gaisler.memctrl.all; | |
32 | library techmap; |
|
33 | library techmap; | |
33 | use techmap.gencomp.all; |
|
34 | use techmap.gencomp.all; | |
34 |
|
35 | |||
35 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on |
|
36 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | |
36 |
|
37 | |||
37 | package lpp_memory is |
|
38 | package lpp_memory is | |
38 |
|
39 | |||
39 | component APB_FIFO is |
|
40 | component APB_FIFO is | |
40 | generic ( |
|
41 | generic ( | |
41 | tech : integer := apa3; |
|
42 | tech : integer := apa3; | |
42 | pindex : integer := 0; |
|
43 | pindex : integer := 0; | |
43 | paddr : integer := 0; |
|
44 | paddr : integer := 0; | |
44 | pmask : integer := 16#fff#; |
|
45 | pmask : integer := 16#fff#; | |
45 | pirq : integer := 0; |
|
46 | pirq : integer := 0; | |
46 | abits : integer := 8; |
|
47 | abits : integer := 8; | |
47 | FifoCnt : integer := 2; |
|
48 | FifoCnt : integer := 2; | |
48 | Data_sz : integer := 16; |
|
49 | Data_sz : integer := 16; | |
49 | Addr_sz : integer := 9; |
|
50 | Addr_sz : integer := 9; | |
50 | Enable_ReUse : std_logic := '0'; |
|
51 | Enable_ReUse : std_logic := '0'; | |
|
52 | Mem_use : integer := use_RAM; | |||
51 | R : integer := 1; |
|
53 | R : integer := 1; | |
52 | W : integer := 1 |
|
54 | W : integer := 1 | |
53 | ); |
|
55 | ); | |
54 | port ( |
|
56 | port ( | |
55 | clk : in std_logic; --! Horloge du composant |
|
57 | clk : in std_logic; --! Horloge du composant | |
56 | rst : in std_logic; --! Reset general du composant |
|
58 | rst : in std_logic; --! Reset general du composant | |
57 | rclk : in std_logic; |
|
59 | rclk : in std_logic; | |
58 | wclk : in std_logic; |
|
60 | wclk : in std_logic; | |
59 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
61 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
60 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire |
|
62 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |
61 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire |
|
63 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |
62 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide |
|
64 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide | |
63 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine |
|
65 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine | |
64 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e |
|
66 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e | |
65 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie |
|
67 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |
66 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) |
|
68 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) | |
67 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) |
|
69 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
68 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
70 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
69 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
71 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
70 | ); |
|
72 | ); | |
71 | end component; |
|
73 | end component; | |
72 |
|
74 | |||
73 |
|
75 | |||
74 | component lpp_fifo is |
|
76 | component lpp_fifo is | |
75 | generic( |
|
77 | generic( | |
76 | tech : integer := 0; |
|
78 | tech : integer := 0; | |
|
79 | Mem_use : integer := use_RAM; | |||
77 | Enable_ReUse : std_logic := '0'; |
|
80 | Enable_ReUse : std_logic := '0'; | |
78 | DataSz : integer range 1 to 32 := 8; |
|
81 | DataSz : integer range 1 to 32 := 8; | |
79 | abits : integer range 2 to 12 := 8 |
|
82 | abits : integer range 2 to 12 := 8 | |
80 | ); |
|
83 | ); | |
81 | port( |
|
84 | port( | |
82 | rstn : in std_logic; |
|
85 | rstn : in std_logic; | |
83 | ReUse : in std_logic; --27/01/12 |
|
86 | ReUse : in std_logic; --27/01/12 | |
84 | rclk : in std_logic; |
|
87 | rclk : in std_logic; | |
85 | ren : in std_logic; |
|
88 | ren : in std_logic; | |
86 | rdata : out std_logic_vector(DataSz-1 downto 0); |
|
89 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
87 | empty : out std_logic; |
|
90 | empty : out std_logic; | |
88 | raddr : out std_logic_vector(abits-1 downto 0); |
|
91 | raddr : out std_logic_vector(abits-1 downto 0); | |
89 | wclk : in std_logic; |
|
92 | wclk : in std_logic; | |
90 | wen : in std_logic; |
|
93 | wen : in std_logic; | |
91 | wdata : in std_logic_vector(DataSz-1 downto 0); |
|
94 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
92 | full : out std_logic; |
|
95 | full : out std_logic; | |
93 | waddr : out std_logic_vector(abits-1 downto 0) |
|
96 | waddr : out std_logic_vector(abits-1 downto 0) | |
94 | ); |
|
97 | ); | |
95 | end component; |
|
98 | end component; | |
96 |
|
99 | |||
97 |
|
100 | |||
98 | component lppFIFOxN is |
|
101 | component lppFIFOxN is | |
99 | generic( |
|
102 | generic( | |
100 | tech : integer := 0; |
|
103 | tech : integer := 0; | |
|
104 | Mem_use : integer := use_RAM; | |||
101 | Data_sz : integer range 1 to 32 := 8; |
|
105 | Data_sz : integer range 1 to 32 := 8; | |
102 | Addr_sz : integer range 1 to 32 := 8; |
|
106 | Addr_sz : integer range 1 to 32 := 8; | |
103 | FifoCnt : integer := 1; |
|
107 | FifoCnt : integer := 1; | |
104 | Enable_ReUse : std_logic := '0' |
|
108 | Enable_ReUse : std_logic := '0' | |
105 | ); |
|
109 | ); | |
106 | port( |
|
110 | port( | |
107 | rst : in std_logic; |
|
111 | rst : in std_logic; | |
108 | wclk : in std_logic; |
|
112 | wclk : in std_logic; | |
109 | rclk : in std_logic; |
|
113 | rclk : in std_logic; | |
110 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); |
|
114 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
111 | wen : in std_logic_vector(FifoCnt-1 downto 0); |
|
115 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
112 | ren : in std_logic_vector(FifoCnt-1 downto 0); |
|
116 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
113 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
|
117 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
114 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); |
|
118 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
115 | full : out std_logic_vector(FifoCnt-1 downto 0); |
|
119 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
116 | empty : out std_logic_vector(FifoCnt-1 downto 0) |
|
120 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
117 | ); |
|
121 | ); | |
118 | end component; |
|
122 | end component; | |
119 |
|
123 | |||
120 |
component |
|
124 | component FillFifo is | |
121 | generic( |
|
125 | generic( | |
122 | tech : integer := 0; |
|
|||
123 |
Data_sz |
|
126 | Data_sz : integer range 1 to 32 := 16; | |
124 |
|
|
127 | Fifo_cnt : integer range 1 to 8 := 5 | |
125 | Enable_ReUse : std_logic := '0' |
|
|||
126 | ); |
|
128 | ); | |
127 | port( |
|
129 | port( | |
128 | rst : in std_logic; |
|
|||
129 | wclk : in std_logic; |
|
|||
130 | rclk : in std_logic; |
|
|||
131 | ReUse : in std_logic_vector(4 downto 0); |
|
|||
132 | wen : in std_logic_vector(4 downto 0); |
|
|||
133 | ren : in std_logic_vector(4 downto 0); |
|
|||
134 | wdata : in std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
135 | rdata : out std_logic_vector((5*Data_sz)-1 downto 0); |
|
|||
136 | full : out std_logic_vector(4 downto 0); |
|
|||
137 | empty : out std_logic_vector(4 downto 0) |
|
|||
138 | ); |
|
|||
139 | end component; |
|
|||
140 |
|
||||
141 | component Bridge is |
|
|||
142 | port( |
|
|||
143 |
|
|
130 | clk : in std_logic; | |
144 |
|
|
131 | raz : in std_logic; | |
145 | EmptyUp : in std_logic; |
|
132 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |
146 | FullDwn : in std_logic; |
|
133 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |
147 | WriteDwn : out std_logic; |
|
134 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |
148 | ReadUp : out std_logic |
|
|||
149 | ); |
|
135 | ); | |
150 | end component; |
|
136 | end component; | |
151 |
|
137 | |||
152 | component ssram_plugin is |
|
138 | component ssram_plugin is | |
153 | generic (tech : integer := 0); |
|
139 | generic (tech : integer := 0); | |
154 | port |
|
140 | port | |
155 | ( |
|
141 | ( | |
156 | clk : in std_logic; |
|
142 | clk : in std_logic; | |
157 | mem_ctrlr_o : in memory_out_type; |
|
143 | mem_ctrlr_o : in memory_out_type; | |
158 | SSRAM_CLK : out std_logic; |
|
144 | SSRAM_CLK : out std_logic; | |
159 | nBWa : out std_logic; |
|
145 | nBWa : out std_logic; | |
160 | nBWb : out std_logic; |
|
146 | nBWb : out std_logic; | |
161 | nBWc : out std_logic; |
|
147 | nBWc : out std_logic; | |
162 | nBWd : out std_logic; |
|
148 | nBWd : out std_logic; | |
163 | nBWE : out std_logic; |
|
149 | nBWE : out std_logic; | |
164 | nADSC : out std_logic; |
|
150 | nADSC : out std_logic; | |
165 | nADSP : out std_logic; |
|
151 | nADSP : out std_logic; | |
166 | nADV : out std_logic; |
|
152 | nADV : out std_logic; | |
167 | nGW : out std_logic; |
|
153 | nGW : out std_logic; | |
168 | nCE1 : out std_logic; |
|
154 | nCE1 : out std_logic; | |
169 | CE2 : out std_logic; |
|
155 | CE2 : out std_logic; | |
170 | nCE3 : out std_logic; |
|
156 | nCE3 : out std_logic; | |
171 | nOE : out std_logic; |
|
157 | nOE : out std_logic; | |
172 | MODE : out std_logic; |
|
158 | MODE : out std_logic; | |
173 | ZZ : out std_logic |
|
159 | ZZ : out std_logic | |
174 | ); |
|
160 | ); | |
175 | end component; |
|
161 | end component; | |
176 |
|
162 | |||
177 | end; |
|
163 | end; |
@@ -1,303 +1,304 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | LIBRARY lpp; |
|
3 | LIBRARY lpp; | |
4 | USE lpp.lpp_ad_conv.ALL; |
|
4 | USE lpp.lpp_ad_conv.ALL; | |
5 | USE lpp.iir_filter.ALL; |
|
5 | USE lpp.iir_filter.ALL; | |
6 | USE lpp.FILTERcfg.ALL; |
|
6 | USE lpp.FILTERcfg.ALL; | |
7 | USE lpp.lpp_memory.ALL; |
|
7 | USE lpp.lpp_memory.ALL; | |
8 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
8 | USE lpp.lpp_top_lfr_pkg.ALL; | |
9 | LIBRARY techmap; |
|
9 | LIBRARY techmap; | |
10 | USE techmap.gencomp.ALL; |
|
10 | USE techmap.gencomp.ALL; | |
11 |
|
11 | |||
12 | ENTITY lpp_top_acq IS |
|
12 | ENTITY lpp_top_acq IS | |
13 | GENERIC( |
|
13 | GENERIC( | |
14 | tech : INTEGER := 0 |
|
14 | tech : INTEGER := 0; | |
|
15 | Mem_use : integer := use_RAM | |||
15 | ); |
|
16 | ); | |
16 | PORT ( |
|
17 | PORT ( | |
17 | -- ADS7886 |
|
18 | -- ADS7886 | |
18 | cnv_run : IN STD_LOGIC; |
|
19 | cnv_run : IN STD_LOGIC; | |
19 | cnv : OUT STD_LOGIC; |
|
20 | cnv : OUT STD_LOGIC; | |
20 | sck : OUT STD_LOGIC; |
|
21 | sck : OUT STD_LOGIC; | |
21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
22 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
22 | -- |
|
23 | -- | |
23 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
24 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
24 | cnv_rstn : IN STD_LOGIC; |
|
25 | cnv_rstn : IN STD_LOGIC; | |
25 | -- |
|
26 | -- | |
26 | clk : IN STD_LOGIC; -- 25 MHz |
|
27 | clk : IN STD_LOGIC; -- 25 MHz | |
27 | rstn : IN STD_LOGIC; |
|
28 | rstn : IN STD_LOGIC; | |
28 | -- |
|
29 | -- | |
29 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
31 | -- |
|
32 | -- | |
32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
34 | -- |
|
35 | -- | |
35 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
36 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
37 | -- |
|
38 | -- | |
38 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
39 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
39 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
|
40 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
40 | ); |
|
41 | ); | |
41 | END lpp_top_acq; |
|
42 | END lpp_top_acq; | |
42 |
|
43 | |||
43 | ARCHITECTURE tb OF lpp_top_acq IS |
|
44 | ARCHITECTURE tb OF lpp_top_acq IS | |
44 |
|
45 | |||
45 | COMPONENT Downsampling |
|
46 | COMPONENT Downsampling | |
46 | GENERIC ( |
|
47 | GENERIC ( | |
47 | ChanelCount : INTEGER; |
|
48 | ChanelCount : INTEGER; | |
48 | SampleSize : INTEGER; |
|
49 | SampleSize : INTEGER; | |
49 | DivideParam : INTEGER); |
|
50 | DivideParam : INTEGER); | |
50 | PORT ( |
|
51 | PORT ( | |
51 | clk : IN STD_LOGIC; |
|
52 | clk : IN STD_LOGIC; | |
52 | rstn : IN STD_LOGIC; |
|
53 | rstn : IN STD_LOGIC; | |
53 | sample_in_val : IN STD_LOGIC; |
|
54 | sample_in_val : IN STD_LOGIC; | |
54 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
55 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
55 | sample_out_val : OUT STD_LOGIC; |
|
56 | sample_out_val : OUT STD_LOGIC; | |
56 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
57 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
57 | END COMPONENT; |
|
58 | END COMPONENT; | |
58 |
|
59 | |||
59 | ----------------------------------------------------------------------------- |
|
60 | ----------------------------------------------------------------------------- | |
60 | CONSTANT ChanelCount : INTEGER := 8; |
|
61 | CONSTANT ChanelCount : INTEGER := 8; | |
61 | CONSTANT ncycle_cnv_high : INTEGER := 79; |
|
62 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
62 | CONSTANT ncycle_cnv : INTEGER := 500; |
|
63 | CONSTANT ncycle_cnv : INTEGER := 500; | |
63 |
|
64 | |||
64 | ----------------------------------------------------------------------------- |
|
65 | ----------------------------------------------------------------------------- | |
65 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); |
|
66 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
66 | SIGNAL sample_val : STD_LOGIC; |
|
67 | SIGNAL sample_val : STD_LOGIC; | |
67 | SIGNAL sample_val_delay : STD_LOGIC; |
|
68 | SIGNAL sample_val_delay : STD_LOGIC; | |
68 | ----------------------------------------------------------------------------- |
|
69 | ----------------------------------------------------------------------------- | |
69 | CONSTANT Coef_SZ : INTEGER := 9; |
|
70 | CONSTANT Coef_SZ : INTEGER := 9; | |
70 | CONSTANT CoefCntPerCel : INTEGER := 6; |
|
71 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
71 | CONSTANT CoefPerCel : INTEGER := 5; |
|
72 | CONSTANT CoefPerCel : INTEGER := 5; | |
72 | CONSTANT Cels_count : INTEGER := 5; |
|
73 | CONSTANT Cels_count : INTEGER := 5; | |
73 |
|
74 | |||
74 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
75 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
75 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
76 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
76 | -- |
|
77 | -- | |
77 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
78 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
78 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
79 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
79 | -- |
|
80 | -- | |
80 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; |
|
81 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |
81 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
82 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
82 | ----------------------------------------------------------------------------- |
|
83 | ----------------------------------------------------------------------------- | |
83 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
84 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
84 | SIGNAL sample_downsampling_out_val : STD_LOGIC; |
|
85 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |
85 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
86 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
86 | -- |
|
87 | -- | |
87 | SIGNAL sample_f0_val : STD_LOGIC; |
|
88 | SIGNAL sample_f0_val : STD_LOGIC; | |
88 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
89 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
89 | ----------------------------------------------------------------------------- |
|
90 | ----------------------------------------------------------------------------- | |
90 | SIGNAL sample_f1_val : STD_LOGIC; |
|
91 | SIGNAL sample_f1_val : STD_LOGIC; | |
91 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
92 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
92 | -- |
|
93 | -- | |
93 | SIGNAL sample_f2_val : STD_LOGIC; |
|
94 | SIGNAL sample_f2_val : STD_LOGIC; | |
94 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
95 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
95 | -- |
|
96 | -- | |
96 | SIGNAL sample_f3_val : STD_LOGIC; |
|
97 | SIGNAL sample_f3_val : STD_LOGIC; | |
97 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
98 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
98 |
|
99 | |||
99 | BEGIN |
|
100 | BEGIN | |
100 |
|
101 | |||
101 | -- component instantiation |
|
102 | -- component instantiation | |
102 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
103 | DIGITAL_acquisition : AD7688_drvr |
|
104 | DIGITAL_acquisition : AD7688_drvr | |
104 | GENERIC MAP ( |
|
105 | GENERIC MAP ( | |
105 | ChanelCount => ChanelCount, |
|
106 | ChanelCount => ChanelCount, | |
106 | ncycle_cnv_high => ncycle_cnv_high, |
|
107 | ncycle_cnv_high => ncycle_cnv_high, | |
107 | ncycle_cnv => ncycle_cnv) |
|
108 | ncycle_cnv => ncycle_cnv) | |
108 | PORT MAP ( |
|
109 | PORT MAP ( | |
109 | cnv_clk => cnv_clk, -- |
|
110 | cnv_clk => cnv_clk, -- | |
110 | cnv_rstn => cnv_rstn, -- |
|
111 | cnv_rstn => cnv_rstn, -- | |
111 | cnv_run => cnv_run, -- |
|
112 | cnv_run => cnv_run, -- | |
112 | cnv => cnv, -- |
|
113 | cnv => cnv, -- | |
113 | clk => clk, -- |
|
114 | clk => clk, -- | |
114 | rstn => rstn, -- |
|
115 | rstn => rstn, -- | |
115 | sck => sck, -- |
|
116 | sck => sck, -- | |
116 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
|
117 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
117 | sample => sample, |
|
118 | sample => sample, | |
118 | sample_val => sample_val); |
|
119 | sample_val => sample_val); | |
119 |
|
120 | |||
120 | ----------------------------------------------------------------------------- |
|
121 | ----------------------------------------------------------------------------- | |
121 |
|
122 | |||
122 | PROCESS (clk, rstn) |
|
123 | PROCESS (clk, rstn) | |
123 | BEGIN -- PROCESS |
|
124 | BEGIN -- PROCESS | |
124 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
125 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
125 | sample_val_delay <= '0'; |
|
126 | sample_val_delay <= '0'; | |
126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
127 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
127 | sample_val_delay <= sample_val; |
|
128 | sample_val_delay <= sample_val; | |
128 | END IF; |
|
129 | END IF; | |
129 | END PROCESS; |
|
130 | END PROCESS; | |
130 |
|
131 | |||
131 | ----------------------------------------------------------------------------- |
|
132 | ----------------------------------------------------------------------------- | |
132 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
133 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
133 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
134 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
134 | sample_filter_in(i, j) <= sample(i)(j); |
|
135 | sample_filter_in(i, j) <= sample(i)(j); | |
135 | END GENERATE; |
|
136 | END GENERATE; | |
136 |
|
137 | |||
137 | sample_filter_in(i, 16) <= sample(i)(15); |
|
138 | sample_filter_in(i, 16) <= sample(i)(15); | |
138 | sample_filter_in(i, 17) <= sample(i)(15); |
|
139 | sample_filter_in(i, 17) <= sample(i)(15); | |
139 | END GENERATE; |
|
140 | END GENERATE; | |
140 |
|
141 | |||
141 | coefs_v2 <= CoefsInitValCst_v2; |
|
142 | coefs_v2 <= CoefsInitValCst_v2; | |
142 |
|
143 | |||
143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
144 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
144 | GENERIC MAP ( |
|
145 | GENERIC MAP ( | |
145 | tech => 0, |
|
146 | tech => 0, | |
146 |
Mem_use => use |
|
147 | Mem_use => Mem_use, | |
147 | Sample_SZ => 18, |
|
148 | Sample_SZ => 18, | |
148 | Coef_SZ => Coef_SZ, |
|
149 | Coef_SZ => Coef_SZ, | |
149 | Coef_Nb => 25, -- TODO |
|
150 | Coef_Nb => 25, -- TODO | |
150 | Coef_sel_SZ => 5, -- TODO |
|
151 | Coef_sel_SZ => 5, -- TODO | |
151 | Cels_count => Cels_count, |
|
152 | Cels_count => Cels_count, | |
152 | ChanelsCount => ChanelCount) |
|
153 | ChanelsCount => ChanelCount) | |
153 | PORT MAP ( |
|
154 | PORT MAP ( | |
154 | rstn => rstn, |
|
155 | rstn => rstn, | |
155 | clk => clk, |
|
156 | clk => clk, | |
156 | virg_pos => 7, |
|
157 | virg_pos => 7, | |
157 | coefs => coefs_v2, |
|
158 | coefs => coefs_v2, | |
158 | sample_in_val => sample_val_delay, |
|
159 | sample_in_val => sample_val_delay, | |
159 | sample_in => sample_filter_in, |
|
160 | sample_in => sample_filter_in, | |
160 | sample_out_val => sample_filter_v2_out_val, |
|
161 | sample_out_val => sample_filter_v2_out_val, | |
161 | sample_out => sample_filter_v2_out); |
|
162 | sample_out => sample_filter_v2_out); | |
162 |
|
163 | |||
163 | ----------------------------------------------------------------------------- |
|
164 | ----------------------------------------------------------------------------- | |
164 | PROCESS (clk, rstn) |
|
165 | PROCESS (clk, rstn) | |
165 | BEGIN -- PROCESS |
|
166 | BEGIN -- PROCESS | |
166 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
167 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
167 | sample_filter_v2_out_r_val <= '0'; |
|
168 | sample_filter_v2_out_r_val <= '0'; | |
168 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
|
169 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
169 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP |
|
170 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |
170 | sample_filter_v2_out_r(I, J) <= '0'; |
|
171 | sample_filter_v2_out_r(I, J) <= '0'; | |
171 | END LOOP rst_all_bits; |
|
172 | END LOOP rst_all_bits; | |
172 | END LOOP rst_all_chanel; |
|
173 | END LOOP rst_all_chanel; | |
173 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
174 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
174 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; |
|
175 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |
175 | IF sample_filter_v2_out_val = '1' THEN |
|
176 | IF sample_filter_v2_out_val = '1' THEN | |
176 | sample_filter_v2_out_r <= sample_filter_v2_out; |
|
177 | sample_filter_v2_out_r <= sample_filter_v2_out; | |
177 | END IF; |
|
178 | END IF; | |
178 | END IF; |
|
179 | END IF; | |
179 | END PROCESS; |
|
180 | END PROCESS; | |
180 |
|
181 | |||
181 | ----------------------------------------------------------------------------- |
|
182 | ----------------------------------------------------------------------------- | |
182 | -- F0 -- @24.576 kHz |
|
183 | -- F0 -- @24.576 kHz | |
183 | ----------------------------------------------------------------------------- |
|
184 | ----------------------------------------------------------------------------- | |
184 | Downsampling_f0 : Downsampling |
|
185 | Downsampling_f0 : Downsampling | |
185 | GENERIC MAP ( |
|
186 | GENERIC MAP ( | |
186 | ChanelCount => ChanelCount, |
|
187 | ChanelCount => ChanelCount, | |
187 | SampleSize => 18, |
|
188 | SampleSize => 18, | |
188 | DivideParam => 4) |
|
189 | DivideParam => 4) | |
189 | PORT MAP ( |
|
190 | PORT MAP ( | |
190 | clk => clk, |
|
191 | clk => clk, | |
191 | rstn => rstn, |
|
192 | rstn => rstn, | |
192 | sample_in_val => sample_filter_v2_out_val , |
|
193 | sample_in_val => sample_filter_v2_out_val , | |
193 | sample_in => sample_filter_v2_out, |
|
194 | sample_in => sample_filter_v2_out, | |
194 | sample_out_val => sample_f0_val, |
|
195 | sample_out_val => sample_f0_val, | |
195 | sample_out => sample_f0); |
|
196 | sample_out => sample_f0); | |
196 |
|
197 | |||
197 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
198 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
198 | sample_f0_wdata(I) <= sample_f0(0, I); |
|
199 | sample_f0_wdata(I) <= sample_f0(0, I); | |
199 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); |
|
200 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |
200 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); |
|
201 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |
201 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); |
|
202 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | |
202 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); |
|
203 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |
203 | END GENERATE all_bit_sample_f0; |
|
204 | END GENERATE all_bit_sample_f0; | |
204 |
|
205 | |||
205 | sample_f0_wen <= NOT(sample_f0_val) & |
|
206 | sample_f0_wen <= NOT(sample_f0_val) & | |
206 | NOT(sample_f0_val) & |
|
207 | NOT(sample_f0_val) & | |
207 | NOT(sample_f0_val) & |
|
208 | NOT(sample_f0_val) & | |
208 | NOT(sample_f0_val) & |
|
209 | NOT(sample_f0_val) & | |
209 | NOT(sample_f0_val); |
|
210 | NOT(sample_f0_val); | |
210 |
|
211 | |||
211 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
212 | -- F1 -- @4096 Hz |
|
213 | -- F1 -- @4096 Hz | |
213 | ----------------------------------------------------------------------------- |
|
214 | ----------------------------------------------------------------------------- | |
214 | Downsampling_f1 : Downsampling |
|
215 | Downsampling_f1 : Downsampling | |
215 | GENERIC MAP ( |
|
216 | GENERIC MAP ( | |
216 | ChanelCount => ChanelCount, |
|
217 | ChanelCount => ChanelCount, | |
217 | SampleSize => 18, |
|
218 | SampleSize => 18, | |
218 | DivideParam => 6) |
|
219 | DivideParam => 6) | |
219 | PORT MAP ( |
|
220 | PORT MAP ( | |
220 | clk => clk, |
|
221 | clk => clk, | |
221 | rstn => rstn, |
|
222 | rstn => rstn, | |
222 | sample_in_val => sample_f0_val , |
|
223 | sample_in_val => sample_f0_val , | |
223 | sample_in => sample_f0, |
|
224 | sample_in => sample_f0, | |
224 | sample_out_val => sample_f1_val, |
|
225 | sample_out_val => sample_f1_val, | |
225 | sample_out => sample_f1); |
|
226 | sample_out => sample_f1); | |
226 |
|
227 | |||
227 | sample_f1_wen <= NOT(sample_f1_val) & |
|
228 | sample_f1_wen <= NOT(sample_f1_val) & | |
228 | NOT(sample_f1_val) & |
|
229 | NOT(sample_f1_val) & | |
229 | NOT(sample_f1_val) & |
|
230 | NOT(sample_f1_val) & | |
230 | NOT(sample_f1_val) & |
|
231 | NOT(sample_f1_val) & | |
231 | NOT(sample_f1_val); |
|
232 | NOT(sample_f1_val); | |
232 |
|
233 | |||
233 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
234 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
234 | sample_f1_wdata(I) <= sample_f1(0, I); |
|
235 | sample_f1_wdata(I) <= sample_f1(0, I); | |
235 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); |
|
236 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |
236 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); |
|
237 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |
237 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); |
|
238 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |
238 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); |
|
239 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | |
239 | END GENERATE all_bit_sample_f1; |
|
240 | END GENERATE all_bit_sample_f1; | |
240 |
|
241 | |||
241 | ----------------------------------------------------------------------------- |
|
242 | ----------------------------------------------------------------------------- | |
242 | -- F2 -- @16 Hz |
|
243 | -- F2 -- @16 Hz | |
243 | ----------------------------------------------------------------------------- |
|
244 | ----------------------------------------------------------------------------- | |
244 | Downsampling_f2 : Downsampling |
|
245 | Downsampling_f2 : Downsampling | |
245 | GENERIC MAP ( |
|
246 | GENERIC MAP ( | |
246 | ChanelCount => ChanelCount, |
|
247 | ChanelCount => ChanelCount, | |
247 | SampleSize => 18, |
|
248 | SampleSize => 18, | |
248 | DivideParam => 96) |
|
249 | DivideParam => 96) | |
249 | PORT MAP ( |
|
250 | PORT MAP ( | |
250 | clk => clk, |
|
251 | clk => clk, | |
251 | rstn => rstn, |
|
252 | rstn => rstn, | |
252 | sample_in_val => sample_f1_val , |
|
253 | sample_in_val => sample_f1_val , | |
253 | sample_in => sample_f1, |
|
254 | sample_in => sample_f1, | |
254 | sample_out_val => sample_f2_val, |
|
255 | sample_out_val => sample_f2_val, | |
255 | sample_out => sample_f2); |
|
256 | sample_out => sample_f2); | |
256 |
|
257 | |||
257 | sample_f2_wen <= NOT(sample_f2_val) & |
|
258 | sample_f2_wen <= NOT(sample_f2_val) & | |
258 | NOT(sample_f2_val) & |
|
259 | NOT(sample_f2_val) & | |
259 | NOT(sample_f2_val) & |
|
260 | NOT(sample_f2_val) & | |
260 | NOT(sample_f2_val) & |
|
261 | NOT(sample_f2_val) & | |
261 | NOT(sample_f2_val); |
|
262 | NOT(sample_f2_val); | |
262 |
|
263 | |||
263 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
264 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
264 | sample_f2_wdata(I) <= sample_f2(0, I); |
|
265 | sample_f2_wdata(I) <= sample_f2(0, I); | |
265 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); |
|
266 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |
266 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); |
|
267 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |
267 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); |
|
268 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |
268 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); |
|
269 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |
269 | END GENERATE all_bit_sample_f2; |
|
270 | END GENERATE all_bit_sample_f2; | |
270 |
|
271 | |||
271 | ----------------------------------------------------------------------------- |
|
272 | ----------------------------------------------------------------------------- | |
272 | -- F3 -- @256 Hz |
|
273 | -- F3 -- @256 Hz | |
273 | ----------------------------------------------------------------------------- |
|
274 | ----------------------------------------------------------------------------- | |
274 | Downsampling_f3 : Downsampling |
|
275 | Downsampling_f3 : Downsampling | |
275 | GENERIC MAP ( |
|
276 | GENERIC MAP ( | |
276 | ChanelCount => ChanelCount, |
|
277 | ChanelCount => ChanelCount, | |
277 | SampleSize => 18, |
|
278 | SampleSize => 18, | |
278 | DivideParam => 256) |
|
279 | DivideParam => 256) | |
279 | PORT MAP ( |
|
280 | PORT MAP ( | |
280 | clk => clk, |
|
281 | clk => clk, | |
281 | rstn => rstn, |
|
282 | rstn => rstn, | |
282 | sample_in_val => sample_f0_val , |
|
283 | sample_in_val => sample_f0_val , | |
283 | sample_in => sample_f0, |
|
284 | sample_in => sample_f0, | |
284 | sample_out_val => sample_f3_val, |
|
285 | sample_out_val => sample_f3_val, | |
285 | sample_out => sample_f3); |
|
286 | sample_out => sample_f3); | |
286 |
|
287 | |||
287 | sample_f3_wen <= (NOT sample_f3_val) & |
|
288 | sample_f3_wen <= (NOT sample_f3_val) & | |
288 | (NOT sample_f3_val) & |
|
289 | (NOT sample_f3_val) & | |
289 | (NOT sample_f3_val) & |
|
290 | (NOT sample_f3_val) & | |
290 | (NOT sample_f3_val) & |
|
291 | (NOT sample_f3_val) & | |
291 | (NOT sample_f3_val); |
|
292 | (NOT sample_f3_val); | |
292 |
|
293 | |||
293 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
294 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
294 | sample_f3_wdata(I) <= sample_f3(0, I); |
|
295 | sample_f3_wdata(I) <= sample_f3(0, I); | |
295 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); |
|
296 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |
296 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); |
|
297 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |
297 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); |
|
298 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |
298 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); |
|
299 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |
299 | END GENERATE all_bit_sample_f3; |
|
300 | END GENERATE all_bit_sample_f3; | |
300 |
|
301 | |||
301 |
|
302 | |||
302 |
|
303 | |||
303 | END tb; |
|
304 | END tb; |
@@ -1,279 +1,280 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_top_lfr_pkg IS |
|
15 | PACKAGE lpp_top_lfr_pkg IS | |
16 |
|
16 | |||
17 | COMPONENT lpp_top_acq |
|
17 | COMPONENT lpp_top_acq | |
18 | GENERIC( |
|
18 | GENERIC( | |
19 | tech : INTEGER := 0 |
|
19 | tech : INTEGER := 0; | |
|
20 | Mem_use : integer := use_RAM | |||
20 | ); |
|
21 | ); | |
21 | PORT ( |
|
22 | PORT ( | |
22 | -- ADS7886 |
|
23 | -- ADS7886 | |
23 | cnv_run : IN STD_LOGIC; |
|
24 | cnv_run : IN STD_LOGIC; | |
24 | cnv : OUT STD_LOGIC; |
|
25 | cnv : OUT STD_LOGIC; | |
25 | sck : OUT STD_LOGIC; |
|
26 | sck : OUT STD_LOGIC; | |
26 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
27 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
27 | -- |
|
28 | -- | |
28 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
29 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
29 | cnv_rstn : IN STD_LOGIC; |
|
30 | cnv_rstn : IN STD_LOGIC; | |
30 | -- |
|
31 | -- | |
31 | clk : IN STD_LOGIC; -- 25 MHz |
|
32 | clk : IN STD_LOGIC; -- 25 MHz | |
32 | rstn : IN STD_LOGIC; |
|
33 | rstn : IN STD_LOGIC; | |
33 | -- |
|
34 | -- | |
34 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
35 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
36 | -- |
|
37 | -- | |
37 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
38 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
39 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
39 | -- |
|
40 | -- | |
40 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
41 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
41 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
42 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
42 | -- |
|
43 | -- | |
43 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
44 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
44 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
|
45 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
45 | ); |
|
46 | ); | |
46 | END COMPONENT; |
|
47 | END COMPONENT; | |
47 |
|
48 | |||
48 | COMPONENT lpp_top_apbreg |
|
49 | COMPONENT lpp_top_apbreg | |
49 | GENERIC ( |
|
50 | GENERIC ( | |
50 | nb_burst_available_size : INTEGER; |
|
51 | nb_burst_available_size : INTEGER; | |
51 | nb_snapshot_param_size : INTEGER; |
|
52 | nb_snapshot_param_size : INTEGER; | |
52 | delta_snapshot_size : INTEGER; |
|
53 | delta_snapshot_size : INTEGER; | |
53 | delta_f2_f0_size : INTEGER; |
|
54 | delta_f2_f0_size : INTEGER; | |
54 | delta_f2_f1_size : INTEGER; |
|
55 | delta_f2_f1_size : INTEGER; | |
55 | pindex : INTEGER; |
|
56 | pindex : INTEGER; | |
56 | paddr : INTEGER; |
|
57 | paddr : INTEGER; | |
57 | pmask : INTEGER; |
|
58 | pmask : INTEGER; | |
58 | pirq : INTEGER); |
|
59 | pirq : INTEGER); | |
59 | PORT ( |
|
60 | PORT ( | |
60 | HCLK : IN STD_ULOGIC; |
|
61 | HCLK : IN STD_ULOGIC; | |
61 | HRESETn : IN STD_ULOGIC; |
|
62 | HRESETn : IN STD_ULOGIC; | |
62 | apbi : IN apb_slv_in_type; |
|
63 | apbi : IN apb_slv_in_type; | |
63 | apbo : OUT apb_slv_out_type; |
|
64 | apbo : OUT apb_slv_out_type; | |
64 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
65 | ready_matrix_f0_0 : IN STD_LOGIC; | |
65 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
66 | ready_matrix_f0_1 : IN STD_LOGIC; | |
66 | ready_matrix_f1 : IN STD_LOGIC; |
|
67 | ready_matrix_f1 : IN STD_LOGIC; | |
67 | ready_matrix_f2 : IN STD_LOGIC; |
|
68 | ready_matrix_f2 : IN STD_LOGIC; | |
68 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
69 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
69 | error_bad_component_error : IN STD_LOGIC; |
|
70 | error_bad_component_error : IN STD_LOGIC; | |
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
72 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
72 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
73 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
73 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
74 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
74 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
75 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
75 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
76 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
76 | status_error_bad_component_error : OUT STD_LOGIC; |
|
77 | status_error_bad_component_error : OUT STD_LOGIC; | |
77 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
78 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
78 | config_active_interruption_onError : OUT STD_LOGIC; |
|
79 | config_active_interruption_onError : OUT STD_LOGIC; | |
79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
84 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
84 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
85 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
85 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
86 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
86 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
87 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
87 | data_shaping_BW : OUT STD_LOGIC; |
|
88 | data_shaping_BW : OUT STD_LOGIC; | |
88 | data_shaping_SP0 : OUT STD_LOGIC; |
|
89 | data_shaping_SP0 : OUT STD_LOGIC; | |
89 | data_shaping_SP1 : OUT STD_LOGIC; |
|
90 | data_shaping_SP1 : OUT STD_LOGIC; | |
90 | data_shaping_R0 : OUT STD_LOGIC; |
|
91 | data_shaping_R0 : OUT STD_LOGIC; | |
91 | data_shaping_R1 : OUT STD_LOGIC; |
|
92 | data_shaping_R1 : OUT STD_LOGIC; | |
92 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
93 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
93 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
94 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
94 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
95 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
95 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
96 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
96 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
97 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
97 | enable_f0 : OUT STD_LOGIC; |
|
98 | enable_f0 : OUT STD_LOGIC; | |
98 | enable_f1 : OUT STD_LOGIC; |
|
99 | enable_f1 : OUT STD_LOGIC; | |
99 | enable_f2 : OUT STD_LOGIC; |
|
100 | enable_f2 : OUT STD_LOGIC; | |
100 | enable_f3 : OUT STD_LOGIC; |
|
101 | enable_f3 : OUT STD_LOGIC; | |
101 | burst_f0 : OUT STD_LOGIC; |
|
102 | burst_f0 : OUT STD_LOGIC; | |
102 | burst_f1 : OUT STD_LOGIC; |
|
103 | burst_f1 : OUT STD_LOGIC; | |
103 | burst_f2 : OUT STD_LOGIC; |
|
104 | burst_f2 : OUT STD_LOGIC; | |
104 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
105 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
106 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
107 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
108 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
108 | END COMPONENT; |
|
109 | END COMPONENT; | |
109 |
|
110 | |||
110 | COMPONENT lpp_top_lfr_wf_picker |
|
111 | COMPONENT lpp_top_lfr_wf_picker | |
111 | GENERIC ( |
|
112 | GENERIC ( | |
112 | hindex : INTEGER; |
|
113 | hindex : INTEGER; | |
113 | pindex : INTEGER; |
|
114 | pindex : INTEGER; | |
114 | paddr : INTEGER; |
|
115 | paddr : INTEGER; | |
115 | pmask : INTEGER; |
|
116 | pmask : INTEGER; | |
116 | pirq : INTEGER; |
|
117 | pirq : INTEGER; | |
117 | tech : INTEGER; |
|
118 | tech : INTEGER; | |
118 | nb_burst_available_size : INTEGER; |
|
119 | nb_burst_available_size : INTEGER; | |
119 | nb_snapshot_param_size : INTEGER; |
|
120 | nb_snapshot_param_size : INTEGER; | |
120 | delta_snapshot_size : INTEGER; |
|
121 | delta_snapshot_size : INTEGER; | |
121 | delta_f2_f0_size : INTEGER; |
|
122 | delta_f2_f0_size : INTEGER; | |
122 | delta_f2_f1_size : INTEGER; |
|
123 | delta_f2_f1_size : INTEGER; | |
123 | ENABLE_FILTER : STD_LOGIC); |
|
124 | ENABLE_FILTER : STD_LOGIC); | |
124 | PORT ( |
|
125 | PORT ( | |
125 | cnv_run : IN STD_LOGIC; |
|
126 | cnv_run : IN STD_LOGIC; | |
126 | cnv : OUT STD_LOGIC; |
|
127 | cnv : OUT STD_LOGIC; | |
127 | sck : OUT STD_LOGIC; |
|
128 | sck : OUT STD_LOGIC; | |
128 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
129 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
129 | cnv_clk : IN STD_LOGIC; |
|
130 | cnv_clk : IN STD_LOGIC; | |
130 | cnv_rstn : IN STD_LOGIC; |
|
131 | cnv_rstn : IN STD_LOGIC; | |
131 | HCLK : IN STD_ULOGIC; |
|
132 | HCLK : IN STD_ULOGIC; | |
132 | HRESETn : IN STD_ULOGIC; |
|
133 | HRESETn : IN STD_ULOGIC; | |
133 | apbi : IN apb_slv_in_type; |
|
134 | apbi : IN apb_slv_in_type; | |
134 | apbo : OUT apb_slv_out_type; |
|
135 | apbo : OUT apb_slv_out_type; | |
135 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
136 | AHB_Master_In : IN AHB_Mst_In_Type; | |
136 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
137 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
137 | coarse_time_0 : IN STD_LOGIC; |
|
138 | coarse_time_0 : IN STD_LOGIC; | |
138 | data_shaping_BW : OUT STD_LOGIC); |
|
139 | data_shaping_BW : OUT STD_LOGIC); | |
139 | END COMPONENT; |
|
140 | END COMPONENT; | |
140 |
|
141 | |||
141 |
|
142 | |||
142 | COMPONENT lpp_top_lfr_wf_picker_ip |
|
143 | COMPONENT lpp_top_lfr_wf_picker_ip | |
143 | GENERIC ( |
|
144 | GENERIC ( | |
144 | hindex : INTEGER; |
|
145 | hindex : INTEGER; | |
145 | nb_burst_available_size : INTEGER; |
|
146 | nb_burst_available_size : INTEGER; | |
146 | nb_snapshot_param_size : INTEGER; |
|
147 | nb_snapshot_param_size : INTEGER; | |
147 | delta_snapshot_size : INTEGER; |
|
148 | delta_snapshot_size : INTEGER; | |
148 | delta_f2_f0_size : INTEGER; |
|
149 | delta_f2_f0_size : INTEGER; | |
149 | delta_f2_f1_size : INTEGER; |
|
150 | delta_f2_f1_size : INTEGER; | |
150 | tech : INTEGER; |
|
151 | tech : INTEGER; | |
151 | Mem_use : INTEGER); |
|
152 | Mem_use : INTEGER); | |
152 | PORT ( |
|
153 | PORT ( | |
153 | sample : IN Samples(7 DOWNTO 0); |
|
154 | sample : IN Samples(7 DOWNTO 0); | |
154 | sample_val : IN STD_LOGIC; |
|
155 | sample_val : IN STD_LOGIC; | |
155 | cnv_clk : IN STD_LOGIC; |
|
156 | cnv_clk : IN STD_LOGIC; | |
156 | cnv_rstn : IN STD_LOGIC; |
|
157 | cnv_rstn : IN STD_LOGIC; | |
157 | clk : IN STD_LOGIC; |
|
158 | clk : IN STD_LOGIC; | |
158 | rstn : IN STD_LOGIC; |
|
159 | rstn : IN STD_LOGIC; | |
159 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
160 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
160 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
161 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
161 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
162 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
162 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
163 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
163 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
164 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
164 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
165 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
165 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
166 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
166 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
167 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
167 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
168 | AHB_Master_In : IN AHB_Mst_In_Type; | |
168 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
169 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
169 | coarse_time_0 : IN STD_LOGIC; |
|
170 | coarse_time_0 : IN STD_LOGIC; | |
170 | data_shaping_SP0 : IN STD_LOGIC; |
|
171 | data_shaping_SP0 : IN STD_LOGIC; | |
171 | data_shaping_SP1 : IN STD_LOGIC; |
|
172 | data_shaping_SP1 : IN STD_LOGIC; | |
172 | data_shaping_R0 : IN STD_LOGIC; |
|
173 | data_shaping_R0 : IN STD_LOGIC; | |
173 | data_shaping_R1 : IN STD_LOGIC; |
|
174 | data_shaping_R1 : IN STD_LOGIC; | |
174 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
175 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
175 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
176 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
176 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
177 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
177 | enable_f0 : IN STD_LOGIC; |
|
178 | enable_f0 : IN STD_LOGIC; | |
178 | enable_f1 : IN STD_LOGIC; |
|
179 | enable_f1 : IN STD_LOGIC; | |
179 | enable_f2 : IN STD_LOGIC; |
|
180 | enable_f2 : IN STD_LOGIC; | |
180 | enable_f3 : IN STD_LOGIC; |
|
181 | enable_f3 : IN STD_LOGIC; | |
181 | burst_f0 : IN STD_LOGIC; |
|
182 | burst_f0 : IN STD_LOGIC; | |
182 | burst_f1 : IN STD_LOGIC; |
|
183 | burst_f1 : IN STD_LOGIC; | |
183 | burst_f2 : IN STD_LOGIC; |
|
184 | burst_f2 : IN STD_LOGIC; | |
184 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
185 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
185 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
186 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
186 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
188 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
188 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
189 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
189 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
190 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
190 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
191 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
194 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
194 | END COMPONENT; |
|
195 | END COMPONENT; | |
195 |
|
196 | |||
196 | COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter |
|
197 | COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter | |
197 | GENERIC ( |
|
198 | GENERIC ( | |
198 | hindex : INTEGER; |
|
199 | hindex : INTEGER; | |
199 | nb_burst_available_size : INTEGER; |
|
200 | nb_burst_available_size : INTEGER; | |
200 | nb_snapshot_param_size : INTEGER; |
|
201 | nb_snapshot_param_size : INTEGER; | |
201 | delta_snapshot_size : INTEGER; |
|
202 | delta_snapshot_size : INTEGER; | |
202 | delta_f2_f0_size : INTEGER; |
|
203 | delta_f2_f0_size : INTEGER; | |
203 | delta_f2_f1_size : INTEGER; |
|
204 | delta_f2_f1_size : INTEGER; | |
204 | tech : INTEGER); |
|
205 | tech : INTEGER); | |
205 | PORT ( |
|
206 | PORT ( | |
206 | sample : IN Samples(7 DOWNTO 0); |
|
207 | sample : IN Samples(7 DOWNTO 0); | |
207 | sample_val : IN STD_LOGIC; |
|
208 | sample_val : IN STD_LOGIC; | |
208 | cnv_clk : IN STD_LOGIC; |
|
209 | cnv_clk : IN STD_LOGIC; | |
209 | cnv_rstn : IN STD_LOGIC; |
|
210 | cnv_rstn : IN STD_LOGIC; | |
210 | clk : IN STD_LOGIC; |
|
211 | clk : IN STD_LOGIC; | |
211 | rstn : IN STD_LOGIC; |
|
212 | rstn : IN STD_LOGIC; | |
212 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
213 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
213 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
214 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
214 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
215 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
215 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
216 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
216 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
217 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
217 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
218 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
218 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
219 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
219 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
220 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
220 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
221 | AHB_Master_In : IN AHB_Mst_In_Type; | |
221 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
222 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
222 | coarse_time_0 : IN STD_LOGIC; |
|
223 | coarse_time_0 : IN STD_LOGIC; | |
223 | data_shaping_SP0 : IN STD_LOGIC; |
|
224 | data_shaping_SP0 : IN STD_LOGIC; | |
224 | data_shaping_SP1 : IN STD_LOGIC; |
|
225 | data_shaping_SP1 : IN STD_LOGIC; | |
225 | data_shaping_R0 : IN STD_LOGIC; |
|
226 | data_shaping_R0 : IN STD_LOGIC; | |
226 | data_shaping_R1 : IN STD_LOGIC; |
|
227 | data_shaping_R1 : IN STD_LOGIC; | |
227 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
228 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
228 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
229 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
229 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
230 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
230 | enable_f0 : IN STD_LOGIC; |
|
231 | enable_f0 : IN STD_LOGIC; | |
231 | enable_f1 : IN STD_LOGIC; |
|
232 | enable_f1 : IN STD_LOGIC; | |
232 | enable_f2 : IN STD_LOGIC; |
|
233 | enable_f2 : IN STD_LOGIC; | |
233 | enable_f3 : IN STD_LOGIC; |
|
234 | enable_f3 : IN STD_LOGIC; | |
234 | burst_f0 : IN STD_LOGIC; |
|
235 | burst_f0 : IN STD_LOGIC; | |
235 | burst_f1 : IN STD_LOGIC; |
|
236 | burst_f1 : IN STD_LOGIC; | |
236 | burst_f2 : IN STD_LOGIC; |
|
237 | burst_f2 : IN STD_LOGIC; | |
237 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
238 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
238 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
239 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
239 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
240 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
240 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
241 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
241 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
242 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
242 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
243 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
243 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
244 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
244 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
245 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
245 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
246 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
246 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
247 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
247 | END COMPONENT; |
|
248 | END COMPONENT; | |
248 |
|
249 | |||
249 | COMPONENT top_wf_picker |
|
250 | COMPONENT top_wf_picker | |
250 | GENERIC ( |
|
251 | GENERIC ( | |
251 | hindex : INTEGER; |
|
252 | hindex : INTEGER; | |
252 | pindex : INTEGER; |
|
253 | pindex : INTEGER; | |
253 | paddr : INTEGER; |
|
254 | paddr : INTEGER; | |
254 | pmask : INTEGER; |
|
255 | pmask : INTEGER; | |
255 | pirq : INTEGER; |
|
256 | pirq : INTEGER; | |
256 | tech : INTEGER; |
|
257 | tech : INTEGER; | |
257 | nb_burst_available_size : INTEGER; |
|
258 | nb_burst_available_size : INTEGER; | |
258 | nb_snapshot_param_size : INTEGER; |
|
259 | nb_snapshot_param_size : INTEGER; | |
259 | delta_snapshot_size : INTEGER; |
|
260 | delta_snapshot_size : INTEGER; | |
260 | delta_f2_f0_size : INTEGER; |
|
261 | delta_f2_f0_size : INTEGER; | |
261 | delta_f2_f1_size : INTEGER; |
|
262 | delta_f2_f1_size : INTEGER; | |
262 | ENABLE_FILTER : STD_LOGIC); |
|
263 | ENABLE_FILTER : STD_LOGIC); | |
263 | PORT ( |
|
264 | PORT ( | |
264 | cnv_clk : IN STD_LOGIC; |
|
265 | cnv_clk : IN STD_LOGIC; | |
265 | cnv_rstn : IN STD_LOGIC; |
|
266 | cnv_rstn : IN STD_LOGIC; | |
266 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
267 | sample_B : IN Samples14v(2 DOWNTO 0); | |
267 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
268 | sample_E : IN Samples14v(4 DOWNTO 0); | |
268 | sample_val : IN STD_LOGIC; |
|
269 | sample_val : IN STD_LOGIC; | |
269 | HCLK : IN STD_ULOGIC; |
|
270 | HCLK : IN STD_ULOGIC; | |
270 | HRESETn : IN STD_ULOGIC; |
|
271 | HRESETn : IN STD_ULOGIC; | |
271 | apbi : IN apb_slv_in_type; |
|
272 | apbi : IN apb_slv_in_type; | |
272 | apbo : OUT apb_slv_out_type; |
|
273 | apbo : OUT apb_slv_out_type; | |
273 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
274 | AHB_Master_In : IN AHB_Mst_In_Type; | |
274 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
275 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
275 | coarse_time_0 : IN STD_LOGIC; |
|
276 | coarse_time_0 : IN STD_LOGIC; | |
276 | data_shaping_BW : OUT STD_LOGIC); |
|
277 | data_shaping_BW : OUT STD_LOGIC); | |
277 | END COMPONENT; |
|
278 | END COMPONENT; | |
278 |
|
279 | |||
279 | END lpp_top_lfr_pkg; |
|
280 | END lpp_top_lfr_pkg; |
1 | NO CONTENT: file was removed |
|
NO CONTENT: file was removed |
1 | NO CONTENT: file was removed |
|
NO CONTENT: file was removed |
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