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1 -- FillFifo.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FillFifo is
7 generic(
8 Data_sz : integer range 1 to 32 := 16;
9 Fifo_cnt : integer range 1 to 8 := 5
10 );
11 port(
12 clk : in std_logic;
13 raz : in std_logic;
14 write : out std_logic_vector(Fifo_cnt-1 downto 0);
15 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
16 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
17 );
18 end entity;
19
20
21 architecture ar_FillFifo of FillFifo is
22
23 signal i : integer := 0;
24
25 type etat is (eX,e0,e00);
26 signal ect : etat;
27
28 type Tbl is array(natural range <>) of std_logic_vector(Data_sz-1 downto 0);
29
30 --constant TblA : Tbl (0 to 255) := (X"FFFF",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE",X"0000",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",
31 --X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE");
32
33 constant TblA : Tbl (0 to 255) := (X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
34 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
35 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
36
37 constant TblB : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
38 X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
39 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
40
41 constant TblC : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
42 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
43 X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
44
45 constant TblD : Tbl (0 to 255) := (X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
46 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
47 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
48
49 constant TblE : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
50 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
51 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
52
53 begin
54
55 process(clk,raz)
56 begin
57 if(raz='0')then
58 i <= 0;
59 Write <= (others => '1');
60 Reuse <= (others => '0');
61 ect <= e00;
62
63 elsif(clk'event and clk='1')then
64
65 case ect is
66
67 when e00 =>
68 Write <= (others => '0');
69 ect <= e0;
70
71 when e0 =>
72 if(i=255)then
73 Write <= (others => '1');
74 Reuse <= (others => '1');
75 ect <= eX;
76 else
77 i <= i+1;
78 ect <= e0;
79 end if;
80
81 when eX =>
82 null;
83
84 end case;
85 end if;
86 end process;
87
88 data <= TblE(i) & TblD(i) & TblC(i) & TblB(i) & TblA(i);
89
90 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -15,28 +15,35
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 entity RAM_CEL is
27 port( WD : in std_logic_vector(15 downto 0); RD : out
28 std_logic_vector(15 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
27 generic(DataSz : integer range 1 to 32 := 8;
28 abits : integer range 2 to 12 := 8);
29 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
30 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
31 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
32 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
31 33 ) ;
32 34 end RAM_CEL;
33 35
34 36
35 37
36 38 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"0000");
39 signal RD_int : std_logic_vector(15 downto 0);
39
40 constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0');
41 constant MAX : integer := 2**(abits);
42
43 type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0);
44
45 signal RAMarray : RAMarrayT:=(others => VectInit);
46 signal RD_int : std_logic_vector(DataSz-1 downto 0);
40 47
41 48 begin
42 49
@@ -46,8 +53,8 RD_int <= RAMarray(to_integer(unsigned
46 53 process(RWclk,reset)
47 54 begin
48 55 if reset = '0' then
49 RD <= (X"0000");
50 rst:for i in 0 to 255 loop
56 RD <= VectInit;
57 rst:for i in 0 to MAX-1 loop
51 58 RAMarray(i) <= (others => '0');
52 59 end loop;
53 60
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@@ -203,17 +203,15 PACKAGE iir_filter IS
203 203 ) ;
204 204 END COMPONENT;
205 205
206 COMPONENT RAM_CEL
207 GENERIC (
208 Sample_SZ : INTEGER);
209 PORT (
210 WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
211 RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
212 WEN, REN : IN STD_LOGIC;
213 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
214 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
215 RWCLK, RESET : IN STD_LOGIC);
216 END COMPONENT;
206 COMPONENT RAM_CEL is
207 generic(DataSz : integer range 1 to 32 := 8;
208 abits : integer range 2 to 12 := 8);
209 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
210 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
211 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
212 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
213 ) ;
214 end COMPONENT;
217 215
218 216 COMPONENT RAM_CEL_N
219 217 GENERIC (
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@@ -57,21 +57,29 signal Matrix_Param : std_logic_vect
57 57 signal Write_reg : std_logic;
58 58 signal Data_cpt : integer;
59 59 signal MAX : integer;
60 signal pong_reg : std_logic;
60 61
62 type etat is (idle0,idle1,pong0,pong1);
63 signal ect : etat;
61 64
62 65 begin
63 66
64 67 process (clkm,rstn)
65 68 begin
66 69 if(rstn='0')then
70 ect <= idle0;
67 71 Valid <= '0';
72 pong_reg <= '0';
73 header_val <= '0';
74 header(5 downto 0) <= (others => '0');
68 75 Write_reg <= '0';
69 76 Data_cpt <= 0;
70 MAX <= 0;
77 MAX <= 128;
71 78
72 79
73 80 elsif(clkm' event and clkm='1')then
74 81 Write_reg <= Matrix_Write;
82 pong_reg <= pong;
75 83
76 84 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 85 MAX <= 128;
@@ -79,33 +87,102 begin
79 87 MAX <= 256;
80 88 end if;
81 89
90 -- if(Write_reg = '0' and Matrix_Write = '1')then
91 -- if(Data_cpt = MAX)then
92 -- Data_cpt <= 0;
93 -- Valid <= '1';
94 -- header_val <= '1';
95 -- else
96 -- Data_cpt <= Data_cpt + 1;
97 -- Valid <= '0';
98 -- end if;
99 -- end if;
100
82 101 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
102 Data_cpt <= Data_cpt + 1;
103 Valid <= '0';
104 elsif(Data_cpt = MAX)then
84 105 Data_cpt <= 0;
85 106 Valid <= '1';
86 107 header_val <= '1';
87 108 else
88 Data_cpt <= Data_cpt + 1;
89 109 Valid <= '0';
90 110 end if;
91 end if;
92 111
112 -- if(header_ack = '1')then
113 -- header_val <= '0';
114 -- end if;
115
116 -- if(emptyIN = "10")then
117 -- ping <= '0';
118 -- elsif(emptyIN = "01")then
119 -- ping <= '1';
120 -- else
121 -- ping <= ping;
122 -- end if;
123
124
125 case ect is
126
127 when idle0 =>
93 128 if(header_ack = '1')then
94 129 header_val <= '0';
130 --if(pong = '1')then
131 ect <= pong0;
132 --elsif(pong = '0')then
133 --ect <= pong1;
134 --end if;
135 end if;
136
137 when pong0 =>
138 header(1 downto 0) <= Matrix_Type;
139 header(5 downto 2) <= Matrix_Param;
140 if(emptyIN(0) = '1')then
141 ect <= idle1;
95 142 end if;
96 143
144 when idle1 =>
145 if(header_ack = '1')then
146 header_val <= '0';
147 ect <= pong1;
148 end if;
149
150 when pong1 =>
151 header(1 downto 0) <= Matrix_Type;
152 header(5 downto 2) <= Matrix_Param;
153 if(emptyIN(1) = '1')then
154 ect <= idle0;
155 end if;
156
157 end case;
97 158 end if;
98 159 end process;
99 160
100 161 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101 162
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
163 --header(1 downto 0) <= Matrix_Type;
164 --header(5 downto 2) <= Matrix_Param;
104 165 header(31 downto 6) <= (others => '0');
105 166
106 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
107 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
167 with ect select
168 dataOUT <= dataIN(Data_sz-1 downto 0) when pong0,
169 dataIN(Data_sz-1 downto 0) when idle0,
170 dataIN((2*Data_sz)-1 downto Data_sz) when pong1,
171 dataIN((2*Data_sz)-1 downto Data_sz) when idle1,
172 (others => '0') when others;
108 173
109 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
174 with ect select
175 emptyOUT <= emptyIN(0) when pong0,
176 emptyIN(0) when idle0,
177 emptyIN(1) when pong1,
178 emptyIN(1) when idle1,
179 '1' when others;
180
181 with ect select
182 RenOUT <= '1' & RenIN when pong0,
183 '1' & RenIN when idle0,
184 RenIN & '1' when pong1,
185 RenIN & '1' when idle1,
186 "11" when others;
110 187
111 188 end architecture;
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@@ -103,6 +103,7 ARCHITECTURE Behavioral OF lpp_dma_ip IS
103 103 -----------------------------------------------------------------------------
104 104 -----------------------------------------------------------------------------
105 105 TYPE state_DMAWriteBurst IS (IDLE,
106 CHECK_COMPONENT_TYPE,
106 107 TRASH_FIFO,
107 108 WAIT_HEADER_ACK,
108 109 SEND_DATA,
@@ -182,8 +183,7 BEGIN
182 183 END PROCESS debug_info;
183 184
184 185
185 matrix_type <= header(1 DOWNTO 0);
186 component_type <= header(5 DOWNTO 2);
186
187 187
188 188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
@@ -191,8 +191,8 BEGIN
191 191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 192 '0';
193 193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
195 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
196 196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 197 '0';
198 198
@@ -208,6 +208,8 BEGIN
208 208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 209 BEGIN -- PROCESS DMAWriteBurst_p
210 210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 matrix_type <= (others => '0');
212 component_type <= (others => '0');
211 213 state <= IDLE;
212 214 header_ack <= '0';
213 215 ready_matrix_f0_0 <= '0';
@@ -216,7 +218,7 BEGIN
216 218 ready_matrix_f2 <= '0';
217 219 error_anticipating_empty_fifo <= '0';
218 220 error_bad_component_error <= '0';
219 component_type_pre <= "1110";
221 component_type_pre <= "0000";
220 222 fifo_ren_trash <= '1';
221 223 component_send <= '0';
222 224 address <= (OTHERS => '0');
@@ -227,6 +229,9 BEGIN
227 229
228 230 CASE state IS
229 231 WHEN IDLE =>
232 matrix_type <= header(1 DOWNTO 0);
233 --component_type <= header(5 DOWNTO 2);
234
230 235 ready_matrix_f0_0 <= '0';
231 236 ready_matrix_f0_1 <= '0';
232 237 ready_matrix_f1 <= '0';
@@ -234,9 +239,14 BEGIN
234 239 error_bad_component_error <= '0';
235 240 header_select <= '1';
236 241 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
242 matrix_type <= header(1 DOWNTO 0);
243 component_type <= header(5 DOWNTO 2);
244 component_type_pre <= component_type;
245 state <= CHECK_COMPONENT_TYPE;
246 END IF;
247
248 WHEN CHECK_COMPONENT_TYPE =>
237 249 IF header_check_ok = '1' THEN
238 header_data <= header;
239 component_type_pre <= header(5 DOWNTO 2);
240 250 header_ack <= '1';
241 251 --
242 252 header_send <= '1';
@@ -248,13 +258,14 BEGIN
248 258 state <= WAIT_HEADER_ACK;
249 259 ELSE
250 260 error_bad_component_error <= '1';
251 component_type_pre <= "1110";
261 component_type_pre <= "0000";
252 262 header_ack <= '1';
253 263 state <= TRASH_FIFO;
254 264 END IF;
255 END IF;
265
256 266
257 267 WHEN TRASH_FIFO =>
268 header_ack <= '0';
258 269 error_bad_component_error <= '0';
259 270 error_anticipating_empty_fifo <= '0';
260 271 IF fifo_empty = '1' THEN
@@ -265,6 +276,7 BEGIN
265 276 END IF;
266 277
267 278 WHEN WAIT_HEADER_ACK =>
279 header_ack <= '0';
268 280 header_send <= '0';
269 281 IF header_send_ko = '1' THEN
270 282 state <= TRASH_FIFO;
@@ -279,7 +291,7 BEGIN
279 291 WHEN SEND_DATA =>
280 292 IF fifo_empty = '1' THEN
281 293 state <= IDLE;
282 IF component_type = "1110" THEN
294 IF component_type = "1110" THEN --"1110" -- JC
283 295 CASE matrix_type IS
284 296 WHEN "00" => ready_matrix_f0_0 <= '1';
285 297 WHEN "01" => ready_matrix_f0_1 <= '1';
@@ -287,6 +299,7 BEGIN
287 299 WHEN "11" => ready_matrix_f2 <= '1';
288 300 WHEN OTHERS => NULL;
289 301 END CASE;
302
290 303 END IF;
291 304 ELSE
292 305 component_send <= '1';
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@@ -33,7 +33,7 library lpp;
33 33 use lpp.lpp_amba.all;
34 34 use lpp.apb_devices_list.all;
35 35 use lpp.lpp_memory.all;
36
36 use lpp.iir_filter.all;
37 37
38 38 entity APB_FIFO is
39 39 generic (
@@ -47,6 +47,7 generic (
47 47 Data_sz : integer := 16;
48 48 Addr_sz : integer := 9;
49 49 Enable_ReUse : std_logic := '0';
50 Mem_use : integer := use_RAM;
50 51 R : integer := 1;
51 52 W : integer := 1
52 53 );
@@ -175,7 +176,7 Full <= sFull;
175 176
176 177 fifos: for i in 0 to FifoCnt-1 generate
177 178 FIFO0 : lpp_fifo
178 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
179 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
179 180 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
180 181 end generate;
181 182
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@@ -24,12 +24,14 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library lpp;
26 26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 28 library techmap;
28 29 use techmap.gencomp.all;
29 30
30 31 entity lppFIFOxN is
31 32 generic(
32 33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
33 35 Data_sz : integer range 1 to 32 := 8;
34 36 Addr_sz : integer range 1 to 32 := 8;
35 37 FifoCnt : integer := 1;
@@ -56,7 +58,7 begin
56 58
57 59 fifos: for i in 0 to FifoCnt-1 generate
58 60 FIFO0 : lpp_fifo
59 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
60 62 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
61 63 end generate;
62 64
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@@ -31,6 +31,7 use techmap.gencomp.all;
31 31 entity lpp_fifo is
32 32 generic(
33 33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
34 35 Enable_ReUse : std_logic := '0';
35 36 DataSz : integer range 1 to 32 := 8;
36 37 abits : integer range 2 to 12 := 8
@@ -75,12 +76,17 begin
75 76 -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
76 77 -- A l'inverse de RAM_CEL !!!
77 78 --==================================================================================
79 memRAM : IF Mem_use = use_RAM GENERATE
78 80 SRAM : syncram_2p
79 81 generic map(tech,abits,DataSz)
80 82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
83 END GENERATE;
81 84 --==================================================================================
82 --RAM0: entity work.RAM_CEL
83 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
85 memCEL : IF Mem_use = use_CEL GENERATE
86 CRAM : RAM_CEL
87 generic map(DataSz,abits)
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
89 END GENERATE;
84 90 --==================================================================================
85 91
86 92 --=============================
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@@ -26,6 +26,7 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
29 30 library gaisler;
30 31 use gaisler.misc.all;
31 32 use gaisler.memctrl.all;
@@ -48,6 +49,7 generic (
48 49 Data_sz : integer := 16;
49 50 Addr_sz : integer := 9;
50 51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
51 53 R : integer := 1;
52 54 W : integer := 1
53 55 );
@@ -74,6 +76,7 end component;
74 76 component lpp_fifo is
75 77 generic(
76 78 tech : integer := 0;
79 Mem_use : integer := use_RAM;
77 80 Enable_ReUse : std_logic := '0';
78 81 DataSz : integer range 1 to 32 := 8;
79 82 abits : integer range 2 to 12 := 8
@@ -98,6 +101,7 end component;
98 101 component lppFIFOxN is
99 102 generic(
100 103 tech : integer := 0;
104 Mem_use : integer := use_RAM;
101 105 Data_sz : integer range 1 to 32 := 8;
102 106 Addr_sz : integer range 1 to 32 := 8;
103 107 FifoCnt : integer := 1;
@@ -117,35 +121,17 port(
117 121 );
118 122 end component;
119 123
120 component lppFIFOx5 is
124 component FillFifo is
121 125 generic(
122 tech : integer := 0;
123 126 Data_sz : integer range 1 to 32 := 16;
124 Addr_sz : integer range 2 to 12 := 8;
125 Enable_ReUse : std_logic := '0'
127 Fifo_cnt : integer range 1 to 8 := 5
126 128 );
127 129 port(
128 rst : in std_logic;
129 wclk : in std_logic;
130 rclk : in std_logic;
131 ReUse : in std_logic_vector(4 downto 0);
132 wen : in std_logic_vector(4 downto 0);
133 ren : in std_logic_vector(4 downto 0);
134 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
135 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
136 full : out std_logic_vector(4 downto 0);
137 empty : out std_logic_vector(4 downto 0)
138 );
139 end component;
140
141 component Bridge is
142 port(
143 130 clk : in std_logic;
144 131 raz : in std_logic;
145 EmptyUp : in std_logic;
146 FullDwn : in std_logic;
147 WriteDwn : out std_logic;
148 ReadUp : out std_logic
132 write : out std_logic_vector(Fifo_cnt-1 downto 0);
133 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
134 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
149 135 );
150 136 end component;
151 137
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@@ -11,7 +11,8 USE techmap.gencomp.ALL;
11 11
12 12 ENTITY lpp_top_acq IS
13 13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0;
15 Mem_use : integer := use_RAM
15 16 );
16 17 PORT (
17 18 -- ADS7886
@@ -143,7 +144,7 BEGIN
143 144 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 145 GENERIC MAP (
145 146 tech => 0,
146 Mem_use => use_CEL, -- use_RAM
147 Mem_use => Mem_use,
147 148 Sample_SZ => 18,
148 149 Coef_SZ => Coef_SZ,
149 150 Coef_Nb => 25, -- TODO
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@@ -16,7 +16,8 PACKAGE lpp_top_lfr_pkg IS
16 16
17 17 COMPONENT lpp_top_acq
18 18 GENERIC(
19 tech : INTEGER := 0
19 tech : INTEGER := 0;
20 Mem_use : integer := use_RAM
20 21 );
21 22 PORT (
22 23 -- ADS7886
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