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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe PELLION | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | ||
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23 | LIBRARY IEEE; | |
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24 | USE IEEE.numeric_std.ALL; | |
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25 | USE IEEE.std_logic_1164.ALL; | |
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26 | ||
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27 | LIBRARY techmap; | |
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28 | USE techmap.gencomp.ALL; | |
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29 | ||
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30 | LIBRARY lpp; | |
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31 | USE lpp.iir_filter.ALL; | |
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32 | USE lpp.general_purpose.ALL; | |
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33 | ||
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34 | ENTITY IIR_CEL_CTRLR_v3 IS | |
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35 | GENERIC ( | |
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36 | tech : INTEGER := 0; | |
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37 | Mem_use : INTEGER := use_RAM; | |
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38 | Sample_SZ : INTEGER := 18; | |
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39 | Coef_SZ : INTEGER := 9; | |
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40 | Coef_Nb : INTEGER := 25; | |
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41 | Coef_sel_SZ : INTEGER := 5; | |
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42 | Cels_count : INTEGER := 5; | |
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43 | ChanelsCount : INTEGER := 8); | |
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44 | PORT ( | |
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45 | rstn : IN STD_LOGIC; | |
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46 | clk : IN STD_LOGIC; | |
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47 | ||
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48 | virg_pos : IN INTEGER; | |
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49 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
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50 | ||
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51 | sample_in1_val : IN STD_LOGIC; | |
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52 | sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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53 | sample_in2_val : IN STD_LOGIC; | |
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54 | sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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55 | ||
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56 | sample_out1_val : OUT STD_LOGIC; | |
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57 | sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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58 | sample_out2_val : OUT STD_LOGIC; | |
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59 | sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |
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60 | END IIR_CEL_CTRLR_v3; | |
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61 | ||
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62 | ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS | |
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63 | ||
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64 | COMPONENT RAM_CTRLR_v2 | |
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65 | GENERIC ( | |
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66 | tech : INTEGER; | |
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67 | Input_SZ_1 : INTEGER; | |
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68 | Mem_use : INTEGER); | |
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69 | PORT ( | |
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70 | rstn : IN STD_LOGIC; | |
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71 | clk : IN STD_LOGIC; | |
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72 | ram_write : IN STD_LOGIC; | |
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73 | ram_read : IN STD_LOGIC; | |
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74 | raddr_rst : IN STD_LOGIC; | |
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75 | raddr_add1 : IN STD_LOGIC; | |
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76 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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77 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
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78 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); | |
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79 | END COMPONENT; | |
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80 | ||
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81 | COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW | |
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82 | GENERIC ( | |
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83 | Sample_SZ : INTEGER; | |
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84 | Coef_SZ : INTEGER; | |
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85 | Coef_Nb : INTEGER; | |
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86 | Coef_sel_SZ : INTEGER); | |
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87 | PORT ( | |
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88 | rstn : IN STD_LOGIC; | |
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89 | clk : IN STD_LOGIC; | |
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90 | virg_pos : IN INTEGER; | |
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91 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
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92 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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93 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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94 | ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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95 | ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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96 | alu_sel_input : IN STD_LOGIC; | |
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97 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
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98 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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99 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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100 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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101 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); | |
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102 | END COMPONENT; | |
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103 | ||
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104 | COMPONENT IIR_CEL_CTRLR_v2_CONTROL | |
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105 | GENERIC ( | |
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106 | Coef_sel_SZ : INTEGER; | |
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107 | Cels_count : INTEGER; | |
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108 | ChanelsCount : INTEGER); | |
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109 | PORT ( | |
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110 | rstn : IN STD_LOGIC; | |
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111 | clk : IN STD_LOGIC; | |
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112 | sample_in_val : IN STD_LOGIC; | |
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113 | sample_in_rot : OUT STD_LOGIC; | |
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114 | sample_out_val : OUT STD_LOGIC; | |
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115 | sample_out_rot : OUT STD_LOGIC; | |
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116 | in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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117 | ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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118 | ram_write : OUT STD_LOGIC; | |
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119 | ram_read : OUT STD_LOGIC; | |
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120 | raddr_rst : OUT STD_LOGIC; | |
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121 | raddr_add1 : OUT STD_LOGIC; | |
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122 | waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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123 | alu_sel_input : OUT STD_LOGIC; | |
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124 | alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
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125 | alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); | |
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126 | END COMPONENT; | |
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127 | ||
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128 | SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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129 | SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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130 | SIGNAL ram_write : STD_LOGIC; | |
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131 | SIGNAL ram_read : STD_LOGIC; | |
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132 | SIGNAL raddr_rst : STD_LOGIC; | |
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133 | SIGNAL raddr_add1 : STD_LOGIC; | |
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134 | SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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135 | SIGNAL alu_sel_input : STD_LOGIC; | |
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136 | SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
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137 | SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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138 | ||
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139 | SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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140 | SIGNAL sample_in_rotate : STD_LOGIC; | |
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141 | SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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142 | SIGNAL sample_out_val_s : STD_LOGIC; | |
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143 | SIGNAL sample_out_val_s2 : STD_LOGIC; | |
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144 | SIGNAL sample_out_rot_s : STD_LOGIC; | |
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145 | SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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146 | ||
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147 | SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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148 | ||
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149 | SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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150 | SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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151 | -- | |
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152 | SIGNAL sample_in_val : STD_LOGIC; | |
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153 | SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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154 | SIGNAL sample_out_val : STD_LOGIC; | |
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155 | SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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156 | ||
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157 | ----------------------------------------------------------------------------- | |
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158 | -- | |
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159 | ----------------------------------------------------------------------------- | |
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160 | SIGNAL CHANNEL_SEL : STD_LOGIC; | |
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161 | ||
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162 | SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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163 | SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
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164 | ||
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165 | SIGNAL ram_write_1 : STD_LOGIC; | |
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166 | SIGNAL ram_read_1 : STD_LOGIC; | |
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167 | SIGNAL raddr_rst_1 : STD_LOGIC; | |
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168 | SIGNAL raddr_add1_1 : STD_LOGIC; | |
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169 | SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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170 | ||
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171 | SIGNAL ram_write_2 : STD_LOGIC; | |
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172 | SIGNAL ram_read_2 : STD_LOGIC; | |
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173 | SIGNAL raddr_rst_2 : STD_LOGIC; | |
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174 | SIGNAL raddr_add1_2 : STD_LOGIC; | |
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175 | SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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176 | ----------------------------------------------------------------------------- | |
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177 | SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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178 | SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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179 | SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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180 | ----------------------------------------------------------------------------- | |
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181 | TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE); | |
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182 | SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION; | |
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183 | ||
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184 | SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
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185 | ||
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186 | BEGIN | |
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187 | ||
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188 | ----------------------------------------------------------------------------- | |
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189 | channel_val(0) <= sample_in1_val; | |
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190 | channel_val(1) <= sample_in2_val; | |
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191 | all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE | |
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192 | PROCESS (clk, rstn) | |
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193 | BEGIN -- PROCESS | |
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194 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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195 | channel_ready(I) <= '0'; | |
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196 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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197 | IF channel_val(I) = '1' THEN | |
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198 | channel_ready(I) <= '1'; | |
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199 | ELSIF channel_done(I) = '1' THEN | |
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200 | channel_ready(I) <= '0'; | |
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201 | END IF; | |
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202 | END IF; | |
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203 | END PROCESS; | |
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204 | END GENERATE all_channel_input_valid; | |
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205 | ----------------------------------------------------------------------------- | |
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206 | all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE | |
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207 | all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE | |
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208 | sample_out_zero(I,J) <= '0'; | |
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209 | END GENERATE all_bit; | |
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210 | END GENERATE all_channel_sample_out; | |
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211 | ||
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212 | PROCESS (clk, rstn) | |
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213 | BEGIN -- PROCESS | |
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214 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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215 | state_channel_selection <= IDLE; | |
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216 | CHANNEL_SEL <= '0'; | |
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217 | sample_in_val <= '0'; | |
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218 | sample_out1_val <= '0'; | |
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219 | sample_out2_val <= '0'; | |
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220 | sample_out1 <= sample_out_zero; | |
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221 | sample_out2 <= sample_out_zero; | |
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222 | channel_done <= "00"; | |
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223 | ||
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224 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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225 | CASE state_channel_selection IS | |
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226 | WHEN IDLE => | |
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227 | CHANNEL_SEL <= '0'; | |
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228 | sample_in_val <= '0'; | |
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229 | sample_out1_val <= '0'; | |
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230 | sample_out2_val <= '0'; | |
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231 | channel_done <= "00"; | |
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232 | IF channel_ready(0) = '1' THEN | |
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233 | state_channel_selection <= ONGOING_1; | |
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234 | CHANNEL_SEL <= '0'; | |
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235 | sample_in_val <= '1'; | |
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236 | ELSIF channel_ready(1) = '1' THEN | |
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237 | state_channel_selection <= ONGOING_2; | |
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238 | CHANNEL_SEL <= '1'; | |
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239 | sample_in_val <= '1'; | |
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240 | END IF; | |
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241 | WHEN ONGOING_1 => | |
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242 | sample_in_val <= '0'; | |
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243 | IF sample_out_val = '1' THEN | |
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244 | state_channel_selection <= WAIT_STATE; | |
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245 | sample_out1 <= sample_out; | |
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246 | sample_out1_val <= '1'; | |
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247 | channel_done(0) <= '1'; | |
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248 | END IF; | |
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249 | WHEN ONGOING_2 => | |
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250 | sample_in_val <= '0'; | |
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251 | IF sample_out_val = '1' THEN | |
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252 | state_channel_selection <= WAIT_STATE; | |
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253 | sample_out2 <= sample_out; | |
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254 | sample_out2_val <= '1'; | |
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255 | channel_done(1) <= '1'; | |
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256 | END IF; | |
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257 | WHEN WAIT_STATE => | |
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258 | state_channel_selection <= IDLE; | |
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259 | CHANNEL_SEL <= '0'; | |
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260 | sample_in_val <= '0'; | |
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261 | sample_out1_val <= '0'; | |
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262 | sample_out2_val <= '0'; | |
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263 | channel_done <= "00"; | |
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264 | ||
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265 | WHEN OTHERS => NULL; | |
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266 | END CASE; | |
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267 | ||
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268 | END IF; | |
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269 | END PROCESS; | |
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270 | ||
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271 | sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2; | |
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272 | ----------------------------------------------------------------------------- | |
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273 | ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE | |
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274 | ram_output_2; | |
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275 | ||
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276 | ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0'; | |
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277 | ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0'; | |
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278 | raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1'; | |
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279 | raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0'; | |
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280 | waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00"; | |
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281 | ||
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282 | ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0'; | |
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283 | ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0'; | |
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284 | raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1'; | |
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285 | raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0'; | |
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286 | waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00"; | |
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287 | ||
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288 | RAM_CTRLR_v2_1: RAM_CTRLR_v2 | |
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289 | GENERIC MAP ( | |
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290 | tech => tech, | |
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291 | Input_SZ_1 => Sample_SZ, | |
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292 | Mem_use => Mem_use) | |
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293 | PORT MAP ( | |
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294 | clk => clk, | |
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295 | rstn => rstn, | |
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296 | ram_write => ram_write_1, | |
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297 | ram_read => ram_read_1, | |
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298 | raddr_rst => raddr_rst_1, | |
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299 | raddr_add1 => raddr_add1_1, | |
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300 | waddr_previous => waddr_previous_1, | |
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301 | sample_in => ram_input, | |
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302 | sample_out => ram_output_1); | |
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303 | ||
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304 | RAM_CTRLR_v2_2: RAM_CTRLR_v2 | |
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305 | GENERIC MAP ( | |
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306 | tech => tech, | |
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307 | Input_SZ_1 => Sample_SZ, | |
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308 | Mem_use => Mem_use) | |
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309 | PORT MAP ( | |
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310 | clk => clk, | |
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311 | rstn => rstn, | |
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312 | ram_write => ram_write_2, | |
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313 | ram_read => ram_read_2, | |
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314 | raddr_rst => raddr_rst_2, | |
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315 | raddr_add1 => raddr_add1_2, | |
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316 | waddr_previous => waddr_previous_2, | |
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317 | sample_in => ram_input, | |
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318 | sample_out => ram_output_2); | |
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319 | ----------------------------------------------------------------------------- | |
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320 | ||
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321 | IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW | |
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322 | GENERIC MAP ( | |
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323 | Sample_SZ => Sample_SZ, | |
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324 | Coef_SZ => Coef_SZ, | |
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325 | Coef_Nb => Coef_Nb, | |
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326 | Coef_sel_SZ => Coef_sel_SZ) | |
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327 | PORT MAP ( | |
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328 | rstn => rstn, | |
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329 | clk => clk, | |
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330 | virg_pos => virg_pos, | |
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331 | coefs => coefs, | |
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332 | --CTRL | |
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333 | in_sel_src => in_sel_src, | |
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334 | ram_sel_Wdata => ram_sel_Wdata, | |
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335 | -- | |
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336 | ram_input => ram_input, | |
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337 | ram_output => ram_output, | |
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338 | -- | |
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339 | alu_sel_input => alu_sel_input, | |
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340 | alu_sel_coeff => alu_sel_coeff, | |
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341 | alu_ctrl => alu_ctrl, | |
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342 | alu_comp => "00", | |
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343 | --DATA | |
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344 | sample_in => sample_in_s, | |
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345 | sample_out => sample_out_s); | |
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346 | ----------------------------------------------------------------------------- | |
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347 | ||
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348 | ||
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349 | IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL | |
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350 | GENERIC MAP ( | |
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351 | Coef_sel_SZ => Coef_sel_SZ, | |
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352 | Cels_count => Cels_count, | |
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353 | ChanelsCount => ChanelsCount) | |
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354 | PORT MAP ( | |
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355 | rstn => rstn, | |
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356 | clk => clk, | |
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357 | sample_in_val => sample_in_val, | |
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358 | sample_in_rot => sample_in_rotate, | |
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359 | sample_out_val => sample_out_val_s, | |
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360 | sample_out_rot => sample_out_rot_s, | |
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361 | ||
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362 | in_sel_src => in_sel_src, | |
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363 | ram_sel_Wdata => ram_sel_Wdata, | |
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364 | ram_write => ram_write, | |
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365 | ram_read => ram_read, | |
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366 | raddr_rst => raddr_rst, | |
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367 | raddr_add1 => raddr_add1, | |
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368 | waddr_previous => waddr_previous, | |
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369 | alu_sel_input => alu_sel_input, | |
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370 | alu_sel_coeff => alu_sel_coeff, | |
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371 | alu_ctrl => alu_ctrl); | |
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372 | ||
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373 | ----------------------------------------------------------------------------- | |
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374 | -- SAMPLE IN | |
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375 | ----------------------------------------------------------------------------- | |
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376 | loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE | |
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377 | ||
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378 | loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE | |
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379 | PROCESS (clk, rstn) | |
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380 | BEGIN -- PROCESS | |
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381 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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382 | sample_in_buf(I, J) <= '0'; | |
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383 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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384 | IF sample_in_val = '1' THEN | |
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385 | sample_in_buf(I, J) <= sample_in(I, J); | |
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386 | ELSIF sample_in_rotate = '1' THEN | |
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387 | sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); | |
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388 | END IF; | |
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389 | END IF; | |
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390 | END PROCESS; | |
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391 | END GENERATE loop_all_chanel; | |
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392 | ||
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393 | sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); | |
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394 | ||
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395 | END GENERATE loop_all_sample; | |
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396 | ||
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397 | ----------------------------------------------------------------------------- | |
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398 | -- SAMPLE OUT | |
|
399 | ----------------------------------------------------------------------------- | |
|
400 | PROCESS (clk, rstn) | |
|
401 | BEGIN -- PROCESS | |
|
402 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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403 | sample_out_val <= '0'; | |
|
404 | sample_out_val_s2 <= '0'; | |
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405 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
406 | sample_out_val <= sample_out_val_s2; | |
|
407 | sample_out_val_s2 <= sample_out_val_s; | |
|
408 | END IF; | |
|
409 | END PROCESS; | |
|
410 | ||
|
411 | chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE | |
|
412 | PROCESS (clk, rstn) | |
|
413 | BEGIN -- PROCESS | |
|
414 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
415 | sample_out_s2(ChanelsCount-1, I) <= '0'; | |
|
416 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
417 | IF sample_out_rot_s = '1' THEN | |
|
418 | sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); | |
|
419 | END IF; | |
|
420 | END IF; | |
|
421 | END PROCESS; | |
|
422 | END GENERATE chanel_HIGH; | |
|
423 | ||
|
424 | chanel_more : IF ChanelsCount > 1 GENERATE | |
|
425 | all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE | |
|
426 | all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE | |
|
427 | PROCESS (clk, rstn) | |
|
428 | BEGIN -- PROCESS | |
|
429 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
430 | sample_out_s2(J-1, I) <= '0'; | |
|
431 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
432 | IF sample_out_rot_s = '1' THEN | |
|
433 | sample_out_s2(J-1, I) <= sample_out_s2(J, I); | |
|
434 | END IF; | |
|
435 | END IF; | |
|
436 | END PROCESS; | |
|
437 | END GENERATE all_bit; | |
|
438 | END GENERATE all_chanel; | |
|
439 | END GENERATE chanel_more; | |
|
440 | ||
|
441 | sample_out <= sample_out_s2; | |
|
442 | END ar_IIR_CEL_CTRLR_v3; |
@@ -0,0 +1,213 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe PELLION | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY lpp; | |
|
26 | USE lpp.iir_filter.ALL; | |
|
27 | USE lpp.general_purpose.ALL; | |
|
28 | ||
|
29 | ||
|
30 | ||
|
31 | ENTITY IIR_CEL_CTRLR_v3_DATAFLOW IS | |
|
32 | GENERIC( | |
|
33 | Sample_SZ : INTEGER := 16; | |
|
34 | Coef_SZ : INTEGER := 9; | |
|
35 | Coef_Nb : INTEGER := 30; | |
|
36 | Coef_sel_SZ : INTEGER := 5 | |
|
37 | ); | |
|
38 | PORT( | |
|
39 | rstn : IN STD_LOGIC; | |
|
40 | clk : IN STD_LOGIC; | |
|
41 | -- PARAMETER | |
|
42 | virg_pos : IN INTEGER; | |
|
43 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
|
44 | -- CONTROL | |
|
45 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
46 | -- | |
|
47 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
48 | -- | |
|
49 | ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
50 | ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
51 | ||
|
52 | -- | |
|
53 | alu_sel_input : IN STD_LOGIC; | |
|
54 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
|
55 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) | |
|
56 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
57 | -- DATA | |
|
58 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
59 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) | |
|
60 | ); | |
|
61 | END IIR_CEL_CTRLR_v3_DATAFLOW; | |
|
62 | ||
|
63 | ARCHITECTURE ar_IIR_CEL_CTRLR_v3_DATAFLOW OF IIR_CEL_CTRLR_v3_DATAFLOW IS | |
|
64 | ||
|
65 | SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
66 | SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
67 | SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
68 | SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); | |
|
69 | ||
|
70 | SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); | |
|
71 | SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); | |
|
72 | ||
|
73 | SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); | |
|
74 | ||
|
75 | BEGIN | |
|
76 | ||
|
77 | ----------------------------------------------------------------------------- | |
|
78 | -- INPUT | |
|
79 | ----------------------------------------------------------------------------- | |
|
80 | PROCESS (clk, rstn) | |
|
81 | BEGIN -- PROCESS | |
|
82 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
83 | reg_sample_in <= (OTHERS => '0'); | |
|
84 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
85 | CASE in_sel_src IS | |
|
86 | WHEN "00" => reg_sample_in <= reg_sample_in; | |
|
87 | WHEN "01" => reg_sample_in <= sample_in; | |
|
88 | WHEN "10" => reg_sample_in <= ram_output; | |
|
89 | WHEN "11" => reg_sample_in <= alu_output; | |
|
90 | WHEN OTHERS => NULL; | |
|
91 | END CASE; | |
|
92 | END IF; | |
|
93 | END PROCESS; | |
|
94 | ||
|
95 | ||
|
96 | ----------------------------------------------------------------------------- | |
|
97 | -- RAM + CTRL | |
|
98 | ----------------------------------------------------------------------------- | |
|
99 | ||
|
100 | ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE | |
|
101 | alu_output WHEN ram_sel_Wdata = "01" ELSE | |
|
102 | ram_output; | |
|
103 | ||
|
104 | ----------------------------------------------------------------------------- | |
|
105 | -- MAC_ACC | |
|
106 | ----------------------------------------------------------------------------- | |
|
107 | -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) | |
|
108 | -- Data In : mac_sample, mac_coef | |
|
109 | -- Data Out: mac_output | |
|
110 | ||
|
111 | alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; | |
|
112 | ||
|
113 | coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE | |
|
114 | coeff_in: IF I < Coef_Nb GENERATE | |
|
115 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
|
116 | arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); | |
|
117 | END GENERATE all_bit; | |
|
118 | END GENERATE coeff_in; | |
|
119 | coeff_null: IF I > (Coef_Nb -1) GENERATE | |
|
120 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
|
121 | arrayCoeff(I,J) <= '0'; | |
|
122 | END GENERATE all_bit; | |
|
123 | END GENERATE coeff_null; | |
|
124 | END GENERATE coefftable; | |
|
125 | ||
|
126 | Coeff_Mux : MUXN | |
|
127 | GENERIC MAP ( | |
|
128 | Input_SZ => Coef_SZ, | |
|
129 | NbStage => Coef_sel_SZ) | |
|
130 | PORT MAP ( | |
|
131 | sel => alu_sel_coeff, | |
|
132 | INPUT => arrayCoeff, | |
|
133 | RES => alu_coef_s); | |
|
134 | ||
|
135 | ||
|
136 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
|
137 | alu_coef(J) <= alu_coef_s(J); | |
|
138 | END GENERATE all_bit; | |
|
139 | ||
|
140 | ----------------------------------------------------------------------------- | |
|
141 | -- TODO : just for Synthesis test | |
|
142 | ||
|
143 | --PROCESS (clk, rstn) | |
|
144 | --BEGIN | |
|
145 | -- IF rstn = '0' THEN | |
|
146 | -- alu_coef <= (OTHERS => '0'); | |
|
147 | -- ELSIF clk'event AND clk = '1' THEN | |
|
148 | -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP | |
|
149 | -- alu_coef(J) <= alu_coef_s(J); | |
|
150 | -- END LOOP all_bit; | |
|
151 | -- END IF; | |
|
152 | --END PROCESS; | |
|
153 | ||
|
154 | ----------------------------------------------------------------------------- | |
|
155 | ||
|
156 | ||
|
157 | ALU_1: ALU | |
|
158 | GENERIC MAP ( | |
|
159 | Arith_en => 1, | |
|
160 | Input_SZ_1 => Sample_SZ, | |
|
161 | Input_SZ_2 => Coef_SZ, | |
|
162 | COMP_EN => 1) | |
|
163 | PORT MAP ( | |
|
164 | clk => clk, | |
|
165 | reset => rstn, | |
|
166 | ctrl => alu_ctrl, | |
|
167 | comp => alu_comp, | |
|
168 | OP1 => alu_sample, | |
|
169 | OP2 => alu_coef, | |
|
170 | RES => alu_output_s); | |
|
171 | ||
|
172 | alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); | |
|
173 | ||
|
174 | sample_out <= alu_output; | |
|
175 | ||
|
176 | END ar_IIR_CEL_CTRLR_v3_DATAFLOW; | |
|
177 | ||
|
178 | ||
|
179 | ||
|
180 | ||
|
181 | ||
|
182 | ||
|
183 | ||
|
184 | ||
|
185 | ||
|
186 | ||
|
187 | ||
|
188 | ||
|
189 | ||
|
190 | ||
|
191 | ||
|
192 | ||
|
193 | ||
|
194 | ||
|
195 | ||
|
196 | ||
|
197 | ||
|
198 | ||
|
199 | ||
|
200 | ||
|
201 | ||
|
202 | ||
|
203 | ||
|
204 | ||
|
205 | ||
|
206 | ||
|
207 | ||
|
208 | ||
|
209 | ||
|
210 | ||
|
211 | ||
|
212 | ||
|
213 |
@@ -379,7 +379,7 BEGIN -- beh | |||
|
379 | 379 | pirq_ms => 6, |
|
380 | 380 | pirq_wfp => 14, |
|
381 | 381 | hindex => 2, |
|
382 |
top_lfr_version => X"01013 |
|
|
382 | top_lfr_version => X"010135") -- aa.bb.cc version | |
|
383 | 383 | -- AA : BOARD NUMBER |
|
384 | 384 | -- 0 => MINI_LFR |
|
385 | 385 | -- 1 => EM |
@@ -582,8 +582,8 BEGIN -- beh | |||
|
582 | 582 | ADC_SDO_sig <= ADC_SDO; |
|
583 | 583 | |
|
584 | 584 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE |
|
585 |
"0010001000100010" WHEN HK_SEL = " |
|
|
586 |
"0100010001000100" WHEN HK_SEL = "1 |
|
|
585 | "0010001000100010" WHEN HK_SEL = "01" ELSE | |
|
586 | "0100010001000100" WHEN HK_SEL = "10" ELSE | |
|
587 | 587 | (OTHERS => '0'); |
|
588 | 588 | |
|
589 | 589 |
@@ -140,6 +140,33 PACKAGE iir_filter IS | |||
|
140 | 140 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); |
|
141 | 141 | END COMPONENT; |
|
142 | 142 | |
|
143 | COMPONENT IIR_CEL_CTRLR_v3 | |
|
144 | GENERIC ( | |
|
145 | tech : INTEGER; | |
|
146 | Mem_use : INTEGER; | |
|
147 | Sample_SZ : INTEGER; | |
|
148 | Coef_SZ : INTEGER; | |
|
149 | Coef_Nb : INTEGER; | |
|
150 | Coef_sel_SZ : INTEGER; | |
|
151 | Cels_count : INTEGER; | |
|
152 | ChanelsCount : INTEGER); | |
|
153 | PORT ( | |
|
154 | rstn : IN STD_LOGIC; | |
|
155 | clk : IN STD_LOGIC; | |
|
156 | virg_pos : IN INTEGER; | |
|
157 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
|
158 | sample_in1_val : IN STD_LOGIC; | |
|
159 | sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
|
160 | sample_in2_val : IN STD_LOGIC; | |
|
161 | sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
|
162 | sample_out1_val : OUT STD_LOGIC; | |
|
163 | sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
|
164 | sample_out2_val : OUT STD_LOGIC; | |
|
165 | sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |
|
166 | END COMPONENT; | |
|
167 | ||
|
168 | ||
|
169 | ||
|
143 | 170 | |
|
144 | 171 | --component FilterCTRLR is |
|
145 | 172 | --port( |
@@ -6,3 +6,5 RAM_CTRLR_v2.vhd | |||
|
6 | 6 | IIR_CEL_CTRLR_v2_CONTROL.vhd |
|
7 | 7 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
|
8 | 8 | IIR_CEL_CTRLR_v2.vhd |
|
9 | IIR_CEL_CTRLR_v3_DATAFLOW.vhd | |
|
10 | IIR_CEL_CTRLR_v3.vhd |
@@ -348,7 +348,7 BEGIN -- beh | |||
|
348 | 348 | sample_f3_v_reg <= (OTHERS => '0'); |
|
349 | 349 | sample_f3_e1_reg <= (OTHERS => '0'); |
|
350 | 350 | sample_f3_e2_reg <= (OTHERS => '0'); |
|
351 |
ELSIF HCLK' |
|
|
351 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
352 | 352 | IF sample_f3_valid = '1' THEN |
|
353 | 353 | sample_f3_v_reg <= sample_f3_v; |
|
354 | 354 | sample_f3_e1_reg <= sample_f3_e1; |
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