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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

LFR-EQM 2.1.71
pellion -
r583:3d475eacd91a simu_with_Leon3
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@@ -422,7 +422,7 BEGIN
422 422 --Aeroflex memory generics:
423 423 mbpedac => BYPASS_EDAC_MEMCTRLR,
424 424 mprog => 1, -- program memory by default values after reset
425 mpsrate => 5, -- default scrub rate period
425 mpsrate => 15, -- default scrub rate period
426 426 mpb2s => 14, -- default busy to scrub delay
427 427 mpapb => 1, -- instantiate apb register
428 428 mchipcnt => 2,
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@@ -265,66 +265,20 BEGIN
265 265 data_shaping_R0 => data_shaping_R0,
266 266 data_shaping_R1 => data_shaping_R1,
267 267 data_shaping_R2 => data_shaping_R2,
268 sample_f0_val => sample_f_val(0),
269 sample_f1_val => sample_f_val(1),
270 sample_f2_val => sample_f_val(2),
271 sample_f3_val => sample_f_val(3),
272 sample_f0_wdata => OPEN,
273 sample_f1_wdata => OPEN,
274 sample_f2_wdata => OPEN,
275 sample_f3_wdata => OPEN,
268 sample_f0_val => sample_f0_val,
269 sample_f1_val => sample_f1_val,
270 sample_f2_val => sample_f2_val,
271 sample_f3_val => sample_f3_val,
272 sample_f0_wdata => sample_f0_data,
273 sample_f1_wdata => sample_f1_data,
274 sample_f2_wdata => sample_f2_data,
275 sample_f3_wdata => sample_f3_data,
276 276 sample_f0_time => sample_f0_time,
277 277 sample_f1_time => sample_f1_time,
278 278 sample_f2_time => sample_f2_time,
279 279 sample_f3_time => sample_f3_time
280 280 );
281 -----------------------------------------------------------------------------
282 ALL_lane: FOR J IN 0 TO 3 GENERATE
283 ALL_channel: FOR I IN 0 TO 5 GENERATE
284 sample_f_data(15 + I*16 + J*6*16 DOWNTO 14 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(J,2));
285 sample_f_data(13 + I*16 + J*6*16 DOWNTO 11 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(I,3));
286 281
287 PROCESS (clk, rstn)
288 BEGIN -- PROCESS
289 IF rstn = '0' THEN -- asynchronous reset (active low)
290 sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16 ) <= STD_LOGIC_VECTOR(to_unsigned(2**11/6*I,11));
291 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
292 IF sample_f_val(J) = '1' THEN
293 sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(
294 to_integer(UNSIGNED(sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16))) + 1,
295 11));
296 END IF;
297 END IF;
298 END PROCESS;
299
300 END GENERATE ALL_channel;
301 END GENERATE ALL_lane;
302
303 PROCESS (clk, rstn)
304 BEGIN -- PROCESS
305 IF rstn = '0' THEN -- asynchronous reset (active low)
306 sample_f0_val <= '0';
307 sample_f1_val <= '0';
308 sample_f2_val <= '0';
309 sample_f3_val <= '0';
310 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
311 sample_f0_val <= sample_f_val(0);
312 sample_f1_val <= sample_f_val(1);
313 sample_f2_val <= sample_f_val(2);
314 sample_f3_val <= sample_f_val(3);
315 END IF;
316 END PROCESS;
317
318
319 sample_f0_data <= sample_f_data(1*6*16-1 DOWNTO 0*6*16);
320 sample_f1_data <= sample_f_data(2*6*16-1 DOWNTO 1*6*16);
321 sample_f2_data <= sample_f_data(3*6*16-1 DOWNTO 2*6*16);
322 sample_f3_data <= sample_f_data(4*6*16-1 DOWNTO 3*6*16);
323
324 --sample_f0_data <= X"0020" & X"0010" & X"0008" & X"0004" & X"0002" & X"0001";
325 --sample_f1_data <= X"1020" & X"1010" & X"1008" & X"1004" & X"1002" & X"1001";
326 --sample_f2_data <= X"2020" & X"2010" & X"2008" & X"2004" & X"2002" & X"2001";
327 --sample_f3_data <= X"4020" & X"4010" & X"4008" & X"4004" & X"4002" & X"4001";
328 282 -----------------------------------------------------------------------------
329 283 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
330 284 GENERIC MAP (
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