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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

add cic_lfr (without the R2 param) subsystem into lpp_lfr_filter
pellion -
r493:3815063a3eb6 (MINI-LFR) WFP_MS-0-1-40 JC
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@@ -511,7 +511,7 BEGIN -- beh
511 511 pirq_ms => 6,
512 512 pirq_wfp => 14,
513 513 hindex => 2,
514 top_lfr_version => X"000127") -- aa.bb.cc version
514 top_lfr_version => X"000128") -- aa.bb.cc version
515 515 PORT MAP (
516 516 clk => clk_25,
517 517 rstn => LFR_rstn,
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@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1 23 LIBRARY ieee;
2 24 USE ieee.std_logic_1164.ALL;
3 25 USE ieee.numeric_std.ALL;
@@ -8,6 +30,8 USE lpp.iir_filter.ALL;
8 30 USE lpp.FILTERcfg.ALL;
9 31 USE lpp.lpp_memory.ALL;
10 32 USE lpp.lpp_waveform_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
34 USE data_type_pkg.ALL;
11 35
12 36 LIBRARY techmap;
13 37 USE techmap.gencomp.ALL;
@@ -95,17 +119,15 ARCHITECTURE tb OF lpp_lfr_filter IS
95 119 -----------------------------------------------------------------------------
96 120 -- SIGNAL sample_f0_val : STD_LOGIC;
97 121 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
98 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
122 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
99 123 --
100 124 -- SIGNAL sample_f1_val : STD_LOGIC;
101 125 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
102 126 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
103 127 --
104 128 -- SIGNAL sample_f2_val : STD_LOGIC;
105 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
106 --
107 -- SIGNAL sample_f3_val : STD_LOGIC;
108 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
129 SIGNAL sample_f2 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
130 SIGNAL sample_f3 : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
109 131
110 132 -----------------------------------------------------------------------------
111 133 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
@@ -295,6 +317,7 BEGIN
295 317
296 318 -----------------------------------------------------------------------------
297 319 -- F2 -- @256 Hz
320 -- F3 -- @16 Hz
298 321 -----------------------------------------------------------------------------
299 322 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
300 323 sample_f0_s(0, I) <= sample_f0(0, I); -- V
@@ -305,67 +328,34 BEGIN
305 328 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
306 329 END GENERATE all_bit_sample_f0_s;
307 330
308 Downsampling_f2 : Downsampling
331
332 cic_lfr_1: cic_lfr
309 333 GENERIC MAP (
310 ChanelCount => 6,
311 SampleSize => 16,
312 DivideParam => 96)
334 tech => 0,
335 use_RAM_nCEL => Mem_use)
313 336 PORT MAP (
314 337 clk => clk,
315 338 rstn => rstn,
316 sample_in_val => sample_f0_val_s ,
317 sample_in => sample_f0_s,
318 sample_out_val => sample_f2_val,
319 sample_out => sample_f2);
339 run => '1',
340
341 data_in => sample_f0_s,
342 data_in_valid => sample_f0_val_s,
320 343
321 --sample_f2_wen <= NOT(sample_f2_val) &
322 -- NOT(sample_f2_val) &
323 -- NOT(sample_f2_val) &
324 -- NOT(sample_f2_val) &
325 -- NOT(sample_f2_val) &
326 -- NOT(sample_f2_val);
344 data_out_16 => sample_f2,
345 data_out_16_valid => sample_f2_val,
346
347 data_out_256 => sample_f3,
348 data_out_256_valid => sample_f3_val);
327 349
328 350 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
329 351 sample_f2_wdata_s(I) <= sample_f2(0, I);
330 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(3, I);
331 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(4, I);
352 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
353 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
332 354 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
333 355 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
334 356 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
335 357 END GENERATE all_bit_sample_f2;
336 358
337 -----------------------------------------------------------------------------
338 -- F3 -- @16 Hz
339 -----------------------------------------------------------------------------
340 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
341 sample_f1_s(0, I) <= sample_f1(0, I); -- V
342 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
343 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
344 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
345 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
346 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
347 END GENERATE all_bit_sample_f1_s;
348
349 Downsampling_f3 : Downsampling
350 GENERIC MAP (
351 ChanelCount => 6,
352 SampleSize => 16,
353 DivideParam => 256)
354 PORT MAP (
355 clk => clk,
356 rstn => rstn,
357 sample_in_val => sample_f1_val_s ,
358 sample_in => sample_f1_s,
359 sample_out_val => sample_f3_val,
360 sample_out => sample_f3);
361
362 --sample_f3_wen <= (NOT sample_f3_val) &
363 -- (NOT sample_f3_val) &
364 -- (NOT sample_f3_val) &
365 -- (NOT sample_f3_val) &
366 -- (NOT sample_f3_val) &
367 -- (NOT sample_f3_val);
368
369 359 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
370 360 sample_f3_wdata_s(I) <= sample_f3(0, I);
371 361 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
@@ -383,4 +373,4 BEGIN
383 373 sample_f2_wdata <= sample_f2_wdata_s;
384 374 sample_f3_wdata <= sample_f3_wdata_s;
385 375
386 END tb; No newline at end of file
376 END tb;
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