@@ -380,7 +380,7 BEGIN -- beh | |||
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380 | 380 | pirq_ms => 6, |
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381 | 381 | pirq_wfp => 14, |
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382 | 382 | hindex => 2, |
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383 |
top_lfr_version => X"01013 |
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383 | top_lfr_version => X"01013A") -- aa.bb.cc version | |
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384 | 384 | -- AA : BOARD NUMBER |
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385 | 385 | -- 0 => MINI_LFR |
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386 | 386 | -- 1 => EM |
@@ -342,7 +342,7 BEGIN -- beh | |||
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342 | 342 | dbguart => 0, |
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343 | 343 | pclow => 2, |
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344 | 344 | clk_freq => 25000, |
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345 |
IS_RADHARD => |
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345 | IS_RADHARD => 0, | |
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346 | 346 | NB_CPU => 1, |
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347 | 347 | ENABLE_FPU => 1, |
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348 | 348 | FPU_NETLIST => 0, |
@@ -517,7 +517,7 BEGIN -- beh | |||
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517 | 517 | pirq_ms => 6, |
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518 | 518 | pirq_wfp => 14, |
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519 | 519 | hindex => 2, |
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520 |
top_lfr_version => X"00013 |
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520 | top_lfr_version => X"00013A") -- aa.bb.cc version | |
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521 | 521 | PORT MAP ( |
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522 | 522 | clk => clk_25, |
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523 | 523 | rstn => LFR_rstn, |
@@ -75,8 +75,6 ARCHITECTURE beh OF cic_lfr_r2 IS | |||
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75 | 75 | -- |
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76 | 76 | CONSTANT S_parameter : INTEGER := 3; |
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77 | 77 | SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0); |
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78 | SIGNAL CARRY_PUSH : STD_LOGIC; | |
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79 | SIGNAL CARRY_POP : STD_LOGIC; | |
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80 | 78 | -- |
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81 | 79 | |
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82 | 80 | SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0); |
@@ -397,4 +395,3 BEGIN | |||
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397 | 395 | END GENERATE all_channel_out_v; |
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398 | 396 | |
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399 | 397 | END beh; |
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400 |
@@ -115,9 +115,6 ARCHITECTURE Behavioral OF apb_lfr_manag | |||
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115 | 115 | SIGNAL soft_reset : STD_LOGIC; |
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116 | 116 | SIGNAL soft_reset_sync : STD_LOGIC; |
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117 | 117 | ----------------------------------------------------------------------------- |
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118 | SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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119 | SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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120 | SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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121 | 118 | SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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122 | 119 | |
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123 | 120 | SIGNAL previous_fine_time_bit : STD_LOGIC; |
@@ -360,9 +357,13 BEGIN | |||
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360 | 357 | ----------------------------------------------------------------------------- |
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361 | 358 | |
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362 | 359 | PROCESS (clk25MHz, resetn) |
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363 |
CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 1 |
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364 | -- for 11, the update frequency is 32Hz | |
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360 | CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT) | |
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365 | 361 | -- for each HK, the update frequency is freq/3 |
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362 | -- | |
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363 | -- for 14, the update frequency is | |
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364 | -- 4Hz and update for each | |
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365 | -- HK is 1.33Hz | |
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366 | ||
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366 | 367 | BEGIN -- PROCESS |
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367 | 368 | IF resetn = '0' THEN -- asynchronous reset (active low) |
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368 | 369 |
@@ -228,7 +228,12 ARCHITECTURE beh OF lpp_lfr IS | |||
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228 | 228 | |
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229 | 229 | SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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230 | 230 | ----------------------------------------------------------------------------- |
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231 | -- SIGNAL run_dma : STD_LOGIC; | |
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231 | SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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232 | SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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233 | SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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234 | SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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235 | SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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236 | ||
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232 | 237 | BEGIN |
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233 | 238 | |
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234 | 239 | debug_vector <= apb_reg_debug_vector; |
@@ -236,7 +241,8 BEGIN | |||
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236 | 241 | |
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237 | 242 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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238 | 243 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
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239 | ||
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244 | sample_time <= coarse_time & fine_time; | |
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245 | ||
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240 | 246 |
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241 | 247 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
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242 | 248 | --END GENERATE all_channel; |
@@ -248,6 +254,7 BEGIN | |||
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248 | 254 | PORT MAP ( |
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249 | 255 | sample => sample_s, |
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250 | 256 | sample_val => sample_val, |
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257 | sample_time => sample_time, | |
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251 | 258 | clk => clk, |
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252 | 259 | rstn => rstn, |
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253 | 260 | data_shaping_SP0 => data_shaping_SP0, |
@@ -262,7 +269,12 BEGIN | |||
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262 | 269 | sample_f0_wdata => sample_f0_data, |
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263 | 270 | sample_f1_wdata => sample_f1_data, |
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264 | 271 | sample_f2_wdata => sample_f2_data, |
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265 |
sample_f3_wdata => sample_f3_data |
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272 | sample_f3_wdata => sample_f3_data, | |
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273 | sample_f0_time => sample_f0_time, | |
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274 | sample_f1_time => sample_f1_time, | |
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275 | sample_f2_time => sample_f2_time, | |
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276 | sample_f3_time => sample_f3_time | |
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277 | ); | |
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266 | 278 | |
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267 | 279 | ----------------------------------------------------------------------------- |
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268 | 280 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
@@ -393,20 +405,24 BEGIN | |||
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393 | 405 | error_buffer_full => wfp_error_buffer_full, |
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394 | 406 | |
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395 | 407 | coarse_time => coarse_time, |
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396 | fine_time => fine_time, | |
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408 | -- fine_time => fine_time, | |
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397 | 409 | |
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398 | 410 | --f0 |
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399 | 411 | data_f0_in_valid => sample_f0_val, |
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400 | 412 | data_f0_in => sample_f0_data, |
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413 | data_f0_time => sample_f0_time, | |
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401 | 414 | --f1 |
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402 | 415 | data_f1_in_valid => sample_f1_val, |
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403 | 416 | data_f1_in => sample_f1_data, |
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417 | data_f1_time => sample_f1_time, | |
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404 | 418 | --f2 |
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405 | 419 | data_f2_in_valid => sample_f2_val, |
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406 | 420 | data_f2_in => sample_f2_data, |
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421 | data_f2_time => sample_f2_time, | |
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407 | 422 | --f3 |
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408 | 423 | data_f3_in_valid => sample_f3_val, |
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409 | 424 | data_f3_in => sample_f3_data, |
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425 | data_f3_time => sample_f3_time, | |
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410 | 426 | -- OUTPUT -- DMA interface |
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411 | 427 | |
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412 | 428 | dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0), |
@@ -452,14 +468,16 BEGIN | |||
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452 | 468 | start_date => start_date, |
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453 | 469 | |
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454 | 470 | coarse_time => coarse_time, |
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455 | fine_time => fine_time, | |
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456 | 471 | |
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457 | 472 | sample_f0_wen => sample_f0_wen, |
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458 | 473 | sample_f0_wdata => sample_f0_wdata, |
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474 | sample_f0_time => sample_f0_time, | |
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459 | 475 | sample_f1_wen => sample_f1_wen, |
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460 | 476 | sample_f1_wdata => sample_f1_wdata, |
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477 | sample_f1_time => sample_f1_time, | |
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461 | 478 | sample_f2_wen => sample_f2_wen, |
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462 | 479 | sample_f2_wdata => sample_f2_wdata, |
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480 | sample_f2_time => sample_f2_time, | |
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463 | 481 | |
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464 | 482 | --DMA |
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465 | 483 | dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT |
@@ -521,4 +539,4 BEGIN | |||
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521 | 539 | buffer_full_err => dma_buffer_full_err, --buffer_full_err, |
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522 | 540 | grant_error => dma_grant_error); --grant_error); |
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523 | 541 | |
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524 |
END beh; |
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542 | END beh; No newline at end of file |
@@ -50,6 +50,7 ENTITY lpp_lfr_filter IS | |||
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50 | 50 | PORT ( |
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51 | 51 | sample : IN Samples(7 DOWNTO 0); |
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52 | 52 | sample_val : IN STD_LOGIC; |
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53 | sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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53 | 54 |
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54 | 55 | clk : IN STD_LOGIC; |
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55 | 56 | rstn : IN STD_LOGIC; |
@@ -68,7 +69,12 ENTITY lpp_lfr_filter IS | |||
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68 | 69 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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69 | 70 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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70 | 71 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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71 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0) | |
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72 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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73 | -- | |
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74 | sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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75 | sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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76 | sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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77 | sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
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72 | 78 |
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73 | 79 | END lpp_lfr_filter; |
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74 | 80 | |
@@ -159,6 +165,9 ARCHITECTURE tb OF lpp_lfr_filter IS | |||
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159 | 165 | |
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160 | 166 | SIGNAL sample_f0_val_s : STD_LOGIC; |
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161 | 167 | SIGNAL sample_f1_val_s : STD_LOGIC; |
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168 | SIGNAL sample_f1_val_ss : STD_LOGIC; | |
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169 | SIGNAL sample_f2_val_s : STD_LOGIC; | |
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170 | SIGNAL sample_f3_val_s : STD_LOGIC; | |
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162 | 171 | |
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163 | 172 | ----------------------------------------------------------------------------- |
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164 | 173 | -- CONFIG FILTER IIR f0 to f1 |
@@ -214,6 +223,16 ARCHITECTURE tb OF lpp_lfr_filter IS | |||
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214 | 223 | f2_f3_gain); |
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215 | 224 | ----------------------------------------------------------------------------- |
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216 | 225 | |
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226 | SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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227 | SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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228 | SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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229 | SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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230 | SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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231 | SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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232 | SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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233 | -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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234 | -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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235 | SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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217 | 236 | |
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218 | 237 | BEGIN |
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219 | 238 | |
@@ -259,6 +278,24 BEGIN | |||
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259 | 278 | sample_out_val => sample_filter_v2_out_val, |
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260 | 279 | sample_out => sample_filter_v2_out); |
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261 | 280 | |
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281 | -- TIME -- | |
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282 | PROCESS (clk, rstn) | |
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283 | BEGIN -- PROCESS | |
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284 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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285 | sample_time_reg <= (OTHERS => '0'); | |
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286 | sample_filter_v2_out_time <= (OTHERS => '0'); | |
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287 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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288 | IF sample_val = '1' THEN | |
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289 | sample_time_reg <= sample_time; | |
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290 | END IF; | |
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291 | IF sample_filter_v2_out_val = '1' THEN | |
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292 | sample_filter_v2_out_time <= sample_time_reg; | |
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293 | END IF; | |
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294 | END IF; | |
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295 | END PROCESS; | |
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296 | ---------- | |
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297 | ||
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298 | ||
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262 | 299 |
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263 | 300 | -- DATA_SHAPING |
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264 | 301 | ----------------------------------------------------------------------------- |
@@ -336,6 +373,21 BEGIN | |||
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336 | 373 | sample_out_val => sample_f0_val_s, |
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337 | 374 | sample_out => sample_f0); |
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338 | 375 | |
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376 | -- TIME -- | |
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377 | PROCESS (clk, rstn) | |
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378 | BEGIN | |
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379 | IF rstn = '0' THEN | |
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380 | sample_f0_time_reg <= (OTHERS => '0'); | |
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381 | ELSIF clk'event AND clk = '1' THEN | |
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382 | IF sample_f0_val_s = '1' THEN | |
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383 | sample_f0_time_reg <= sample_filter_v2_out_time; | |
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384 | END IF; | |
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385 | END IF; | |
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386 | END PROCESS; | |
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387 | sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg; | |
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388 | sample_f0_time <= sample_f0_time_s; | |
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389 | ---------- | |
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390 | ||
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339 | 391 | sample_f0_val <= sample_f0_val_s; |
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340 | 392 | |
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341 | 393 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
@@ -401,8 +453,26 BEGIN | |||
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401 | 453 | rstn => rstn, |
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402 | 454 | sample_in_val => sample_f1_val_s, |
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403 | 455 | sample_in => sample_f1_s, |
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404 | sample_out_val => sample_f1_val, | |
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405 |
sample_out => sample_f1); |
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456 | sample_out_val => sample_f1_val_ss, | |
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457 | sample_out => sample_f1); | |
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458 | ||
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459 | sample_f1_val <= sample_f1_val_ss; | |
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460 | ||
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461 | -- TIME -- | |
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462 | PROCESS (clk, rstn) | |
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463 | BEGIN | |
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464 | IF rstn = '0' THEN | |
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465 | sample_f1_time_reg <= (OTHERS => '0'); | |
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466 | ELSIF clk'event AND clk = '1' THEN | |
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467 | IF sample_f1_val_ss = '1' THEN | |
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468 | sample_f1_time_reg <= sample_f0_time_s; | |
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469 | END IF; | |
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470 | END IF; | |
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471 | END PROCESS; | |
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472 | sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg; | |
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473 | sample_f1_time <= sample_f1_time_s; | |
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474 | ---------- | |
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475 | ||
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406 | 476 | |
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407 | 477 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
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408 | 478 | all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE |
@@ -509,8 +579,10 BEGIN | |||
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509 | 579 | rstn => rstn, |
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510 | 580 | sample_in_val => sample_f2_filter_val , |
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511 | 581 | sample_in => sample_f2_cic_s, |
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512 | sample_out_val => sample_f2_val, | |
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513 |
sample_out => sample_f2); |
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582 | sample_out_val => sample_f2_val_s, | |
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583 | sample_out => sample_f2); | |
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584 | ||
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585 | sample_f2_val <= sample_f2_val_s; | |
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514 | 586 | |
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515 | 587 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
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516 | 588 | all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE |
@@ -530,14 +602,32 BEGIN | |||
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530 | 602 | rstn => rstn, |
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531 | 603 | sample_in_val => sample_f3_filter_val , |
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532 | 604 | sample_in => sample_f3_cic_s, |
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533 | sample_out_val => sample_f3_val, | |
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605 | sample_out_val => sample_f3_val_s, | |
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534 | 606 | sample_out => sample_f3); |
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607 | sample_f3_val <= sample_f3_val_s; | |
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535 | 608 | |
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536 | 609 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
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537 | 610 | all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE |
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538 | 611 | sample_f3_wdata_s(16*J+I) <= sample_f3(J,I); |
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539 | 612 | END GENERATE all_channel_sample_f3; |
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540 |
END GENERATE all_bit_sample_f3; |
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613 | END GENERATE all_bit_sample_f3; | |
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614 | ||
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615 | ----------------------------------------------------------------------------- | |
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616 | ||
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617 | -- TIME -- | |
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618 | PROCESS (clk, rstn) | |
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619 | BEGIN | |
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620 | IF rstn = '0' THEN | |
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621 | sample_f2_time_reg <= (OTHERS => '0'); | |
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622 | sample_f3_time_reg <= (OTHERS => '0'); | |
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623 | ELSIF clk'event AND clk = '1' THEN | |
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624 | IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF; | |
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625 | IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF; | |
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626 | END IF; | |
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627 | END PROCESS; | |
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628 | sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg; | |
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629 | sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg; | |
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630 | ---------- | |
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541 | 631 | |
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542 | 632 | ----------------------------------------------------------------------------- |
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543 | 633 | -- |
@@ -28,18 +28,20 ENTITY lpp_lfr_ms IS | |||
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28 | 28 | -- DATA INPUT |
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29 | 29 | --------------------------------------------------------------------------- |
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30 | 30 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
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31 | -- TIME | |
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32 |
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33 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
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31 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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32 | --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
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34 | 33 | -- |
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35 | 34 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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36 | 35 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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36 | sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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37 | 37 | -- |
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38 | 38 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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39 | 39 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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40 | sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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40 | 41 | -- |
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41 | 42 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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42 | 43 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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44 | sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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43 | 45 | |
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44 | 46 | --------------------------------------------------------------------------- |
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45 | 47 | -- DMA |
@@ -217,7 +219,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
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217 | 219 | ----------------------------------------------------------------------------- |
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218 | 220 | -- TIME REG & INFOs |
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219 | 221 | ----------------------------------------------------------------------------- |
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220 |
SIGNAL all_time : STD_LOGIC_VECTOR(4 |
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222 | SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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221 | 223 | |
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222 | 224 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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223 | 225 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -1173,7 +1175,8 BEGIN | |||
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1173 | 1175 | ----------------------------------------------------------------------------- |
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1174 | 1176 | -- TIME MANAGMENT |
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1175 | 1177 | ----------------------------------------------------------------------------- |
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1176 | all_time <= coarse_time & fine_time; | |
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1178 | all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time; | |
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1179 | --all_time <= coarse_time & fine_time; | |
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1177 | 1180 | -- |
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1178 | 1181 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; |
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1179 | 1182 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; |
@@ -1197,7 +1200,7 BEGIN | |||
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1197 | 1200 | PORT MAP ( |
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1198 | 1201 | clk => clk, |
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1199 | 1202 | rstn => rstn, |
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1200 | time_in => all_time, | |
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1203 | time_in => all_time((I+1)*48-1 DOWNTO I*48), | |
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1201 | 1204 | update_1 => time_update_f(I), |
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1202 | 1205 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) |
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1203 | 1206 | ); |
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@@ -1,395 +1,403 | |||
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | ||
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4 | LIBRARY grlib; | |
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5 | USE grlib.amba.ALL; | |
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6 | ||
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7 | LIBRARY lpp; | |
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8 | USE lpp.lpp_ad_conv.ALL; | |
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9 | USE lpp.iir_filter.ALL; | |
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10 | USE lpp.FILTERcfg.ALL; | |
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11 | USE lpp.lpp_memory.ALL; | |
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12 | LIBRARY techmap; | |
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13 | USE techmap.gencomp.ALL; | |
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14 | ||
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15 | PACKAGE lpp_lfr_pkg IS | |
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16 | ----------------------------------------------------------------------------- | |
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17 | -- TEMP | |
|
18 | ----------------------------------------------------------------------------- | |
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19 | COMPONENT lpp_lfr_ms_test | |
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20 | GENERIC ( | |
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21 | Mem_use : INTEGER); | |
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22 | PORT ( | |
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23 |
clk |
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24 |
rstn |
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25 | ||
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26 | -- TIME | |
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27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
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28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
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29 | -- | |
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30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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32 | -- | |
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33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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35 | -- | |
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36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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38 | ||
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39 | ||
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40 | ||
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41 | --------------------------------------------------------------------------- | |
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42 |
error_input_fifo_write |
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43 | ||
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44 | -- | |
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45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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49 | ||
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50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
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51 | ||
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52 | -- IN | |
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53 |
MEM_IN_SM_locked |
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54 | ||
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55 | ----------------------------------------------------------------------------- | |
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56 | ||
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57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
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58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
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59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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61 | ||
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62 | SM_correlation_start : OUT STD_LOGIC; | |
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63 | SM_correlation_auto : OUT STD_LOGIC; | |
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64 | SM_correlation_done : IN STD_LOGIC | |
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65 | ); | |
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66 | END COMPONENT; | |
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67 | ||
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68 | ||
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69 | ----------------------------------------------------------------------------- | |
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70 | COMPONENT lpp_lfr_ms | |
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71 | GENERIC ( | |
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72 | Mem_use : INTEGER); | |
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73 | PORT ( | |
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74 | clk : IN STD_LOGIC; | |
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75 | rstn : IN STD_LOGIC; | |
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76 | run : IN STD_LOGIC; | |
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77 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
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78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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79 |
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80 |
sample_f0_w |
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81 |
sample_f0_ |
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82 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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83 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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84 |
sample_f |
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85 |
sample_f2_w |
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86 | dma_fifo_burst_valid : OUT STD_LOGIC; | |
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87 |
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88 |
dma_fifo_ |
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89 |
dma_ |
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90 |
dma_ |
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91 |
dma_buffer_ |
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92 |
dma_buffer_ |
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93 |
dma_buffer_ |
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94 |
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95 |
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96 |
ready_matrix_f |
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97 |
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98 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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99 | status_ready_matrix_f0 : IN STD_LOGIC; | |
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100 | status_ready_matrix_f1 : IN STD_LOGIC; | |
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101 |
status_ready_matrix_f |
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102 |
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103 |
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104 |
addr_matrix_f |
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105 |
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106 |
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107 |
length_matrix_f |
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108 |
matrix_ |
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109 |
matrix_ |
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110 |
matrix_time_f |
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111 |
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112 | END COMPONENT; | |
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113 | ||
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114 | COMPONENT lpp_lfr_ms_fsmdma | |
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115 | PORT ( | |
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116 | clk : IN STD_ULOGIC; | |
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117 | rstn : IN STD_ULOGIC; | |
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118 |
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119 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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120 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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121 |
fifo_ |
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122 |
fifo_ |
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123 | fifo_empty_threshold : IN STD_LOGIC; | |
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124 |
fifo_ |
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125 |
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126 |
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127 |
dma_fifo_ |
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128 |
dma_ |
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129 |
dma_ |
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130 |
dma_buffer_ |
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131 |
dma_buffer_ |
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132 |
dma_buffer_ |
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133 |
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134 |
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135 |
status_ready_matrix_f |
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136 |
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137 |
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138 |
addr_matrix_f |
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139 |
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140 |
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141 |
length_matrix_f |
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142 |
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143 |
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144 |
ready_matrix_f |
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145 |
matrix_ |
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146 |
matrix_ |
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147 |
matrix_time_f |
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148 | error_buffer_full : OUT STD_LOGIC); | |
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149 | END COMPONENT; | |
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150 | ||
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151 | COMPONENT lpp_lfr_ms_FFT | |
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152 | PORT ( | |
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153 | clk : IN STD_LOGIC; | |
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154 | rstn : IN STD_LOGIC; | |
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155 |
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156 |
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157 |
sample_ |
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158 |
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159 | fft_pong : OUT STD_LOGIC; | |
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160 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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161 |
fft_ |
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162 |
fft_data_ |
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163 |
fft_re |
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164 | END COMPONENT; | |
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165 | ||
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166 | COMPONENT lpp_lfr_filter | |
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167 | GENERIC ( | |
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168 | Mem_use : INTEGER); | |
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169 |
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170 | sample : IN Samples(7 DOWNTO 0); | |
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171 | sample_val : IN STD_LOGIC; | |
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172 |
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173 |
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174 | data_shaping_SP0 : IN STD_LOGIC; | |
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175 | data_shaping_SP1 : IN STD_LOGIC; | |
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176 |
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177 |
data_shaping_ |
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178 |
data_shaping_ |
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179 |
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180 |
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181 |
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182 |
sample_f |
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183 |
sample_f |
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184 |
sample_f |
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185 |
sample_f |
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186 |
sample_f |
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187 | END COMPONENT; | |
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188 | ||
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189 | COMPONENT lpp_lfr | |
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190 | GENERIC ( | |
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191 | Mem_use : INTEGER; | |
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192 | nb_data_by_buffer_size : INTEGER; | |
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193 | -- nb_word_by_buffer_size : INTEGER; | |
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194 | nb_snapshot_param_size : INTEGER; | |
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195 | delta_vector_size : INTEGER; | |
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196 | delta_vector_size_f0_2 : INTEGER; | |
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197 | pindex : INTEGER; | |
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198 | paddr : INTEGER; | |
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199 |
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200 | pirq_ms : INTEGER; | |
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201 | pirq_wfp : INTEGER; | |
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202 | hindex : INTEGER; | |
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203 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
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204 | ); | |
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205 | PORT ( | |
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206 |
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207 |
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208 | sample_B : IN Samples(2 DOWNTO 0); | |
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209 | sample_E : IN Samples(4 DOWNTO 0); | |
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210 | sample_val : IN STD_LOGIC; | |
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211 | apbi : IN apb_slv_in_type; | |
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212 | apbo : OUT apb_slv_out_type; | |
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213 | ahbi : IN AHB_Mst_In_Type; | |
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214 | ahbo : OUT AHB_Mst_Out_Type; | |
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215 |
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216 |
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217 | data_shaping_BW : OUT STD_LOGIC ; | |
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218 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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219 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
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220 | ); | |
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221 | END COMPONENT; | |
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222 | ||
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223 | ----------------------------------------------------------------------------- | |
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224 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
|
225 | ----------------------------------------------------------------------------- | |
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226 | COMPONENT lpp_lfr_WFP_nMS | |
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227 | GENERIC ( | |
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228 | Mem_use : INTEGER; | |
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229 | nb_data_by_buffer_size : INTEGER; | |
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230 | nb_word_by_buffer_size : INTEGER; | |
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231 | nb_snapshot_param_size : INTEGER; | |
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232 | delta_vector_size : INTEGER; | |
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233 | delta_vector_size_f0_2 : INTEGER; | |
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234 | pindex : INTEGER; | |
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235 | paddr : INTEGER; | |
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236 |
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237 | pirq_ms : INTEGER; | |
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238 | pirq_wfp : INTEGER; | |
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239 | hindex : INTEGER; | |
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240 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
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241 | PORT ( | |
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242 |
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243 |
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244 | sample_B : IN Samples(2 DOWNTO 0); | |
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245 | sample_E : IN Samples(4 DOWNTO 0); | |
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246 | sample_val : IN STD_LOGIC; | |
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247 | apbi : IN apb_slv_in_type; | |
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248 | apbo : OUT apb_slv_out_type; | |
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249 | ahbi : IN AHB_Mst_In_Type; | |
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250 | ahbo : OUT AHB_Mst_Out_Type; | |
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251 |
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252 |
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253 | data_shaping_BW : OUT STD_LOGIC; | |
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254 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
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255 | END COMPONENT; | |
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256 | ----------------------------------------------------------------------------- | |
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257 | ||
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258 | COMPONENT lpp_lfr_apbreg | |
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259 | GENERIC ( | |
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260 | nb_data_by_buffer_size : INTEGER; | |
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261 | nb_snapshot_param_size : INTEGER; | |
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262 | delta_vector_size : INTEGER; | |
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263 | delta_vector_size_f0_2 : INTEGER; | |
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264 | pindex : INTEGER; | |
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265 | paddr : INTEGER; | |
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266 | pmask : INTEGER; | |
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267 | pirq_ms : INTEGER; | |
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268 | pirq_wfp : INTEGER; | |
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269 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
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270 | PORT ( | |
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271 | HCLK : IN STD_ULOGIC; | |
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272 |
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273 |
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274 |
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275 |
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276 | ready_matrix_f0 : IN STD_LOGIC; | |
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277 | ready_matrix_f1 : IN STD_LOGIC; | |
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278 | ready_matrix_f2 : IN STD_LOGIC; | |
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279 |
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280 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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281 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
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282 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
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283 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
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284 |
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285 |
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286 |
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287 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
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288 |
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289 |
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290 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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291 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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292 |
matrix_ |
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293 |
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294 |
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295 |
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296 |
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297 | data_shaping_R0 : OUT STD_LOGIC; | |
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298 | data_shaping_R1 : OUT STD_LOGIC; | |
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299 | data_shaping_R2 : OUT STD_LOGIC; | |
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300 |
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301 |
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302 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
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303 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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304 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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305 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
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306 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
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307 |
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308 | enable_f1 : OUT STD_LOGIC; | |
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309 |
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310 | enable_f3 : OUT STD_LOGIC; | |
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311 |
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312 |
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313 | burst_f2 : OUT STD_LOGIC; | |
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314 | run : OUT STD_LOGIC; | |
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315 |
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316 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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317 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
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318 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
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319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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322 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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323 |
s |
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324 |
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325 | sample_f3_valid : IN STD_LOGIC; | |
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326 |
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327 | END COMPONENT; | |
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328 | ||
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329 | COMPONENT lpp_top_ms | |
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330 | GENERIC ( | |
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331 | Mem_use : INTEGER; | |
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332 | nb_burst_available_size : INTEGER; | |
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333 | nb_snapshot_param_size : INTEGER; | |
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334 | delta_snapshot_size : INTEGER; | |
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335 | delta_f2_f0_size : INTEGER; | |
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336 | delta_f2_f1_size : INTEGER; | |
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337 | pindex : INTEGER; | |
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338 | paddr : INTEGER; | |
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339 |
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340 | pirq_ms : INTEGER; | |
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341 | pirq_wfp : INTEGER; | |
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342 |
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343 |
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344 | PORT ( | |
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345 |
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346 |
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347 | sample_B : IN Samples14v(2 DOWNTO 0); | |
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348 | sample_E : IN Samples14v(4 DOWNTO 0); | |
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349 | sample_val : IN STD_LOGIC; | |
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350 | apbi : IN apb_slv_in_type; | |
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351 | apbo : OUT apb_slv_out_type; | |
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352 | ahbi_ms : IN AHB_Mst_In_Type; | |
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353 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
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354 | data_shaping_BW : OUT STD_LOGIC; | |
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355 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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356 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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357 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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358 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
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359 | ); | |
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360 | END COMPONENT; | |
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361 | ||
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362 | COMPONENT lpp_apbreg_ms_pointer | |
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363 | PORT ( | |
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364 | clk : IN STD_LOGIC; | |
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365 | rstn : IN STD_LOGIC; | |
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366 | run : IN STD_LOGIC; | |
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367 | reg0_status_ready_matrix : IN STD_LOGIC; | |
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368 | reg0_ready_matrix : OUT STD_LOGIC; | |
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369 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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370 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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371 | reg1_status_ready_matrix : IN STD_LOGIC; | |
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372 | reg1_ready_matrix : OUT STD_LOGIC; | |
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373 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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374 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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375 |
ready_matrix |
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376 |
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377 |
addr_matrix |
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378 |
matrix_time |
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379 | END COMPONENT; | |
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380 | ||
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381 | COMPONENT lpp_lfr_ms_reg_head | |
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382 | PORT ( | |
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383 |
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384 |
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385 | in_wen : IN STD_LOGIC; | |
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386 |
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387 | in_full : IN STD_LOGIC; | |
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388 | in_empty : IN STD_LOGIC; | |
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389 | out_write_error : OUT STD_LOGIC; | |
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390 | out_wen : OUT STD_LOGIC; | |
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391 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
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392 |
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393 | END COMPONENT; | |
|
394 | ||
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395 | END lpp_lfr_pkg; | |
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1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | ||
|
4 | LIBRARY grlib; | |
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5 | USE grlib.amba.ALL; | |
|
6 | ||
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7 | LIBRARY lpp; | |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
|
9 | USE lpp.iir_filter.ALL; | |
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10 | USE lpp.FILTERcfg.ALL; | |
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11 | USE lpp.lpp_memory.ALL; | |
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12 | LIBRARY techmap; | |
|
13 | USE techmap.gencomp.ALL; | |
|
14 | ||
|
15 | PACKAGE lpp_lfr_pkg IS | |
|
16 | ----------------------------------------------------------------------------- | |
|
17 | -- TEMP | |
|
18 | ----------------------------------------------------------------------------- | |
|
19 | COMPONENT lpp_lfr_ms_test | |
|
20 | GENERIC ( | |
|
21 | Mem_use : INTEGER); | |
|
22 | PORT ( | |
|
23 | clk : IN STD_LOGIC; | |
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24 | rstn : IN STD_LOGIC; | |
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25 | ||
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26 | -- TIME | |
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27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
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29 | -- | |
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30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
32 | -- | |
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33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
35 | -- | |
|
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
38 | ||
|
39 | ||
|
40 | ||
|
41 | --------------------------------------------------------------------------- | |
|
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
43 | ||
|
44 | -- | |
|
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
49 | ||
|
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
|
51 | ||
|
52 | -- IN | |
|
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
54 | ||
|
55 | ----------------------------------------------------------------------------- | |
|
56 | ||
|
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
61 | ||
|
62 | SM_correlation_start : OUT STD_LOGIC; | |
|
63 | SM_correlation_auto : OUT STD_LOGIC; | |
|
64 | SM_correlation_done : IN STD_LOGIC | |
|
65 | ); | |
|
66 | END COMPONENT; | |
|
67 | ||
|
68 | ||
|
69 | ----------------------------------------------------------------------------- | |
|
70 | COMPONENT lpp_lfr_ms | |
|
71 | GENERIC ( | |
|
72 | Mem_use : INTEGER); | |
|
73 | PORT ( | |
|
74 | clk : IN STD_LOGIC; | |
|
75 | rstn : IN STD_LOGIC; | |
|
76 | run : IN STD_LOGIC; | |
|
77 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
79 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
80 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
81 | sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
82 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
83 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
84 | sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
85 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
86 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
87 | sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | dma_fifo_burst_valid : OUT STD_LOGIC; | |
|
89 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
90 | dma_fifo_ren : IN STD_LOGIC; | |
|
91 | dma_buffer_new : OUT STD_LOGIC; | |
|
92 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
93 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
94 | dma_buffer_full : IN STD_LOGIC; | |
|
95 | dma_buffer_full_err : IN STD_LOGIC; | |
|
96 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
97 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
98 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
99 | error_buffer_full : OUT STD_LOGIC; | |
|
100 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
101 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
102 | status_ready_matrix_f1 : IN STD_LOGIC; | |
|
103 | status_ready_matrix_f2 : IN STD_LOGIC; | |
|
104 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
105 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
106 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
107 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
108 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
109 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
110 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
111 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
112 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
113 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); | |
|
114 | END COMPONENT; | |
|
115 | ||
|
116 | COMPONENT lpp_lfr_ms_fsmdma | |
|
117 | PORT ( | |
|
118 | clk : IN STD_ULOGIC; | |
|
119 | rstn : IN STD_ULOGIC; | |
|
120 | run : IN STD_LOGIC; | |
|
121 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
122 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
123 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
124 | fifo_empty : IN STD_LOGIC; | |
|
125 | fifo_empty_threshold : IN STD_LOGIC; | |
|
126 | fifo_ren : OUT STD_LOGIC; | |
|
127 | dma_fifo_valid_burst : OUT STD_LOGIC; | |
|
128 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
129 | dma_fifo_ren : IN STD_LOGIC; | |
|
130 | dma_buffer_new : OUT STD_LOGIC; | |
|
131 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
132 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
133 | dma_buffer_full : IN STD_LOGIC; | |
|
134 | dma_buffer_full_err : IN STD_LOGIC; | |
|
135 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
136 | status_ready_matrix_f1 : IN STD_LOGIC; | |
|
137 | status_ready_matrix_f2 : IN STD_LOGIC; | |
|
138 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
139 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
140 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
141 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
142 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
143 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
144 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
145 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
146 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
147 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
148 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
149 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
150 | error_buffer_full : OUT STD_LOGIC); | |
|
151 | END COMPONENT; | |
|
152 | ||
|
153 | COMPONENT lpp_lfr_ms_FFT | |
|
154 | PORT ( | |
|
155 | clk : IN STD_LOGIC; | |
|
156 | rstn : IN STD_LOGIC; | |
|
157 | sample_valid : IN STD_LOGIC; | |
|
158 | fft_read : IN STD_LOGIC; | |
|
159 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
160 | sample_load : OUT STD_LOGIC; | |
|
161 | fft_pong : OUT STD_LOGIC; | |
|
162 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
163 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
164 | fft_data_valid : OUT STD_LOGIC; | |
|
165 | fft_ready : OUT STD_LOGIC); | |
|
166 | END COMPONENT; | |
|
167 | ||
|
168 | COMPONENT lpp_lfr_filter | |
|
169 | GENERIC ( | |
|
170 | Mem_use : INTEGER); | |
|
171 | PORT ( | |
|
172 | sample : IN Samples(7 DOWNTO 0); | |
|
173 | sample_val : IN STD_LOGIC; | |
|
174 | sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
175 | clk : IN STD_LOGIC; | |
|
176 | rstn : IN STD_LOGIC; | |
|
177 | data_shaping_SP0 : IN STD_LOGIC; | |
|
178 | data_shaping_SP1 : IN STD_LOGIC; | |
|
179 | data_shaping_R0 : IN STD_LOGIC; | |
|
180 | data_shaping_R1 : IN STD_LOGIC; | |
|
181 | data_shaping_R2 : IN STD_LOGIC; | |
|
182 | sample_f0_val : OUT STD_LOGIC; | |
|
183 | sample_f1_val : OUT STD_LOGIC; | |
|
184 | sample_f2_val : OUT STD_LOGIC; | |
|
185 | sample_f3_val : OUT STD_LOGIC; | |
|
186 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
187 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
188 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
189 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
190 | sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
191 | sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
192 | sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
193 | sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
194 | ); | |
|
195 | END COMPONENT; | |
|
196 | ||
|
197 | COMPONENT lpp_lfr | |
|
198 | GENERIC ( | |
|
199 | Mem_use : INTEGER; | |
|
200 | nb_data_by_buffer_size : INTEGER; | |
|
201 | -- nb_word_by_buffer_size : INTEGER; | |
|
202 | nb_snapshot_param_size : INTEGER; | |
|
203 | delta_vector_size : INTEGER; | |
|
204 | delta_vector_size_f0_2 : INTEGER; | |
|
205 | pindex : INTEGER; | |
|
206 | paddr : INTEGER; | |
|
207 | pmask : INTEGER; | |
|
208 | pirq_ms : INTEGER; | |
|
209 | pirq_wfp : INTEGER; | |
|
210 | hindex : INTEGER; | |
|
211 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
|
212 | ); | |
|
213 | PORT ( | |
|
214 | clk : IN STD_LOGIC; | |
|
215 | rstn : IN STD_LOGIC; | |
|
216 | sample_B : IN Samples(2 DOWNTO 0); | |
|
217 | sample_E : IN Samples(4 DOWNTO 0); | |
|
218 | sample_val : IN STD_LOGIC; | |
|
219 | apbi : IN apb_slv_in_type; | |
|
220 | apbo : OUT apb_slv_out_type; | |
|
221 | ahbi : IN AHB_Mst_In_Type; | |
|
222 | ahbo : OUT AHB_Mst_Out_Type; | |
|
223 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
224 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
225 | data_shaping_BW : OUT STD_LOGIC; | |
|
226 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
227 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
|
228 | ); | |
|
229 | END COMPONENT; | |
|
230 | ||
|
231 | ----------------------------------------------------------------------------- | |
|
232 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
|
233 | ----------------------------------------------------------------------------- | |
|
234 | COMPONENT lpp_lfr_WFP_nMS | |
|
235 | GENERIC ( | |
|
236 | Mem_use : INTEGER; | |
|
237 | nb_data_by_buffer_size : INTEGER; | |
|
238 | nb_word_by_buffer_size : INTEGER; | |
|
239 | nb_snapshot_param_size : INTEGER; | |
|
240 | delta_vector_size : INTEGER; | |
|
241 | delta_vector_size_f0_2 : INTEGER; | |
|
242 | pindex : INTEGER; | |
|
243 | paddr : INTEGER; | |
|
244 | pmask : INTEGER; | |
|
245 | pirq_ms : INTEGER; | |
|
246 | pirq_wfp : INTEGER; | |
|
247 | hindex : INTEGER; | |
|
248 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
|
249 | PORT ( | |
|
250 | clk : IN STD_LOGIC; | |
|
251 | rstn : IN STD_LOGIC; | |
|
252 | sample_B : IN Samples(2 DOWNTO 0); | |
|
253 | sample_E : IN Samples(4 DOWNTO 0); | |
|
254 | sample_val : IN STD_LOGIC; | |
|
255 | apbi : IN apb_slv_in_type; | |
|
256 | apbo : OUT apb_slv_out_type; | |
|
257 | ahbi : IN AHB_Mst_In_Type; | |
|
258 | ahbo : OUT AHB_Mst_Out_Type; | |
|
259 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
260 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
261 | data_shaping_BW : OUT STD_LOGIC; | |
|
262 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
|
263 | END COMPONENT; | |
|
264 | ----------------------------------------------------------------------------- | |
|
265 | ||
|
266 | COMPONENT lpp_lfr_apbreg | |
|
267 | GENERIC ( | |
|
268 | nb_data_by_buffer_size : INTEGER; | |
|
269 | nb_snapshot_param_size : INTEGER; | |
|
270 | delta_vector_size : INTEGER; | |
|
271 | delta_vector_size_f0_2 : INTEGER; | |
|
272 | pindex : INTEGER; | |
|
273 | paddr : INTEGER; | |
|
274 | pmask : INTEGER; | |
|
275 | pirq_ms : INTEGER; | |
|
276 | pirq_wfp : INTEGER; | |
|
277 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
|
278 | PORT ( | |
|
279 | HCLK : IN STD_ULOGIC; | |
|
280 | HRESETn : IN STD_ULOGIC; | |
|
281 | apbi : IN apb_slv_in_type; | |
|
282 | apbo : OUT apb_slv_out_type; | |
|
283 | run_ms : OUT STD_LOGIC; | |
|
284 | ready_matrix_f0 : IN STD_LOGIC; | |
|
285 | ready_matrix_f1 : IN STD_LOGIC; | |
|
286 | ready_matrix_f2 : IN STD_LOGIC; | |
|
287 | error_buffer_full : IN STD_LOGIC; | |
|
288 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
289 | status_ready_matrix_f0 : OUT STD_LOGIC; | |
|
290 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
|
291 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
|
292 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
293 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
294 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
295 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
296 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
297 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
298 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
299 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
300 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
301 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
302 | data_shaping_BW : OUT STD_LOGIC; | |
|
303 | data_shaping_SP0 : OUT STD_LOGIC; | |
|
304 | data_shaping_SP1 : OUT STD_LOGIC; | |
|
305 | data_shaping_R0 : OUT STD_LOGIC; | |
|
306 | data_shaping_R1 : OUT STD_LOGIC; | |
|
307 | data_shaping_R2 : OUT STD_LOGIC; | |
|
308 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
309 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
310 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
311 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
312 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
313 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
314 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
315 | enable_f0 : OUT STD_LOGIC; | |
|
316 | enable_f1 : OUT STD_LOGIC; | |
|
317 | enable_f2 : OUT STD_LOGIC; | |
|
318 | enable_f3 : OUT STD_LOGIC; | |
|
319 | burst_f0 : OUT STD_LOGIC; | |
|
320 | burst_f1 : OUT STD_LOGIC; | |
|
321 | burst_f2 : OUT STD_LOGIC; | |
|
322 | run : OUT STD_LOGIC; | |
|
323 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
324 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
325 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
|
326 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
|
327 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
328 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
|
329 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
330 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
331 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
332 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
333 | sample_f3_valid : IN STD_LOGIC; | |
|
334 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); | |
|
335 | END COMPONENT; | |
|
336 | ||
|
337 | COMPONENT lpp_top_ms | |
|
338 | GENERIC ( | |
|
339 | Mem_use : INTEGER; | |
|
340 | nb_burst_available_size : INTEGER; | |
|
341 | nb_snapshot_param_size : INTEGER; | |
|
342 | delta_snapshot_size : INTEGER; | |
|
343 | delta_f2_f0_size : INTEGER; | |
|
344 | delta_f2_f1_size : INTEGER; | |
|
345 | pindex : INTEGER; | |
|
346 | paddr : INTEGER; | |
|
347 | pmask : INTEGER; | |
|
348 | pirq_ms : INTEGER; | |
|
349 | pirq_wfp : INTEGER; | |
|
350 | hindex_wfp : INTEGER; | |
|
351 | hindex_ms : INTEGER); | |
|
352 | PORT ( | |
|
353 | clk : IN STD_LOGIC; | |
|
354 | rstn : IN STD_LOGIC; | |
|
355 | sample_B : IN Samples14v(2 DOWNTO 0); | |
|
356 | sample_E : IN Samples14v(4 DOWNTO 0); | |
|
357 | sample_val : IN STD_LOGIC; | |
|
358 | apbi : IN apb_slv_in_type; | |
|
359 | apbo : OUT apb_slv_out_type; | |
|
360 | ahbi_ms : IN AHB_Mst_In_Type; | |
|
361 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
|
362 | data_shaping_BW : OUT STD_LOGIC; | |
|
363 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
364 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
365 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
366 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
367 | ); | |
|
368 | END COMPONENT; | |
|
369 | ||
|
370 | COMPONENT lpp_apbreg_ms_pointer | |
|
371 | PORT ( | |
|
372 | clk : IN STD_LOGIC; | |
|
373 | rstn : IN STD_LOGIC; | |
|
374 | run : IN STD_LOGIC; | |
|
375 | reg0_status_ready_matrix : IN STD_LOGIC; | |
|
376 | reg0_ready_matrix : OUT STD_LOGIC; | |
|
377 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
378 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
379 | reg1_status_ready_matrix : IN STD_LOGIC; | |
|
380 | reg1_ready_matrix : OUT STD_LOGIC; | |
|
381 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
382 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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383 | ready_matrix : IN STD_LOGIC; | |
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384 | status_ready_matrix : OUT STD_LOGIC; | |
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385 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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386 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
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387 | END COMPONENT; | |
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388 | ||
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389 | COMPONENT lpp_lfr_ms_reg_head | |
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390 | PORT ( | |
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391 | clk : IN STD_LOGIC; | |
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392 | rstn : IN STD_LOGIC; | |
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393 | in_wen : IN STD_LOGIC; | |
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394 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
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395 | in_full : IN STD_LOGIC; | |
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396 | in_empty : IN STD_LOGIC; | |
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397 | out_write_error : OUT STD_LOGIC; | |
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398 | out_wen : OUT STD_LOGIC; | |
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399 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
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400 | out_full : OUT STD_LOGIC); | |
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401 | END COMPONENT; | |
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402 | ||
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403 | END lpp_lfr_pkg; No newline at end of file |
@@ -94,20 +94,24 ENTITY lpp_waveform IS | |||
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94 | 94 | --------------------------------------------------------------------------- |
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95 | 95 | -- INPUT |
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96 | 96 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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97 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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97 | -- fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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98 | 98 | |
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99 | 99 | --f0 |
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100 | 100 | data_f0_in_valid : IN STD_LOGIC; |
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101 | 101 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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102 | data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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102 | 103 | --f1 |
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103 | 104 | data_f1_in_valid : IN STD_LOGIC; |
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104 | 105 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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106 | data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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105 | 107 | --f2 |
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106 | 108 | data_f2_in_valid : IN STD_LOGIC; |
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107 | 109 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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110 | data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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108 | 111 | --f3 |
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109 | 112 | data_f3_in_valid : IN STD_LOGIC; |
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110 | 113 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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114 | data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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111 | 115 | |
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112 | 116 | --------------------------------------------------------------------------- |
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113 | 117 | -- DMA -------------------------------------------------------------------- |
@@ -172,8 +176,8 ARCHITECTURE beh OF lpp_waveform IS | |||
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172 | 176 | SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
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173 | 177 | SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); |
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174 | 178 | SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug |
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175 |
SIGNAL time_reg1 : STD_LOGIC_VECTOR(4 |
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176 |
SIGNAL time_reg2 : STD_LOGIC_VECTOR(4 |
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179 | SIGNAL time_reg1 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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180 | SIGNAL time_reg2 : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
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177 | 181 | -- |
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178 | 182 | |
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179 | 183 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b |
@@ -301,7 +305,10 BEGIN -- beh | |||
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301 | 305 | time_reg1 <= (OTHERS => '0'); |
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302 | 306 | time_reg2 <= (OTHERS => '0'); |
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303 | 307 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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304 | time_reg1 <= fine_time & coarse_time; | |
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308 | time_reg1(48*1-1 DOWNTO 48*0) <= data_f0_time(15 DOWNTO 0) & data_f0_time(47 DOWNTO 16); | |
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309 | time_reg1(48*2-1 DOWNTO 48*1) <= data_f1_time(15 DOWNTO 0) & data_f1_time(47 DOWNTO 16); | |
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310 | time_reg1(48*3-1 DOWNTO 48*2) <= data_f2_time(15 DOWNTO 0) & data_f2_time(47 DOWNTO 16); | |
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311 | time_reg1(48*4-1 DOWNTO 48*3) <= data_f3_time(15 DOWNTO 0) & data_f3_time(47 DOWNTO 16); | |
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305 | 312 | time_reg2 <= time_reg1; |
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306 | 313 | END IF; |
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307 | 314 | END PROCESS; |
@@ -315,7 +322,7 BEGIN -- beh | |||
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315 | 322 | run => run, |
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316 | 323 | valid_in => valid_in(I), |
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317 | 324 | ack_in => valid_ack(I), |
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318 | time_in => time_reg2, -- Todo | |
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325 | time_in => time_reg2(48*(I+1)-1 DOWNTO 48*I), -- Todo | |
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319 | 326 | valid_out => valid_out(I), |
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320 | 327 | time_out => time_out(I), -- Todo |
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321 | 328 | error => status_new_err(I)); |
@@ -135,15 +135,19 PACKAGE lpp_waveform_pkg IS | |||
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135 | 135 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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136 | 136 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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137 | 137 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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138 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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138 | --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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139 | 139 | data_f0_in_valid : IN STD_LOGIC; |
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140 | 140 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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141 | data_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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141 | 142 | data_f1_in_valid : IN STD_LOGIC; |
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142 | 143 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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144 | data_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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143 | 145 | data_f2_in_valid : IN STD_LOGIC; |
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144 | 146 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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147 | data_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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145 | 148 | data_f3_in_valid : IN STD_LOGIC; |
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146 | 149 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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150 | data_f3_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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147 | 151 | |
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148 | 152 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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149 | 153 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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