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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | LIBRARY lpp; | |
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4 | USE lpp.lpp_ad_conv.ALL; | |
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5 | ||
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6 | ------------------------------------------------------------------------------- | |
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7 | ||
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8 | ENTITY TB_Data_Acquisition IS | |
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9 | ||
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10 | END TB_Data_Acquisition; | |
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11 | ||
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12 | ------------------------------------------------------------------------------- | |
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13 | ||
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14 | ARCHITECTURE tb OF TB_Data_Acquisition IS | |
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15 | ||
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16 | COMPONENT TestModule_ADS7886 | |
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17 | GENERIC ( | |
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18 | freq : INTEGER; | |
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19 |
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20 |
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21 | PORT ( | |
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22 | cnv_run : IN STD_LOGIC; | |
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23 |
cnv : IN |
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24 |
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25 |
s |
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26 | END COMPONENT; | |
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27 | ||
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28 | COMPONENT Top_Data_Acquisition | |
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29 | PORT ( | |
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30 |
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31 |
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32 |
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33 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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34 | cnv_clk : IN STD_LOGIC; | |
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35 |
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36 | clk : IN STD_LOGIC; | |
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37 | rstn : IN STD_LOGIC; | |
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38 | -- | |
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39 | sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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40 | sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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41 | sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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42 | sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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43 | -- | |
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44 |
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45 | sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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46 |
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47 |
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48 | -- | |
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49 |
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50 |
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51 | sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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52 |
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53 | -- | |
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54 | sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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55 | sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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56 | sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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57 | sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); | |
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58 | END COMPONENT; | |
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59 | ||
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60 | -- component ports | |
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61 | SIGNAL cnv_rstn : STD_LOGIC; | |
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62 | SIGNAL cnv : STD_LOGIC; | |
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63 | SIGNAL rstn : STD_LOGIC; | |
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64 | SIGNAL sck : STD_LOGIC; | |
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65 | SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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66 | SIGNAL run_cnv : STD_LOGIC; | |
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67 | ||
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68 | ||
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69 | -- clock | |
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70 | signal Clk : STD_LOGIC := '1'; | |
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71 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
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72 | ||
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73 | ----------------------------------------------------------------------------- | |
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74 | SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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75 | SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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76 | SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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77 | SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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78 | ----------------------------------------------------------------------------- | |
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79 | SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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80 | SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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81 | SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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82 | SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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83 | ----------------------------------------------------------------------------- | |
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84 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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85 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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86 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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87 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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88 | ----------------------------------------------------------------------------- | |
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89 | SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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90 | SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); | |
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91 | SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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92 | SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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93 | ||
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94 | ||
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95 | BEGIN -- tb | |
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96 | ||
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97 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE | |
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98 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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99 | GENERIC MAP ( | |
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100 | freq => 24*(I+1), | |
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101 | amplitude => 30000/(I+1), | |
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102 | impulsion => 0) | |
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103 | PORT MAP ( | |
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104 | cnv_run => run_cnv, | |
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105 | cnv => cnv, | |
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106 | sck => sck, | |
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107 | sdo => sdo(I)); | |
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108 | END GENERATE MODULE_ADS7886; | |
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109 | ||
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110 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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111 | GENERIC MAP ( | |
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112 | freq => 0, | |
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113 | amplitude => 30000, | |
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114 | impulsion => 1) | |
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115 | PORT MAP ( | |
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116 |
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117 |
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118 |
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119 | sdo => sdo(7)); | |
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120 | ||
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121 | ||
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122 | -- clock generation | |
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123 | Clk <= not Clk after 20 ns; -- 25 Mhz | |
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124 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz | |
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125 | ||
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126 | -- waveform generation | |
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127 | WaveGen_Proc: process | |
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128 | begin | |
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129 | -- insert signal assignments here | |
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130 | wait until Clk = '1'; | |
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131 | rstn <= '0'; | |
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132 | cnv_rstn <= '0'; | |
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133 | run_cnv <= '0'; | |
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134 | wait until Clk = '1'; | |
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135 | wait until Clk = '1'; | |
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136 | wait until Clk = '1'; | |
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137 | rstn <= '1'; | |
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138 | cnv_rstn <= '1'; | |
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139 | wait until Clk = '1'; | |
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140 | wait until Clk = '1'; | |
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141 | wait until Clk = '1'; | |
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142 | wait until Clk = '1'; | |
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143 | wait until Clk = '1'; | |
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144 | wait until Clk = '1'; | |
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145 | run_cnv <= '1'; | |
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146 | wait; | |
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147 | ||
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148 | end process WaveGen_Proc; | |
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149 | ||
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150 | ----------------------------------------------------------------------------- | |
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151 | ||
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152 | Top_Data_Acquisition_1: Top_Data_Acquisition | |
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153 | PORT MAP ( | |
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154 | cnv_run => run_cnv, | |
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155 | cnv => cnv, | |
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156 | sck => sck, | |
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157 | sdo => sdo, | |
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158 | cnv_clk => cnv_clk, | |
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159 | cnv_rstn => cnv_rstn, | |
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160 | clk => clk, | |
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161 | rstn => rstn, | |
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162 | -- | |
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163 | sample_f0_0_ren => sample_f0_0_ren, | |
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164 | sample_f0_0_rdata => sample_f0_0_rdata, | |
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165 | sample_f0_0_full => sample_f0_0_full, | |
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166 | sample_f0_0_empty => sample_f0_0_empty, | |
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167 | -- | |
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168 | sample_f0_1_ren => sample_f0_1_ren, | |
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169 | sample_f0_1_rdata => sample_f0_1_rdata, | |
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170 | sample_f0_1_full => sample_f0_1_full, | |
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171 | sample_f0_1_empty => sample_f0_1_empty, | |
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172 | -- | |
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173 | sample_f1_ren => sample_f1_ren, | |
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174 | sample_f1_rdata => sample_f1_rdata, | |
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175 | sample_f1_full => sample_f1_full, | |
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176 | sample_f1_empty => sample_f1_empty, | |
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177 | -- | |
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178 | sample_f3_ren => sample_f3_ren, | |
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179 | sample_f3_rdata => sample_f3_rdata, | |
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180 | sample_f3_full => sample_f3_full, | |
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181 | sample_f3_empty => sample_f3_empty | |
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182 | ); | |
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183 | sample_f0_0_ren <= (OTHERS => '1'); | |
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184 | sample_f0_1_ren <= (OTHERS => '1'); | |
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185 | sample_f1_ren <= (OTHERS => '1'); | |
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186 | sample_f3_ren <= (OTHERS => '1'); | |
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187 | ||
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188 | END tb; | |
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | LIBRARY lpp; | |
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4 | USE lpp.lpp_ad_conv.ALL; | |
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5 | USE lpp.lpp_top_lfr_pkg.ALL; | |
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6 | ||
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7 | ------------------------------------------------------------------------------- | |
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8 | ||
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9 | ENTITY TB_Data_Acquisition IS | |
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10 | ||
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11 | END TB_Data_Acquisition; | |
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12 | ||
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13 | ------------------------------------------------------------------------------- | |
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14 | ||
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15 | ARCHITECTURE tb OF TB_Data_Acquisition IS | |
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16 | ||
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17 | COMPONENT TestModule_ADS7886 | |
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18 | GENERIC ( | |
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19 | freq : INTEGER; | |
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20 | amplitude : INTEGER; | |
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21 | impulsion : INTEGER); | |
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22 | PORT ( | |
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23 | cnv_run : IN STD_LOGIC; | |
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24 | cnv : IN STD_LOGIC; | |
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25 | sck : IN STD_LOGIC; | |
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26 | sdo : OUT STD_LOGIC); | |
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27 | END COMPONENT; | |
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28 | ||
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29 | -- component ports | |
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30 | SIGNAL cnv_rstn : STD_LOGIC; | |
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31 | SIGNAL cnv : STD_LOGIC; | |
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32 | SIGNAL rstn : STD_LOGIC; | |
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33 | SIGNAL sck : STD_LOGIC; | |
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34 | SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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35 | SIGNAL run_cnv : STD_LOGIC; | |
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36 | ||
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37 | ||
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38 | -- clock | |
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39 | signal Clk : STD_LOGIC := '1'; | |
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40 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
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41 | ||
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42 | ----------------------------------------------------------------------------- | |
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43 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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44 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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45 | ----------------------------------------------------------------------------- | |
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46 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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47 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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48 | ----------------------------------------------------------------------------- | |
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49 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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50 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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51 | ----------------------------------------------------------------------------- | |
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52 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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53 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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54 | ||
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55 | BEGIN -- tb | |
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56 | ||
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57 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE | |
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58 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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59 | GENERIC MAP ( | |
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60 | freq => 24*(I+1), | |
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61 | amplitude => 30000/(I+1), | |
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62 | impulsion => 0) | |
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63 | PORT MAP ( | |
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64 | cnv_run => run_cnv, | |
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65 | cnv => cnv, | |
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66 | sck => sck, | |
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67 | sdo => sdo(I)); | |
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68 | END GENERATE MODULE_ADS7886; | |
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69 | ||
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70 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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71 | GENERIC MAP ( | |
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72 | freq => 0, | |
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73 | amplitude => 30000, | |
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74 | impulsion => 1) | |
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75 | PORT MAP ( | |
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76 | cnv_run => run_cnv, | |
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77 | cnv => cnv, | |
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78 | sck => sck, | |
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79 | sdo => sdo(7)); | |
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80 | ||
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81 | ||
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82 | -- clock generation | |
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83 | Clk <= not Clk after 20 ns; -- 25 Mhz | |
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84 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz | |
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85 | ||
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86 | -- waveform generation | |
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87 | WaveGen_Proc: process | |
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88 | begin | |
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89 | -- insert signal assignments here | |
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90 | wait until Clk = '1'; | |
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91 | rstn <= '0'; | |
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92 | cnv_rstn <= '0'; | |
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93 | run_cnv <= '0'; | |
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94 | wait until Clk = '1'; | |
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95 | wait until Clk = '1'; | |
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96 | wait until Clk = '1'; | |
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97 | rstn <= '1'; | |
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98 | cnv_rstn <= '1'; | |
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99 | wait until Clk = '1'; | |
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100 | wait until Clk = '1'; | |
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101 | wait until Clk = '1'; | |
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102 | wait until Clk = '1'; | |
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103 | wait until Clk = '1'; | |
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104 | wait until Clk = '1'; | |
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105 | run_cnv <= '1'; | |
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106 | wait; | |
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107 | ||
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108 | end process WaveGen_Proc; | |
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109 | ||
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110 | ----------------------------------------------------------------------------- | |
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111 | ||
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112 | Top_Data_Acquisition_1: lpp_top_acq | |
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113 | PORT MAP ( | |
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114 | cnv_run => run_cnv, | |
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115 | cnv => cnv, | |
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116 | sck => sck, | |
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117 | sdo => sdo, | |
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118 | cnv_clk => cnv_clk, | |
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119 | cnv_rstn => cnv_rstn, | |
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120 | clk => clk, | |
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121 | rstn => rstn, | |
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122 | -- | |
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123 | sample_f0_wen => sample_f0_wen, | |
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124 | sample_f0_wdata => sample_f0_wdata, | |
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125 | -- | |
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126 | sample_f1_wen => sample_f1_wen, | |
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127 | sample_f1_wdata => sample_f1_wdata, | |
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128 | -- | |
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129 | sample_f2_wen => sample_f2_wen, | |
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130 | sample_f2_wdata => sample_f2_wdata, | |
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131 | -- | |
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132 | sample_f3_wen => sample_f3_wen, | |
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133 | sample_f3_wdata => sample_f3_wdata | |
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134 | ); | |
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135 | ||
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136 | ||
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137 | ||
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138 | ||
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139 | ||
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140 | END tb; | |
| @@ -1,49 +1,54 | |||
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1 | ||
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2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |
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3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |
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4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |
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5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |
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6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |
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7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |
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8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
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9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |
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10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |
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11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |
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12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |
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13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |
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14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |
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15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |
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16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |
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17 | ||
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18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |
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19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
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20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |
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21 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_C |
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22 |
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23 | ||
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24 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |
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25 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/ |
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26 |
vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_ |
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27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |
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28 | ||
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29 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd | |
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30 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_ |
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31 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFO |
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32 | ||
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33 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd | |
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34 | ||
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35 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
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36 |
vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_ |
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37 | ||
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38 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |
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39 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ |
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40 |
vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ |
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41 | ||
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42 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd | |
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43 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |
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44 | ||
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45 | #vsim work.TB_Data_Acquisition | |
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46 | ||
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47 | #log -r * | |
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48 | #do wave_data_acquisition.do | |
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1 | ||
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2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |
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3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |
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4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |
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5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |
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6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |
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7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |
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8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
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9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |
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10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |
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11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |
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12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |
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13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |
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14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |
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15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |
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16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |
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17 | ||
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18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |
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19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
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20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |
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21 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd | |
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22 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd | |
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23 | #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd | |
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24 | ||
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25 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |
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26 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
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27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |
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28 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |
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29 | ||
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30 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd | |
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31 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd | |
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32 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd | |
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33 | ||
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34 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd | |
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35 | ||
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36 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
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37 | vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |
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38 | ||
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39 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |
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40 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd | |
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41 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd | |
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42 | ||
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43 | ||
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44 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
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45 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd | |
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46 | #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd | |
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47 | ||
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48 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |
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49 | ||
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50 | vsim work.TB_Data_Acquisition | |
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51 | ||
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52 | #log -r * | |
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53 | #do wave_data_acquisition.do | |
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49 | 54 | #run 5 ms No newline at end of file |
| @@ -1,242 +1,49 | |||
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1 | 1 | onerror {resume} |
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2 | 2 | quietly WaveActivateNextPane {} 0 |
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3 |
add wave -noupdate -group { |
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4 |
add wave -noupdate -group { |
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5 |
add wave -noupdate -group { |
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6 |
add wave -noupdate -group { |
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7 |
add wave -noupdate -group { |
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8 |
add wave -noupdate -group { |
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9 |
add wave -noupdate -group { |
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10 |
add wave -noupdate -group { |
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11 |
add wave -noupdate -group { |
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12 |
add wave -noupdate -group { |
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13 |
add wave -noupdate -group { |
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14 |
add wave -noupdate -group { |
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15 |
add wave -noupdate -group { |
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16 |
add wave -noupdate -group { |
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17 |
add wave -noupdate -group { |
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18 |
add wave -noupdate -group { |
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19 |
add wave -noupdate -group { |
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20 |
add wave -noupdate -group { |
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21 |
add wave -noupdate -group { |
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22 |
add wave -noupdate -group { |
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23 |
add wave -noupdate -group { |
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24 |
add wave -noupdate -group F |
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25 |
add wave -noupdate -group FI |
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26 |
add wave -noupdate -group FI |
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27 |
add wave -noupdate -group FI |
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28 |
add wave -noupdate -group FI |
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29 |
add wave -noupdate -group FI |
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30 |
add wave -noupdate -group FI |
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31 |
add wave -noupdate -group FI |
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32 |
add wave -noupdate -group FI |
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33 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk | |
|
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34 | add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in | |
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35 | add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out | |
|
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36 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos | |
|
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37 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest | |
|
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38 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs | |
|
|
39 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old | |
|
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40 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel | |
|
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41 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read | |
|
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42 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr | |
|
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43 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count | |
|
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44 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write | |
|
|
45 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel | |
|
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46 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0 | |
|
|
47 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in | |
|
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48 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk | |
|
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49 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out | |
|
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50 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl | |
|
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51 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in | |
|
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52 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in | |
|
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53 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out | |
|
|
54 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel | |
|
|
55 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan | |
|
|
56 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff | |
|
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57 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff | |
|
|
58 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg | |
|
|
59 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state | |
|
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60 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run | |
|
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61 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv | |
|
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62 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck | |
|
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63 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo | |
|
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64 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk | |
|
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65 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn | |
|
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66 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk | |
|
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67 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn | |
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68 | add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample | |
|
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69 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val | |
|
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70 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs | |
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71 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in | |
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72 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out | |
|
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73 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state | |
|
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74 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff | |
|
|
75 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing | |
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76 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing | |
|
|
77 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk | |
|
|
78 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset | |
|
|
79 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl | |
|
|
80 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1 | |
|
|
81 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2 | |
|
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82 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res | |
|
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83 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input | |
|
|
84 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
|
|
85 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
|
|
86 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn | |
|
|
87 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk | |
|
|
88 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos | |
|
|
89 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs | |
|
|
90 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src | |
|
|
91 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata | |
|
|
92 | add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input | |
|
|
93 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write | |
|
|
94 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read | |
|
|
95 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst | |
|
|
96 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 | |
|
|
97 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous | |
|
|
98 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input | |
|
|
99 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff | |
|
|
100 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl | |
|
|
101 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in | |
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|
102 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out | |
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|
103 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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|
104 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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|
105 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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|
106 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample | |
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|
107 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s | |
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|
108 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff | |
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109 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s | |
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110 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef | |
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111 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn | |
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112 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk | |
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113 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos | |
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114 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs | |
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115 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
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116 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
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117 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
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118 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
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119 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src | |
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120 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata | |
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121 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write | |
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122 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read | |
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123 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst | |
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124 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1 | |
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125 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous | |
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126 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input | |
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127 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff | |
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128 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl | |
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129 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf | |
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130 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate | |
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131 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s | |
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132 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s | |
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133 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 | |
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134 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s | |
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135 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s | |
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136 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 | |
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137 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src | |
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138 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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139 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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140 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in | |
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141 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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142 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous | |
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143 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write | |
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144 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata | |
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145 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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146 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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147 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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148 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input | |
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149 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read | |
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150 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst | |
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151 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 | |
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152 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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153 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff | |
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154 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s | |
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155 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef | |
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156 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff | |
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157 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input | |
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158 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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159 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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160 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl | |
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161 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef | |
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162 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample | |
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163 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s | |
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164 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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165 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state | |
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166 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing | |
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167 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing | |
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168 | add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out | |
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169 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn | |
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170 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk | |
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171 | add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray | |
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172 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter | |
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173 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst | |
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174 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1 | |
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175 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous | |
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176 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write | |
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177 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen | |
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178 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr | |
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179 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd | |
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180 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in | |
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181 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read | |
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182 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren | |
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183 | add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr | |
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184 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd | |
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185 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out | |
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186 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
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187 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
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188 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
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189 | add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
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190 | add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) | |
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191 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk | |
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192 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset | |
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193 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac | |
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194 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add | |
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195 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1 | |
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196 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2 | |
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197 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res | |
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198 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add | |
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199 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult | |
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200 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout | |
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201 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina | |
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202 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb | |
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203 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout | |
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204 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel | |
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205 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz | |
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206 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz | |
|
|
207 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel | |
|
|
208 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d | |
|
|
209 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d | |
|
|
210 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d | |
|
|
211 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d | |
|
|
212 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d | |
|
|
213 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d | |
|
|
214 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d | |
|
|
215 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d | |
|
|
216 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d | |
|
|
217 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val | |
|
|
218 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot | |
|
|
219 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state | |
|
|
220 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out | |
|
|
221 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s | |
|
|
222 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 | |
|
|
223 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s | |
|
|
224 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s | |
|
|
225 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 | |
|
|
3 | add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample | |
|
|
4 | add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val | |
|
|
5 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
|
|
6 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
|
|
7 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
|
|
8 | add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
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|
9 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val | |
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|
10 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in | |
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|
11 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val | |
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|
12 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out | |
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|
13 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val | |
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|
14 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in | |
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|
15 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val | |
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16 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out | |
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|
17 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val | |
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18 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in | |
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|
19 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val | |
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20 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out | |
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21 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val | |
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22 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in | |
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|
23 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val | |
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|
24 | add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out | |
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|
25 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen | |
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26 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata | |
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27 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen | |
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28 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata | |
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29 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen | |
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30 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata | |
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31 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen | |
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32 | add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata | |
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226 | 33 | TreeUpdate [SetDefaultTree] |
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227 |
WaveRestoreCursors {{Cursor 1} { |
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228 |
configure wave -namecolwidth |
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34 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} | |
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35 | configure wave -namecolwidth 430 | |
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229 | 36 | configure wave -valuecolwidth 100 |
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230 | 37 | configure wave -justifyvalue left |
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231 | 38 | configure wave -signalnamewidth 0 |
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232 | 39 | configure wave -snapdistance 10 |
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233 | 40 | configure wave -datasetprefix 0 |
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234 | 41 | configure wave -rowmargin 4 |
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235 | 42 | configure wave -childrowmargin 2 |
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236 | 43 | configure wave -gridoffset 0 |
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237 | 44 | configure wave -gridperiod 1 |
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238 | 45 | configure wave -griddelta 40 |
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239 | 46 | configure wave -timeline 0 |
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240 | 47 | configure wave -timelineunits ns |
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241 | 48 | update |
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242 |
WaveRestoreZoom { |
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49 | WaveRestoreZoom {0 ps} {754717 ps} | |
| @@ -1,250 +1,251 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
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4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Jean-christophe PELLION |
|
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
|
21 | 21 | ------------------------------------------------------------------------------- |
|
|
22 | 22 | LIBRARY IEEE; |
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|
23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
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25 | 25 | LIBRARY lpp; |
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26 | 26 | USE lpp.iir_filter.ALL; |
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27 | 27 | USE lpp.general_purpose.ALL; |
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|
28 | 28 | |
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29 | 29 | |
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30 | 30 | |
|
|
31 | 31 | ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS |
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|
32 | 32 | GENERIC( |
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33 | 33 | tech : INTEGER := 0; |
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34 | 34 | Mem_use : INTEGER := use_RAM; |
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|
35 | 35 | Sample_SZ : INTEGER := 16; |
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|
36 | 36 | Coef_SZ : INTEGER := 9; |
|
|
37 | 37 | Coef_Nb : INTEGER := 30; |
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|
38 | 38 | Coef_sel_SZ : INTEGER := 5 |
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39 | 39 | ); |
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40 | 40 | PORT( |
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41 | 41 | rstn : IN STD_LOGIC; |
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42 | 42 | clk : IN STD_LOGIC; |
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|
43 | 43 | -- PARAMETER |
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|
44 | 44 | virg_pos : IN INTEGER; |
|
|
45 | 45 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); |
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46 | 46 | -- CONTROL |
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47 | 47 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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48 | 48 | -- |
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49 | 49 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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50 | 50 | ram_write : IN STD_LOGIC; |
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51 | 51 | ram_read : IN STD_LOGIC; |
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52 | 52 | raddr_rst : IN STD_LOGIC; |
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53 | 53 | raddr_add1 : IN STD_LOGIC; |
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54 | 54 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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55 | 55 | -- |
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56 | 56 | alu_sel_input : IN STD_LOGIC; |
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57 | 57 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); |
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58 | 58 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) |
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59 | 59 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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60 | 60 | -- DATA |
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61 | 61 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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62 | 62 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) |
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63 | 63 | ); |
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64 | 64 | END IIR_CEL_CTRLR_v2_DATAFLOW; |
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65 | 65 | |
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66 | 66 | ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS |
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67 | 67 | |
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68 | 68 | COMPONENT RAM_CTRLR_v2 |
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69 | 69 | GENERIC ( |
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70 | 70 | tech : INTEGER; |
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71 | 71 | Input_SZ_1 : INTEGER; |
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72 | 72 | Mem_use : INTEGER); |
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73 | 73 | PORT ( |
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74 | 74 | rstn : IN STD_LOGIC; |
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75 | 75 | clk : IN STD_LOGIC; |
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76 | 76 | ram_write : IN STD_LOGIC; |
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77 | 77 | ram_read : IN STD_LOGIC; |
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78 | 78 | raddr_rst : IN STD_LOGIC; |
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79 | 79 | raddr_add1 : IN STD_LOGIC; |
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80 | 80 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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81 | 81 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
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82 | 82 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); |
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83 | 83 | END COMPONENT; |
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84 | 84 | |
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85 | 85 | SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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86 | 86 | SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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87 | 87 | SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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88 | 88 | SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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89 | 89 | SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
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90 | 90 | SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); |
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91 | 91 | |
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92 | 92 | SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); |
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93 | 93 | SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); |
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94 | 94 | |
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95 | 95 | SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); |
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96 | 96 | |
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97 | 97 | BEGIN |
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98 | 98 | |
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99 | 99 | ----------------------------------------------------------------------------- |
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100 | 100 | -- INPUT |
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101 | 101 | ----------------------------------------------------------------------------- |
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102 | 102 | PROCESS (clk, rstn) |
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103 | 103 | BEGIN -- PROCESS |
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104 | 104 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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105 | 105 | reg_sample_in <= (OTHERS => '0'); |
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106 | 106 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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107 | 107 | CASE in_sel_src IS |
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108 | 108 | WHEN "00" => reg_sample_in <= reg_sample_in; |
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109 | 109 | WHEN "01" => reg_sample_in <= sample_in; |
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110 | 110 | WHEN "10" => reg_sample_in <= ram_output; |
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111 | 111 | WHEN "11" => reg_sample_in <= alu_output; |
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112 | 112 | WHEN OTHERS => NULL; |
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113 | 113 | END CASE; |
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114 | 114 | END IF; |
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115 | 115 | END PROCESS; |
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116 | 116 | |
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117 | 117 | |
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118 | 118 | ----------------------------------------------------------------------------- |
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119 | 119 | -- RAM + CTRL |
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120 | 120 | ----------------------------------------------------------------------------- |
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121 | 121 | |
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122 | 122 | ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE |
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123 | 123 | alu_output WHEN ram_sel_Wdata = "01" ELSE |
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124 | 124 | ram_output; |
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125 | 125 | |
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126 | 126 | RAM_CTRLR_v2_1: RAM_CTRLR_v2 |
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127 | 127 | GENERIC MAP ( |
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128 | 128 | tech => tech, |
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129 | 129 | Input_SZ_1 => Sample_SZ, |
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130 | 130 | Mem_use => Mem_use) |
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131 | 131 | PORT MAP ( |
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132 | 132 | clk => clk, |
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133 | 133 | rstn => rstn, |
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134 | 134 | ram_write => ram_write, |
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135 | 135 | ram_read => ram_read, |
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136 | 136 | raddr_rst => raddr_rst, |
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137 | 137 | raddr_add1 => raddr_add1, |
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138 | 138 | waddr_previous => waddr_previous, |
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139 | 139 | sample_in => ram_input, |
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140 | 140 | sample_out => ram_output); |
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141 | 141 | |
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142 | 142 | ----------------------------------------------------------------------------- |
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143 | 143 | -- MAC_ACC |
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144 | 144 | ----------------------------------------------------------------------------- |
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145 | 145 | -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) |
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146 | 146 | -- Data In : mac_sample, mac_coef |
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147 | 147 | -- Data Out: mac_output |
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148 | 148 | |
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149 | 149 | alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; |
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150 | 150 | |
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151 | 151 | coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE |
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152 | 152 | coeff_in: IF I < Coef_Nb GENERATE |
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153 | 153 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE |
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154 | 154 | arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); |
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155 | 155 | END GENERATE all_bit; |
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156 | 156 | END GENERATE coeff_in; |
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157 | 157 | coeff_null: IF I > (Coef_Nb -1) GENERATE |
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158 | 158 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE |
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159 | 159 | arrayCoeff(I,J) <= '0'; |
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160 | 160 | END GENERATE all_bit; |
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161 | 161 | END GENERATE coeff_null; |
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162 | 162 | END GENERATE coefftable; |
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163 | 163 | |
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164 | 164 | Coeff_Mux : MUXN |
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165 | 165 | GENERIC MAP ( |
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166 | 166 | Input_SZ => Coef_SZ, |
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167 | 167 | NbStage => Coef_sel_SZ) |
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168 | 168 | PORT MAP ( |
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169 | 169 | sel => alu_sel_coeff, |
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170 | 170 | INPUT => arrayCoeff, |
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171 | 171 | RES => alu_coef_s); |
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172 | 172 | |
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173 | 173 | |
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174 | 174 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE |
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175 | 175 | alu_coef(J) <= alu_coef_s(J); |
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176 | 176 | END GENERATE all_bit; |
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177 | 177 | |
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178 | 178 | ----------------------------------------------------------------------------- |
|
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179 | 179 | -- TODO : just for Synthesis test |
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180 | 180 | |
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181 | 181 | --PROCESS (clk, rstn) |
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182 | 182 | --BEGIN |
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183 | 183 | -- IF rstn = '0' THEN |
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184 | 184 | -- alu_coef <= (OTHERS => '0'); |
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185 | 185 | -- ELSIF clk'event AND clk = '1' THEN |
|
|
186 | 186 | -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP |
|
|
187 | 187 | -- alu_coef(J) <= alu_coef_s(J); |
|
|
188 | 188 | -- END LOOP all_bit; |
|
|
189 | 189 | -- END IF; |
|
|
190 | 190 | --END PROCESS; |
|
|
191 | 191 | |
|
|
192 | 192 | ----------------------------------------------------------------------------- |
|
|
193 | 193 | |
|
|
194 | 194 | |
|
|
195 | 195 | ALU_1: ALU |
|
|
196 | 196 | GENERIC MAP ( |
|
|
197 | 197 | Arith_en => 1, |
|
|
198 | 198 | Input_SZ_1 => Sample_SZ, |
|
|
199 |
Input_SZ_2 => Coef_SZ |
|
|
|
199 | Input_SZ_2 => Coef_SZ, | |
|
|
200 | COMP_EN => 1) | |
|
|
200 | 201 | PORT MAP ( |
|
|
201 | 202 | clk => clk, |
|
|
202 | 203 | reset => rstn, |
|
|
203 | 204 | ctrl => alu_ctrl, |
|
|
204 | 205 | comp => alu_comp, |
|
|
205 | 206 | OP1 => alu_sample, |
|
|
206 | 207 | OP2 => alu_coef, |
|
|
207 | 208 | RES => alu_output_s); |
|
|
208 | 209 | |
|
|
209 | 210 | alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); |
|
|
210 | 211 | |
|
|
211 | 212 | sample_out <= alu_output; |
|
|
212 | 213 | |
|
|
213 | 214 | END ar_IIR_CEL_CTRLR_v2_DATAFLOW; |
|
|
214 | 215 | |
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215 | 216 | |
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216 | 217 | |
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217 | 218 | |
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218 | 219 | |
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219 | 220 | |
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220 | 221 | |
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221 | 222 | |
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222 | 223 | |
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223 | 224 | |
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224 | 225 | |
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225 | 226 | |
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226 | 227 | |
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227 | 228 | |
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228 | 229 | |
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229 | 230 | |
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230 | 231 | |
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231 | 232 | |
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232 | 233 | |
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233 | 234 | |
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234 | 235 | |
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235 | 236 | |
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236 | 237 | |
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237 | 238 | |
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238 | 239 | |
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239 | 240 | |
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240 | 241 | |
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241 | 242 | |
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242 | 243 | |
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243 | 244 | |
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244 | 245 | |
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245 | 246 | |
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246 | 247 | |
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247 | 248 | |
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248 | 249 | |
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249 | 250 | |
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250 | 251 | |
| @@ -1,120 +1,120 | |||
|
|
1 | 1 | ------------------------------------------------------------------------------ |
|
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Alexis Jeandet |
|
|
20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
|
21 | 21 | ---------------------------------------------------------------------------- |
|
|
22 | 22 | LIBRARY IEEE; |
|
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
|
25 | 25 | LIBRARY lpp; |
|
|
26 | 26 | USE lpp.iir_filter.ALL; |
|
|
27 | 27 | USE lpp.FILTERcfg.ALL; |
|
|
28 | 28 | USE lpp.general_purpose.ALL; |
|
|
29 | 29 | LIBRARY techmap; |
|
|
30 | 30 | USE techmap.gencomp.ALL; |
|
|
31 | 31 | |
|
|
32 | 32 | ENTITY RAM_CTRLR_v2 IS |
|
|
33 | 33 | GENERIC( |
|
|
34 | 34 | tech : INTEGER := 0; |
|
|
35 | 35 | Input_SZ_1 : INTEGER := 16; |
|
|
36 | 36 | Mem_use : INTEGER := use_RAM |
|
|
37 | 37 | ); |
|
|
38 | 38 | PORT( |
|
|
39 | 39 | rstn : IN STD_LOGIC; |
|
|
40 | 40 | clk : IN STD_LOGIC; |
|
|
41 | 41 | -- R/W Ctrl |
|
|
42 | 42 | ram_write : IN STD_LOGIC; |
|
|
43 | 43 | ram_read : IN STD_LOGIC; |
|
|
44 | 44 | -- ADDR Ctrl |
|
|
45 | 45 | raddr_rst : IN STD_LOGIC; |
|
|
46 | 46 | raddr_add1 : IN STD_LOGIC; |
|
|
47 | 47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
48 | 48 | -- Data |
|
|
49 | 49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
|
50 | 50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
|
|
51 | 51 | ); |
|
|
52 | 52 | END RAM_CTRLR_v2; |
|
|
53 | 53 | |
|
|
54 | 54 | |
|
|
55 | 55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS |
|
|
56 | 56 | |
|
|
57 | 57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
|
58 | 58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
|
59 | 59 | SIGNAL WEN, REN : STD_LOGIC; |
|
|
60 | 60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
|
61 | 61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
|
62 | 62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
|
63 | 63 | |
|
|
64 | 64 | BEGIN |
|
|
65 | 65 | |
|
|
66 | 66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); |
|
|
67 | 67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; |
|
|
68 | 68 | ----------------------------------------------------------------------------- |
|
|
69 | 69 | -- RAM |
|
|
70 | 70 | ----------------------------------------------------------------------------- |
|
|
71 | 71 | |
|
|
72 | 72 | memCEL : IF Mem_use = use_CEL GENERATE |
|
|
73 | 73 | WEN <= NOT ram_write; |
|
|
74 | 74 | REN <= NOT ram_read; |
|
|
75 | RAMblk : RAM_CEL | |
|
|
75 | RAMblk : RAM_CEL_N | |
|
|
76 | 76 | GENERIC MAP(Input_SZ_1) |
|
|
77 | 77 | PORT MAP( |
|
|
78 | 78 | WD => WD, |
|
|
79 | 79 | RD => RD, |
|
|
80 | 80 | WEN => WEN, |
|
|
81 | 81 | REN => REN, |
|
|
82 | 82 | WADDR => WADDR, |
|
|
83 | 83 | RADDR => RADDR, |
|
|
84 | 84 | RWCLK => clk, |
|
|
85 | 85 | RESET => rstn |
|
|
86 | 86 | ) ; |
|
|
87 | 87 | END GENERATE; |
|
|
88 | 88 | |
|
|
89 | 89 | memRAM : IF Mem_use = use_RAM GENERATE |
|
|
90 | 90 | SRAM : syncram_2p |
|
|
91 | 91 | GENERIC MAP(tech, 8, Input_SZ_1) |
|
|
92 | 92 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); |
|
|
93 | 93 | END GENERATE; |
|
|
94 | 94 | |
|
|
95 | 95 | ----------------------------------------------------------------------------- |
|
|
96 | 96 | -- RADDR |
|
|
97 | 97 | ----------------------------------------------------------------------------- |
|
|
98 | 98 | PROCESS (clk, rstn) |
|
|
99 | 99 | BEGIN -- PROCESS |
|
|
100 | 100 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|
101 | 101 | counter <= (OTHERS => '0'); |
|
|
102 | 102 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|
103 | 103 | IF raddr_rst = '1' THEN |
|
|
104 | 104 | counter <= (OTHERS => '0'); |
|
|
105 | 105 | ELSIF raddr_add1 = '1' THEN |
|
|
106 | 106 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); |
|
|
107 | 107 | END IF; |
|
|
108 | 108 | END IF; |
|
|
109 | 109 | END PROCESS; |
|
|
110 | 110 | RADDR <= counter; |
|
|
111 | 111 | |
|
|
112 | 112 | ----------------------------------------------------------------------------- |
|
|
113 | 113 | -- WADDR |
|
|
114 | 114 | ----------------------------------------------------------------------------- |
|
|
115 | 115 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE |
|
|
116 | 116 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE |
|
|
117 | 117 | STD_LOGIC_VECTOR(UNSIGNED(counter)); |
|
|
118 | 118 | |
|
|
119 | 119 | |
|
|
120 | 120 | END ar_RAM_CTRLR_v2; |
| @@ -1,290 +1,302 | |||
|
|
1 | 1 | ------------------------------------------------------------------------------ |
|
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Alexis Jeandet |
|
|
20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
|
21 | 21 | ---------------------------------------------------------------------------- |
|
|
22 | 22 | LIBRARY ieee; |
|
|
23 | 23 | USE ieee.std_logic_1164.ALL; |
|
|
24 | 24 | LIBRARY grlib; |
|
|
25 | 25 | USE grlib.amba.ALL; |
|
|
26 | 26 | USE grlib.stdlib.ALL; |
|
|
27 | 27 | USE grlib.devices.ALL; |
|
|
28 | 28 | LIBRARY lpp; |
|
|
29 | 29 | |
|
|
30 | 30 | |
|
|
31 | 31 | |
|
|
32 | 32 | |
|
|
33 | 33 | PACKAGE iir_filter IS |
|
|
34 | 34 | |
|
|
35 | 35 | |
|
|
36 | 36 | --===========================================================| |
|
|
37 | 37 | --================A L U C O N T R O L======================| |
|
|
38 | 38 | --===========================================================| |
|
|
39 | 39 | CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; |
|
|
40 | 40 | CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; |
|
|
41 | 41 | CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; |
|
|
42 | 42 | CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; |
|
|
43 | 43 | CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; |
|
|
44 | 44 | CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101"; |
|
|
45 | 45 | |
|
|
46 | 46 | --____ |
|
|
47 | 47 | --RAM | |
|
|
48 | 48 | --____| |
|
|
49 | 49 | CONSTANT use_RAM : INTEGER := 1; |
|
|
50 | 50 | CONSTANT use_CEL : INTEGER := 0; |
|
|
51 | 51 | |
|
|
52 | 52 | |
|
|
53 | 53 | --===========================================================| |
|
|
54 | 54 | --=============C O E F S ====================================| |
|
|
55 | 55 | --===========================================================| |
|
|
56 | 56 | -- create a specific type of data for coefs to avoid errors | |
|
|
57 | 57 | --===========================================================| |
|
|
58 | 58 | |
|
|
59 | 59 | TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER; |
|
|
60 | 60 | |
|
|
61 | 61 | TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
|
62 | 62 | |
|
|
63 | 63 | TYPE in_IIR_CEL_reg IS RECORD |
|
|
64 | 64 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
65 | 65 | virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
66 | 66 | END RECORD; |
|
|
67 | 67 | |
|
|
68 | 68 | TYPE out_IIR_CEL_reg IS RECORD |
|
|
69 | 69 | config : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
70 | 70 | status : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
71 | 71 | END RECORD; |
|
|
72 | 72 | |
|
|
73 | 73 | |
|
|
74 | 74 | COMPONENT APB_IIR_CEL IS |
|
|
75 | 75 | GENERIC ( |
|
|
76 | 76 | tech : INTEGER := 0; |
|
|
77 | 77 | pindex : INTEGER := 0; |
|
|
78 | 78 | paddr : INTEGER := 0; |
|
|
79 | 79 | pmask : INTEGER := 16#fff#; |
|
|
80 | 80 | pirq : INTEGER := 0; |
|
|
81 | 81 | abits : INTEGER := 8; |
|
|
82 | 82 | Sample_SZ : INTEGER := 16; |
|
|
83 | 83 | ChanelsCount : INTEGER := 6; |
|
|
84 | 84 | Coef_SZ : INTEGER := 9; |
|
|
85 | 85 | CoefCntPerCel : INTEGER := 6; |
|
|
86 | 86 | Cels_count : INTEGER := 5; |
|
|
87 | 87 | virgPos : INTEGER := 7; |
|
|
88 | 88 | Mem_use : INTEGER := use_RAM |
|
|
89 | 89 | ); |
|
|
90 | 90 | PORT ( |
|
|
91 | 91 | rst : IN STD_LOGIC; |
|
|
92 | 92 | clk : IN STD_LOGIC; |
|
|
93 | 93 | apbi : IN apb_slv_in_type; |
|
|
94 | 94 | apbo : OUT apb_slv_out_type; |
|
|
95 | 95 | sample_clk : IN STD_LOGIC; |
|
|
96 | 96 | sample_clk_out : OUT STD_LOGIC; |
|
|
97 | 97 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
98 | 98 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
99 | 99 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') |
|
|
100 | 100 | ); |
|
|
101 | 101 | END COMPONENT; |
|
|
102 | 102 | |
|
|
103 | 103 | |
|
|
104 | 104 | COMPONENT Top_IIR IS |
|
|
105 | 105 | GENERIC( |
|
|
106 | 106 | Sample_SZ : INTEGER := 18; |
|
|
107 | 107 | ChanelsCount : INTEGER := 1; |
|
|
108 | 108 | Coef_SZ : INTEGER := 9; |
|
|
109 | 109 | CoefCntPerCel : INTEGER := 6; |
|
|
110 | 110 | Cels_count : INTEGER := 5); |
|
|
111 | 111 | PORT( |
|
|
112 | 112 | reset : IN STD_LOGIC; |
|
|
113 | 113 | clk : IN STD_LOGIC; |
|
|
114 | 114 | sample_clk : IN STD_LOGIC; |
|
|
115 | 115 | -- BP : in std_logic; |
|
|
116 | 116 | -- BPinput : in std_logic_vector(3 downto 0); |
|
|
117 | 117 | LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
118 | 118 | INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
119 | 119 | OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0) |
|
|
120 | 120 | ); |
|
|
121 | 121 | END COMPONENT; |
|
|
122 | 122 | |
|
|
123 | 123 | COMPONENT IIR_CEL_CTRLR_v2 |
|
|
124 | 124 | GENERIC ( |
|
|
125 | 125 | tech : INTEGER; |
|
|
126 | 126 | Mem_use : INTEGER; |
|
|
127 | 127 | Sample_SZ : INTEGER; |
|
|
128 | 128 | Coef_SZ : INTEGER; |
|
|
129 | 129 | Coef_Nb : INTEGER; |
|
|
130 | 130 | Coef_sel_SZ : INTEGER; |
|
|
131 | 131 | Cels_count : INTEGER; |
|
|
132 | 132 | ChanelsCount : INTEGER); |
|
|
133 | 133 | PORT ( |
|
|
134 | 134 | rstn : IN STD_LOGIC; |
|
|
135 | 135 | clk : IN STD_LOGIC; |
|
|
136 | 136 | virg_pos : IN INTEGER; |
|
|
137 | 137 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); |
|
|
138 | 138 | sample_in_val : IN STD_LOGIC; |
|
|
139 | 139 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
140 | 140 | sample_out_val : OUT STD_LOGIC; |
|
|
141 | 141 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); |
|
|
142 | 142 | END COMPONENT; |
|
|
143 | 143 | |
|
|
144 | 144 | |
|
|
145 | 145 | --component FilterCTRLR is |
|
|
146 | 146 | --port( |
|
|
147 | 147 | -- reset : in std_logic; |
|
|
148 | 148 | -- clk : in std_logic; |
|
|
149 | 149 | -- sample_clk : in std_logic; |
|
|
150 | 150 | -- ALU_Ctrl : out std_logic_vector(3 downto 0); |
|
|
151 | 151 | -- sample_in : in samplT; |
|
|
152 | 152 | -- coef : out std_logic_vector(Coef_SZ-1 downto 0); |
|
|
153 | 153 | -- sample : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
|
154 | 154 | --); |
|
|
155 | 155 | --end component; |
|
|
156 | 156 | |
|
|
157 | 157 | |
|
|
158 | 158 | --component FILTER_RAM_CTRLR is |
|
|
159 | 159 | --port( |
|
|
160 | 160 | -- reset : in std_logic; |
|
|
161 | 161 | -- clk : in std_logic; |
|
|
162 | 162 | -- run : in std_logic; |
|
|
163 | 163 | -- GO_0 : in std_logic; |
|
|
164 | 164 | -- B_A : in std_logic; |
|
|
165 | 165 | -- writeForce : in std_logic; |
|
|
166 | 166 | -- next_blk : in std_logic; |
|
|
167 | 167 | -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); |
|
|
168 | 168 | -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) |
|
|
169 | 169 | --); |
|
|
170 | 170 | --end component; |
|
|
171 | 171 | |
|
|
172 | 172 | |
|
|
173 | 173 | COMPONENT IIR_CEL_CTRLR IS |
|
|
174 | 174 | GENERIC( |
|
|
175 | 175 | tech : INTEGER := 0; |
|
|
176 | 176 | Sample_SZ : INTEGER := 16; |
|
|
177 | 177 | ChanelsCount : INTEGER := 1; |
|
|
178 | 178 | Coef_SZ : INTEGER := 9; |
|
|
179 | 179 | CoefCntPerCel : INTEGER := 3; |
|
|
180 | 180 | Cels_count : INTEGER := 5; |
|
|
181 | 181 | Mem_use : INTEGER := use_RAM |
|
|
182 | 182 | ); |
|
|
183 | 183 | PORT( |
|
|
184 | 184 | reset : IN STD_LOGIC; |
|
|
185 | 185 | clk : IN STD_LOGIC; |
|
|
186 | 186 | sample_clk : IN STD_LOGIC; |
|
|
187 | 187 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
188 | 188 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
189 | 189 | virg_pos : IN INTEGER; |
|
|
190 | 190 | GOtest : OUT STD_LOGIC; |
|
|
191 | 191 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) |
|
|
192 | 192 | ); |
|
|
193 | 193 | END COMPONENT; |
|
|
194 | 194 | |
|
|
195 | 195 | |
|
|
196 | 196 | COMPONENT RAM IS |
|
|
197 | 197 | GENERIC( |
|
|
198 | 198 | Input_SZ_1 : INTEGER := 8 |
|
|
199 | 199 | ); |
|
|
200 | 200 | PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT |
|
|
201 | 201 | STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC; |
|
|
202 | 202 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN |
|
|
203 | 203 | STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC |
|
|
204 | 204 | ) ; |
|
|
205 | 205 | END COMPONENT; |
|
|
206 | 206 | |
|
|
207 | 207 | COMPONENT RAM_CEL |
|
|
208 | 208 | GENERIC ( |
|
|
209 | 209 | Sample_SZ : INTEGER); |
|
|
210 | 210 | PORT ( |
|
|
211 | 211 | WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
|
212 | 212 | RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); |
|
|
213 | 213 | WEN, REN : IN STD_LOGIC; |
|
|
214 | 214 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
|
215 | 215 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
|
216 | 216 | RWCLK, RESET : IN STD_LOGIC); |
|
|
217 | 217 | END COMPONENT; |
|
|
218 | 218 | |
|
|
219 | COMPONENT RAM_CEL_N | |
|
|
220 | GENERIC ( | |
|
|
221 | size : INTEGER); | |
|
|
222 | PORT ( | |
|
|
223 | WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
|
|
224 | RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
|
|
225 | WEN, REN : IN STD_LOGIC; | |
|
|
226 | WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
227 | RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
228 | RWCLK, RESET : IN STD_LOGIC); | |
|
|
229 | END COMPONENT; | |
|
|
230 | ||
|
|
219 | 231 | COMPONENT IIR_CEL_FILTER IS |
|
|
220 | 232 | GENERIC( |
|
|
221 | 233 | tech : INTEGER := 0; |
|
|
222 | 234 | Sample_SZ : INTEGER := 16; |
|
|
223 | 235 | ChanelsCount : INTEGER := 1; |
|
|
224 | 236 | Coef_SZ : INTEGER := 9; |
|
|
225 | 237 | CoefCntPerCel : INTEGER := 3; |
|
|
226 | 238 | Cels_count : INTEGER := 5; |
|
|
227 | 239 | Mem_use : INTEGER := use_RAM); |
|
|
228 | 240 | PORT( |
|
|
229 | 241 | reset : IN STD_LOGIC; |
|
|
230 | 242 | clk : IN STD_LOGIC; |
|
|
231 | 243 | sample_clk : IN STD_LOGIC; |
|
|
232 | 244 | regs_in : IN in_IIR_CEL_reg; |
|
|
233 | 245 | regs_out : IN out_IIR_CEL_reg; |
|
|
234 | 246 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
235 | 247 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); |
|
|
236 | 248 | GOtest : OUT STD_LOGIC; |
|
|
237 | 249 | coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) |
|
|
238 | 250 | |
|
|
239 | 251 | ); |
|
|
240 | 252 | END COMPONENT; |
|
|
241 | 253 | |
|
|
242 | 254 | |
|
|
243 | 255 | COMPONENT RAM_CTRLR2 IS |
|
|
244 | 256 | GENERIC( |
|
|
245 | 257 | tech : INTEGER := 0; |
|
|
246 | 258 | Input_SZ_1 : INTEGER := 16; |
|
|
247 | 259 | Mem_use : INTEGER := use_RAM |
|
|
248 | 260 | ); |
|
|
249 | 261 | PORT( |
|
|
250 | 262 | reset : IN STD_LOGIC; |
|
|
251 | 263 | clk : IN STD_LOGIC; |
|
|
252 | 264 | WD_sel : IN STD_LOGIC; |
|
|
253 | 265 | Read : IN STD_LOGIC; |
|
|
254 | 266 | WADDR_sel : IN STD_LOGIC; |
|
|
255 | 267 | count : IN STD_LOGIC; |
|
|
256 | 268 | SVG_ADDR : IN STD_LOGIC; |
|
|
257 | 269 | Write : IN STD_LOGIC; |
|
|
258 | 270 | GO_0 : IN STD_LOGIC; |
|
|
259 | 271 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
|
260 | 272 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
|
|
261 | 273 | ); |
|
|
262 | 274 | END COMPONENT; |
|
|
263 | 275 | |
|
|
264 | 276 | COMPONENT APB_IIR_Filter IS |
|
|
265 | 277 | GENERIC ( |
|
|
266 | 278 | tech : INTEGER := 0; |
|
|
267 | 279 | pindex : INTEGER := 0; |
|
|
268 | 280 | paddr : INTEGER := 0; |
|
|
269 | 281 | pmask : INTEGER := 16#fff#; |
|
|
270 | 282 | pirq : INTEGER := 0; |
|
|
271 | 283 | abits : INTEGER := 8; |
|
|
272 | 284 | Sample_SZ : INTEGER := 16; |
|
|
273 | 285 | ChanelsCount : INTEGER := 1; |
|
|
274 | 286 | Coef_SZ : INTEGER := 9; |
|
|
275 | 287 | CoefCntPerCel : INTEGER := 6; |
|
|
276 | 288 | Cels_count : INTEGER := 5; |
|
|
277 | 289 | virgPos : INTEGER := 3; |
|
|
278 | 290 | Mem_use : INTEGER := use_RAM |
|
|
279 | 291 | ); |
|
|
280 | 292 | PORT ( |
|
|
281 | 293 | rst : IN STD_LOGIC; |
|
|
282 | 294 | clk : IN STD_LOGIC; |
|
|
283 | 295 | apbi : IN apb_slv_in_type; |
|
|
284 | 296 | apbo : OUT apb_slv_out_type; |
|
|
285 | 297 | sample_clk_out : OUT STD_LOGIC; |
|
|
286 | 298 | GOtest : OUT STD_LOGIC; |
|
|
287 | 299 | CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1') |
|
|
288 | 300 | ); |
|
|
289 | 301 | END COMPONENT; |
|
|
290 | 302 | END; |
| @@ -1,63 +1,65 | |||
|
|
1 | 1 | ------------------------------------------------------------------------------ |
|
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Martin Morlot |
|
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
|
21 | 21 | ------------------------------------------------------------------------------- |
|
|
22 | 22 | library IEEE; |
|
|
23 | 23 | use IEEE.numeric_std.all; |
|
|
24 | 24 | use IEEE.std_logic_1164.all; |
|
|
25 | 25 | library lpp; |
|
|
26 | 26 | use lpp.general_purpose.all; |
|
|
27 | 27 | |
|
|
28 | 28 | --! Une ALU : Arithmetic and logical unit, permettant de rοΏ½aliser une ou plusieurs opοΏ½ration |
|
|
29 | 29 | |
|
|
30 | 30 | entity ALU is |
|
|
31 | 31 | generic( |
|
|
32 | 32 | Arith_en : integer := 1; |
|
|
33 | 33 | Logic_en : integer := 1; |
|
|
34 | 34 | Input_SZ_1 : integer := 16; |
|
|
35 |
Input_SZ_2 : integer := 16 |
|
|
|
35 | Input_SZ_2 : integer := 16; | |
|
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
|
37 | ); | |
|
|
36 | 38 | port( |
|
|
37 | 39 | clk : in std_logic; --! Horloge du composant |
|
|
38 | 40 | reset : in std_logic; --! Reset general du composant |
|
|
39 | 41 | ctrl : in std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e |
|
|
40 | 42 | comp : in std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes |
|
|
41 | 43 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande |
|
|
42 | 44 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second OpοΏ½rande |
|
|
43 | 45 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! RοΏ½sultat de l'opοΏ½ration |
|
|
44 | 46 | ); |
|
|
45 | 47 | end ALU; |
|
|
46 | 48 | |
|
|
47 | 49 | --! @details SοΏ½lection grace a l'entrοΏ½e "ctrl" : |
|
|
48 | 50 | --! Pause : IDLE = 000 |
|
|
49 | 51 | --! Multiplieur/Accumulateur : MAC = 001 |
|
|
50 | 52 | --! Multiplication : MULT = 010 |
|
|
51 | 53 | --! Addition : ADD = 011 |
|
|
52 | 54 | --! Reset du MAC : CLRMAC = 100 |
|
|
53 | 55 | architecture ar_ALU of ALU is |
|
|
54 | 56 | |
|
|
55 | 57 | begin |
|
|
56 | 58 | |
|
|
57 | 59 | arith : if Arith_en = 1 generate |
|
|
58 | 60 | MACinst : MAC |
|
|
59 | generic map(Input_SZ_1,Input_SZ_2) | |
|
|
61 | generic map(Input_SZ_1,Input_SZ_2,COMP_EN) | |
|
|
60 | 62 | port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); |
|
|
61 | 63 | end generate; |
|
|
62 | 64 | |
|
|
63 | end architecture; No newline at end of file | |
|
|
65 | end architecture; | |
| @@ -1,294 +1,301 | |||
|
|
1 | 1 | ------------------------------------------------------------------------------ |
|
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Alexis Jeandet |
|
|
20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
|
21 | 21 | ---------------------------------------------------------------------------- |
|
|
22 | 22 | LIBRARY IEEE; |
|
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
|
25 | 25 | LIBRARY lpp; |
|
|
26 | 26 | USE lpp.general_purpose.ALL; |
|
|
27 | 27 | --TODO |
|
|
28 | 28 | --terminer le testbensh puis changer le resize dans les instanciations |
|
|
29 | 29 | --par un resize sur un vecteur en combi |
|
|
30 | 30 | |
|
|
31 | 31 | |
|
|
32 | 32 | ENTITY MAC IS |
|
|
33 | 33 | GENERIC( |
|
|
34 | 34 | Input_SZ_A : INTEGER := 8; |
|
|
35 | Input_SZ_B : INTEGER := 8 | |
|
|
35 | Input_SZ_B : INTEGER := 8; | |
|
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
|
36 | 37 | |
|
|
37 | 38 | ); |
|
|
38 | 39 | PORT( |
|
|
39 | 40 | clk : IN STD_LOGIC; |
|
|
40 | 41 | reset : IN STD_LOGIC; |
|
|
41 | 42 | clr_MAC : IN STD_LOGIC; |
|
|
42 | 43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
43 | 44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
44 | 45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
45 | 46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
46 | 47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
|
47 | 48 | ); |
|
|
48 | 49 | END MAC; |
|
|
49 | 50 | |
|
|
50 | 51 | |
|
|
51 | 52 | |
|
|
52 | 53 | |
|
|
53 | 54 | ARCHITECTURE ar_MAC OF MAC IS |
|
|
54 | 55 | |
|
|
55 | signal add,mult : std_logic; | |
|
|
56 |
|
|
|
|
56 | SIGNAL add, mult : STD_LOGIC; | |
|
|
57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
57 | 58 | |
|
|
58 |
|
|
|
|
59 |
|
|
|
|
60 |
|
|
|
|
59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
61 | 62 | |
|
|
62 | signal MACMUXsel : std_logic; | |
|
|
63 |
|
|
|
|
64 |
|
|
|
|
63 | SIGNAL MACMUXsel : STD_LOGIC; | |
|
|
64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
65 | 66 | |
|
|
66 | signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0); | |
|
|
67 | signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0); | |
|
|
67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
|
68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
|
68 | 69 | |
|
|
69 | signal MACMUX2sel : std_logic; | |
|
|
70 | SIGNAL MACMUX2sel : STD_LOGIC; | |
|
|
70 | 71 | |
|
|
71 | signal add_D : std_logic; | |
|
|
72 | signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0); | |
|
|
73 | signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0); | |
|
|
74 |
|
|
|
|
75 | signal MACMUXsel_D : std_logic; | |
|
|
76 | signal MACMUX2sel_D : std_logic; | |
|
|
77 | signal MACMUX2sel_D_D : std_logic; | |
|
|
78 | signal clr_MAC_D : std_logic; | |
|
|
79 | signal clr_MAC_D_D : std_logic; | |
|
|
80 | signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0); | |
|
|
72 | SIGNAL add_D : STD_LOGIC; | |
|
|
73 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
|
74 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
|
75 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
|
76 | SIGNAL MACMUXsel_D : STD_LOGIC; | |
|
|
77 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |
|
|
78 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |
|
|
79 | SIGNAL clr_MAC_D : STD_LOGIC; | |
|
|
80 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |
|
|
81 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
81 | 82 | |
|
|
82 | SIGNAL load_mult_result : STD_LOGIC; | |
|
|
83 | SIGNAL load_mult_result_D : STD_LOGIC; | |
|
|
83 | SIGNAL load_mult_result : STD_LOGIC; | |
|
|
84 | SIGNAL load_mult_result_D : STD_LOGIC; | |
|
|
84 | 85 | |
|
|
85 | 86 | BEGIN |
|
|
86 | 87 | |
|
|
87 | 88 | |
|
|
88 | 89 | |
|
|
89 | 90 | |
|
|
90 | 91 | --============================================================== |
|
|
91 | 92 | --=============M A C C O N T R O L E R========================= |
|
|
92 | 93 | --============================================================== |
|
|
93 | 94 | MAC_CONTROLER1 : MAC_CONTROLER |
|
|
94 | 95 | PORT MAP( |
|
|
95 | 96 | ctrl => MAC_MUL_ADD, |
|
|
96 | 97 | MULT => mult, |
|
|
97 | 98 | ADD => add, |
|
|
98 | 99 | LOAD_ADDER => load_mult_result, |
|
|
99 | 100 | MACMUX_sel => MACMUXsel, |
|
|
100 | 101 | MACMUX2_sel => MACMUX2sel |
|
|
101 | 102 | |
|
|
102 | 103 | ); |
|
|
103 | 104 | --============================================================== |
|
|
104 | 105 | |
|
|
105 | 106 | |
|
|
106 | 107 | |
|
|
107 | 108 | |
|
|
108 | 109 | --============================================================== |
|
|
109 | 110 | --=============M U L T I P L I E R============================== |
|
|
110 | 111 | --============================================================== |
|
|
111 | 112 | Multiplieri_nst : Multiplier |
|
|
112 | 113 | GENERIC MAP( |
|
|
113 | 114 | Input_SZ_A => Input_SZ_A, |
|
|
114 | 115 | Input_SZ_B => Input_SZ_B |
|
|
115 | 116 | ) |
|
|
116 | port map( | |
|
|
117 |
clk |
|
|
|
118 |
reset |
|
|
|
119 |
mult |
|
|
|
120 |
OP1 |
|
|
|
121 |
OP2 |
|
|
|
122 |
RES |
|
|
|
123 | ); | |
|
|
117 | PORT MAP( | |
|
|
118 | clk => clk, | |
|
|
119 | reset => reset, | |
|
|
120 | mult => mult, | |
|
|
121 | OP1 => OP1_2C, | |
|
|
122 | OP2 => OP2_2C, | |
|
|
123 | RES => MULTout | |
|
|
124 | ); | |
|
|
124 | 125 | --============================================================== |
|
|
125 | 126 | |
|
|
126 | 127 | PROCESS (clk, reset) |
|
|
127 | 128 | BEGIN -- PROCESS |
|
|
128 | 129 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
|
129 | 130 | load_mult_result_D <= '0'; |
|
|
130 |
ELSIF clk' |
|
|
|
131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
131 | 132 | load_mult_result_D <= load_mult_result; |
|
|
132 | 133 | END IF; |
|
|
133 | 134 | END PROCESS; |
|
|
134 | ||
|
|
135 | ||
|
|
135 | 136 | --============================================================== |
|
|
136 | 137 | --======================A D D E R ============================== |
|
|
137 | 138 | --============================================================== |
|
|
138 | 139 | adder_inst : Adder |
|
|
139 | 140 | GENERIC MAP( |
|
|
140 | 141 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
|
141 | 142 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
|
142 | 143 | ) |
|
|
143 | 144 | PORT MAP( |
|
|
144 | 145 | clk => clk, |
|
|
145 | 146 | reset => reset, |
|
|
146 | 147 | clr => clr_MAC_D, |
|
|
147 | 148 | load => load_mult_result_D, |
|
|
148 | 149 | add => add_D, |
|
|
149 | 150 | OP1 => ADDERinA, |
|
|
150 | 151 | OP2 => ADDERinB, |
|
|
151 | 152 | RES => ADDERout |
|
|
152 | 153 | ); |
|
|
153 | 154 | |
|
|
154 | 155 | --============================================================== |
|
|
155 | 156 | --===================TWO COMPLEMENTERS========================== |
|
|
156 | 157 | --============================================================== |
|
|
157 | TWO_COMPLEMENTER1 : TwoComplementer | |
|
|
158 | generic map( | |
|
|
159 | Input_SZ => Input_SZ_A | |
|
|
160 | ) | |
|
|
161 | port map( | |
|
|
162 | clk => clk, | |
|
|
163 |
|
|
|
|
164 | clr => clr_MAC, | |
|
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165 | TwoComp => Comp_2C(0), | |
|
|
166 | OP => OP1, | |
|
|
167 |
|
|
|
|
168 | ); | |
|
|
158 | gen_comp : IF COMP_EN = 0 GENERATE | |
|
|
159 | TWO_COMPLEMENTER1 : TwoComplementer | |
|
|
160 | GENERIC MAP( | |
|
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161 | Input_SZ => Input_SZ_A | |
|
|
162 | ) | |
|
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163 | PORT MAP( | |
|
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164 | clk => clk, | |
|
|
165 | reset => reset, | |
|
|
166 | clr => clr_MAC, | |
|
|
167 | TwoComp => Comp_2C(0), | |
|
|
168 | OP => OP1, | |
|
|
169 | RES => OP1_2C | |
|
|
170 | ); | |
|
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169 | 171 | |
|
|
170 | ||
|
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171 | TWO_COMPLEMENTER2 : TwoComplementer | |
|
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172 | generic map( | |
|
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173 | Input_SZ => Input_SZ_B | |
|
|
174 | ) | |
|
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175 | port map( | |
|
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176 | clk => clk, | |
|
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177 |
|
|
|
|
178 | clr => clr_MAC, | |
|
|
179 | TwoComp => Comp_2C(1), | |
|
|
180 |
|
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|
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181 | RES => OP2_2C | |
|
|
182 | ); | |
|
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172 | TWO_COMPLEMENTER2 : TwoComplementer | |
|
|
173 | GENERIC MAP( | |
|
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174 | Input_SZ => Input_SZ_B | |
|
|
175 | ) | |
|
|
176 | PORT MAP( | |
|
|
177 | clk => clk, | |
|
|
178 | reset => reset, | |
|
|
179 | clr => clr_MAC, | |
|
|
180 | TwoComp => Comp_2C(1), | |
|
|
181 | OP => OP2, | |
|
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182 | RES => OP2_2C | |
|
|
183 | ); | |
|
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184 | END GENERATE gen_comp; | |
|
|
185 | ||
|
|
186 | no_gen_comp : IF COMP_EN = 1 GENERATE | |
|
|
187 | OP2_2C <= OP2; | |
|
|
188 | OP1_2C <= OP1; | |
|
|
189 | END GENERATE no_gen_comp; | |
|
|
183 | 190 | --============================================================== |
|
|
184 | 191 | |
|
|
185 | 192 | clr_MACREG1 : MAC_REG |
|
|
186 | 193 | GENERIC MAP(size => 1) |
|
|
187 | 194 | PORT MAP( |
|
|
188 | 195 | reset => reset, |
|
|
189 | 196 | clk => clk, |
|
|
190 | 197 | D(0) => clr_MAC, |
|
|
191 | 198 | Q(0) => clr_MAC_D |
|
|
192 | 199 | ); |
|
|
193 | 200 | |
|
|
194 | 201 | addREG : MAC_REG |
|
|
195 | 202 | GENERIC MAP(size => 1) |
|
|
196 | 203 | PORT MAP( |
|
|
197 | 204 | reset => reset, |
|
|
198 | 205 | clk => clk, |
|
|
199 | 206 | D(0) => add, |
|
|
200 | 207 | Q(0) => add_D |
|
|
201 | 208 | ); |
|
|
202 | 209 | |
|
|
203 | OP1REG : MAC_REG | |
|
|
204 |
|
|
|
|
205 | port map( | |
|
|
206 |
reset |
|
|
|
207 |
clk |
|
|
|
208 |
D |
|
|
|
209 |
Q |
|
|
|
210 | ); | |
|
|
210 | OP1REG : MAC_REG | |
|
|
211 | GENERIC MAP(size => Input_SZ_A) | |
|
|
212 | PORT MAP( | |
|
|
213 | reset => reset, | |
|
|
214 | clk => clk, | |
|
|
215 | D => OP1_2C, | |
|
|
216 | Q => OP1_2C_D | |
|
|
217 | ); | |
|
|
211 | 218 | |
|
|
212 | 219 | |
|
|
213 | OP2REG : MAC_REG | |
|
|
214 |
|
|
|
|
215 | port map( | |
|
|
216 |
reset |
|
|
|
217 |
clk |
|
|
|
218 |
D |
|
|
|
219 |
Q |
|
|
|
220 | ); | |
|
|
220 | OP2REG : MAC_REG | |
|
|
221 | GENERIC MAP(size => Input_SZ_B) | |
|
|
222 | PORT MAP( | |
|
|
223 | reset => reset, | |
|
|
224 | clk => clk, | |
|
|
225 | D => OP2_2C, | |
|
|
226 | Q => OP2_2C_D | |
|
|
227 | ); | |
|
|
221 | 228 | |
|
|
222 | 229 | MULToutREG : MAC_REG |
|
|
223 | 230 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) |
|
|
224 | 231 | PORT MAP( |
|
|
225 | 232 | reset => reset, |
|
|
226 | 233 | clk => clk, |
|
|
227 | 234 | D => MULTout, |
|
|
228 | 235 | Q => MULTout_D |
|
|
229 | 236 | ); |
|
|
230 | 237 | |
|
|
231 | 238 | MACMUXselREG : MAC_REG |
|
|
232 | 239 | GENERIC MAP(size => 1) |
|
|
233 | 240 | PORT MAP( |
|
|
234 | 241 | reset => reset, |
|
|
235 | 242 | clk => clk, |
|
|
236 | 243 | D(0) => MACMUXsel, |
|
|
237 | 244 | Q(0) => MACMUXsel_D |
|
|
238 | 245 | ); |
|
|
239 | 246 | |
|
|
240 | 247 | MACMUX2selREG : MAC_REG |
|
|
241 | 248 | GENERIC MAP(size => 1) |
|
|
242 | 249 | PORT MAP( |
|
|
243 | 250 | reset => reset, |
|
|
244 | 251 | clk => clk, |
|
|
245 | 252 | D(0) => MACMUX2sel, |
|
|
246 | 253 | Q(0) => MACMUX2sel_D |
|
|
247 | 254 | ); |
|
|
248 | 255 | |
|
|
249 | 256 | MACMUX2selREG2 : MAC_REG |
|
|
250 | 257 | GENERIC MAP(size => 1) |
|
|
251 | 258 | PORT MAP( |
|
|
252 | 259 | reset => reset, |
|
|
253 | 260 | clk => clk, |
|
|
254 | 261 | D(0) => MACMUX2sel_D, |
|
|
255 | 262 | Q(0) => MACMUX2sel_D_D |
|
|
256 | 263 | ); |
|
|
257 | 264 | |
|
|
258 | 265 | --============================================================== |
|
|
259 | 266 | --======================M A C M U X =========================== |
|
|
260 | 267 | --============================================================== |
|
|
261 | 268 | MACMUX_inst : MAC_MUX |
|
|
262 | 269 | GENERIC MAP( |
|
|
263 | 270 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
|
264 | 271 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
|
265 | 272 | |
|
|
266 | 273 | ) |
|
|
267 | 274 | PORT MAP( |
|
|
268 | 275 | sel => MACMUXsel_D, |
|
|
269 | 276 | INA1 => ADDERout, |
|
|
270 | 277 | INA2 => OP2_2C_D_Resz, |
|
|
271 | 278 | INB1 => MULTout, |
|
|
272 | 279 | INB2 => OP1_2C_D_Resz, |
|
|
273 | 280 | OUTA => ADDERinA, |
|
|
274 | 281 | OUTB => ADDERinB |
|
|
275 | 282 | ); |
|
|
276 | 283 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); |
|
|
277 | 284 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); |
|
|
278 | 285 | --============================================================== |
|
|
279 | 286 | |
|
|
280 | 287 | |
|
|
281 | 288 | --============================================================== |
|
|
282 | 289 | --======================M A C M U X2 ========================== |
|
|
283 | 290 | --============================================================== |
|
|
284 | 291 | MAC_MUX2_inst : MAC_MUX2 |
|
|
285 | 292 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) |
|
|
286 | 293 | PORT MAP( |
|
|
287 | 294 | sel => MACMUX2sel_D_D, |
|
|
288 | 295 | RES2 => MULTout_D, |
|
|
289 | 296 | RES1 => ADDERout, |
|
|
290 | 297 | RES => RES |
|
|
291 | 298 | ); |
|
|
292 | 299 | --============================================================== |
|
|
293 | 300 | |
|
|
294 | 301 | END ar_MAC; |
| @@ -1,270 +1,272 | |||
|
|
1 | 1 | ------------------------------------------------------------------------------ |
|
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Alexis Jeandet |
|
|
20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
|
21 | 21 | ---------------------------------------------------------------------------- |
|
|
22 | 22 | --UPDATE |
|
|
23 | 23 | ------------------------------------------------------------------------------- |
|
|
24 | 24 | -- 14-03-2013 - Jean-christophe Pellion |
|
|
25 | 25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) |
|
|
26 | 26 | ------------------------------------------------------------------------------- |
|
|
27 | 27 | |
|
|
28 | 28 | LIBRARY ieee; |
|
|
29 | 29 | USE ieee.std_logic_1164.ALL; |
|
|
30 | 30 | |
|
|
31 | 31 | |
|
|
32 | 32 | |
|
|
33 | 33 | PACKAGE general_purpose IS |
|
|
34 | 34 | |
|
|
35 | 35 | |
|
|
36 | 36 | |
|
|
37 | 37 | COMPONENT Clk_divider IS |
|
|
38 | 38 | GENERIC(OSC_freqHz : INTEGER := 50000000; |
|
|
39 | 39 | TargetFreq_Hz : INTEGER := 50000); |
|
|
40 | 40 | PORT (clk : IN STD_LOGIC; |
|
|
41 | 41 | reset : IN STD_LOGIC; |
|
|
42 | 42 | clk_divided : OUT STD_LOGIC); |
|
|
43 | 43 | END COMPONENT; |
|
|
44 | 44 | |
|
|
45 | 45 | |
|
|
46 | 46 | COMPONENT Clk_divider2 IS |
|
|
47 | 47 | generic(N : integer := 16); |
|
|
48 | 48 | port( |
|
|
49 | 49 | clk_in : in std_logic; |
|
|
50 | 50 | clk_out : out std_logic); |
|
|
51 | 51 | END COMPONENT; |
|
|
52 | 52 | |
|
|
53 | 53 | COMPONENT Adder IS |
|
|
54 | 54 | GENERIC( |
|
|
55 | 55 | Input_SZ_A : INTEGER := 16; |
|
|
56 | 56 | Input_SZ_B : INTEGER := 16 |
|
|
57 | 57 | |
|
|
58 | 58 | ); |
|
|
59 | 59 | PORT( |
|
|
60 | 60 | clk : IN STD_LOGIC; |
|
|
61 | 61 | reset : IN STD_LOGIC; |
|
|
62 | 62 | clr : IN STD_LOGIC; |
|
|
63 | 63 | load : IN STD_LOGIC; |
|
|
64 | 64 | add : IN STD_LOGIC; |
|
|
65 | 65 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
66 | 66 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
67 | 67 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) |
|
|
68 | 68 | ); |
|
|
69 | 69 | END COMPONENT; |
|
|
70 | 70 | |
|
|
71 | 71 | COMPONENT ADDRcntr IS |
|
|
72 | 72 | PORT( |
|
|
73 | 73 | clk : IN STD_LOGIC; |
|
|
74 | 74 | reset : IN STD_LOGIC; |
|
|
75 | 75 | count : IN STD_LOGIC; |
|
|
76 | 76 | clr : IN STD_LOGIC; |
|
|
77 | 77 | Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
|
|
78 | 78 | ); |
|
|
79 | 79 | END COMPONENT; |
|
|
80 | 80 | |
|
|
81 | 81 | COMPONENT ALU IS |
|
|
82 | 82 | GENERIC( |
|
|
83 | 83 | Arith_en : INTEGER := 1; |
|
|
84 | 84 | Logic_en : INTEGER := 1; |
|
|
85 | 85 | Input_SZ_1 : INTEGER := 16; |
|
|
86 | Input_SZ_2 : INTEGER := 9 | |
|
|
86 | Input_SZ_2 : INTEGER := 9; | |
|
|
87 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
|
87 | 88 | |
|
|
88 | 89 | ); |
|
|
89 | 90 | PORT( |
|
|
90 | 91 | clk : IN STD_LOGIC; |
|
|
91 | 92 | reset : IN STD_LOGIC; |
|
|
92 | 93 | ctrl : IN STD_LOGIC_VECTOR(2 downto 0); |
|
|
93 | 94 | comp : IN STD_LOGIC_VECTOR(1 downto 0); |
|
|
94 | 95 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
|
95 | 96 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); |
|
|
96 | 97 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) |
|
|
97 | 98 | ); |
|
|
98 | 99 | END COMPONENT; |
|
|
99 | 100 | |
|
|
100 | 101 | --------------------------------------------------------- |
|
|
101 | 102 | -------- // SοΏ½lection grace a l'entrοΏ½e "ctrl" \\ -------- |
|
|
102 | 103 | --------------------------------------------------------- |
|
|
103 | 104 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; |
|
|
104 | 105 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; |
|
|
105 | 106 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; |
|
|
106 | 107 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; |
|
|
107 | 108 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; |
|
|
108 | 109 | --------------------------------------------------------- |
|
|
109 | 110 | |
|
|
110 | 111 | COMPONENT MAC IS |
|
|
111 | 112 | GENERIC( |
|
|
112 | 113 | Input_SZ_A : INTEGER := 8; |
|
|
113 | Input_SZ_B : INTEGER := 8 | |
|
|
114 | Input_SZ_B : INTEGER := 8; | |
|
|
115 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
|
114 | 116 | ); |
|
|
115 | 117 | PORT( |
|
|
116 | 118 | clk : IN STD_LOGIC; |
|
|
117 | 119 | reset : IN STD_LOGIC; |
|
|
118 | 120 | clr_MAC : IN STD_LOGIC; |
|
|
119 | 121 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
120 | 122 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
121 | 123 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
122 | 124 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
123 | 125 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
|
124 | 126 | ); |
|
|
125 | 127 | END COMPONENT; |
|
|
126 | 128 | |
|
|
127 | 129 | COMPONENT TwoComplementer is |
|
|
128 | 130 | generic( |
|
|
129 | 131 | Input_SZ : integer := 16); |
|
|
130 | 132 | port( |
|
|
131 | 133 | clk : in std_logic; --! Horloge du composant |
|
|
132 | 134 | reset : in std_logic; --! Reset general du composant |
|
|
133 | 135 | clr : in std_logic; --! Un reset spοΏ½cifique au programme |
|
|
134 | 136 | TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment |
|
|
135 | 137 | OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e |
|
|
136 | 138 | RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non |
|
|
137 | 139 | ); |
|
|
138 | 140 | end COMPONENT; |
|
|
139 | 141 | |
|
|
140 | 142 | COMPONENT MAC_CONTROLER IS |
|
|
141 | 143 | PORT( |
|
|
142 | 144 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
143 | 145 | MULT : OUT STD_LOGIC; |
|
|
144 | 146 | ADD : OUT STD_LOGIC; |
|
|
145 | 147 | LOAD_ADDER : out std_logic; |
|
|
146 | 148 | MACMUX_sel : OUT STD_LOGIC; |
|
|
147 | 149 | MACMUX2_sel : OUT STD_LOGIC |
|
|
148 | 150 | ); |
|
|
149 | 151 | END COMPONENT; |
|
|
150 | 152 | |
|
|
151 | 153 | COMPONENT MAC_MUX IS |
|
|
152 | 154 | GENERIC( |
|
|
153 | 155 | Input_SZ_A : INTEGER := 16; |
|
|
154 | 156 | Input_SZ_B : INTEGER := 16 |
|
|
155 | 157 | |
|
|
156 | 158 | ); |
|
|
157 | 159 | PORT( |
|
|
158 | 160 | sel : IN STD_LOGIC; |
|
|
159 | 161 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
160 | 162 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
161 | 163 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
162 | 164 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
163 | 165 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
164 | 166 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) |
|
|
165 | 167 | ); |
|
|
166 | 168 | END COMPONENT; |
|
|
167 | 169 | |
|
|
168 | 170 | |
|
|
169 | 171 | COMPONENT MAC_MUX2 IS |
|
|
170 | 172 | GENERIC(Input_SZ : INTEGER := 16); |
|
|
171 | 173 | PORT( |
|
|
172 | 174 | sel : IN STD_LOGIC; |
|
|
173 | 175 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
|
174 | 176 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
|
175 | 177 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
|
176 | 178 | ); |
|
|
177 | 179 | END COMPONENT; |
|
|
178 | 180 | |
|
|
179 | 181 | |
|
|
180 | 182 | COMPONENT MAC_REG IS |
|
|
181 | 183 | GENERIC(size : INTEGER := 16); |
|
|
182 | 184 | PORT( |
|
|
183 | 185 | reset : IN STD_LOGIC; |
|
|
184 | 186 | clk : IN STD_LOGIC; |
|
|
185 | 187 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
|
186 | 188 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
|
187 | 189 | ); |
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188 | 190 | END COMPONENT; |
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189 | 191 | |
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190 | 192 | |
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191 | 193 | COMPONENT MUX2 IS |
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192 | 194 | GENERIC(Input_SZ : INTEGER := 16); |
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193 | 195 | PORT( |
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194 | 196 | sel : IN STD_LOGIC; |
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195 | 197 | IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
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196 | 198 | IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
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197 | 199 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
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198 | 200 | ); |
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199 | 201 | END COMPONENT; |
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200 | 202 | |
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201 | 203 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
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202 | 204 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; |
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203 | 205 | |
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204 | 206 | COMPONENT MUXN |
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205 | 207 | GENERIC ( |
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206 | 208 | Input_SZ : INTEGER; |
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207 | 209 | NbStage : INTEGER); |
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208 | 210 | PORT ( |
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209 | 211 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); |
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210 | 212 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); |
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211 | 213 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
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212 | 214 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); |
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213 | 215 | END COMPONENT; |
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214 | 216 | |
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215 | 217 | |
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216 | 218 | |
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217 | 219 | COMPONENT Multiplier IS |
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218 | 220 | GENERIC( |
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219 | 221 | Input_SZ_A : INTEGER := 16; |
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220 | 222 | Input_SZ_B : INTEGER := 16 |
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221 | 223 | |
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222 | 224 | ); |
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223 | 225 | PORT( |
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224 | 226 | clk : IN STD_LOGIC; |
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225 | 227 | reset : IN STD_LOGIC; |
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226 | 228 | mult : IN STD_LOGIC; |
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227 | 229 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
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228 | 230 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
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229 | 231 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
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230 | 232 | ); |
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231 | 233 | END COMPONENT; |
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232 | 234 | |
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233 | 235 | COMPONENT REG IS |
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234 | 236 | GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0); |
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235 | 237 | PORT( |
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236 | 238 | reset : IN STD_LOGIC; |
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237 | 239 | clk : IN STD_LOGIC; |
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238 | 240 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
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239 | 241 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
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240 | 242 | ); |
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241 | 243 | END COMPONENT; |
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242 | 244 | |
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243 | 245 | |
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244 | 246 | |
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245 | 247 | COMPONENT RShifter IS |
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246 | 248 | GENERIC( |
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247 | 249 | Input_SZ : INTEGER := 16; |
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248 | 250 | shift_SZ : INTEGER := 4 |
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249 | 251 | ); |
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250 | 252 | PORT( |
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251 | 253 | clk : IN STD_LOGIC; |
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252 | 254 | reset : IN STD_LOGIC; |
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253 | 255 | shift : IN STD_LOGIC; |
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254 | 256 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
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255 | 257 | cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0); |
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256 | 258 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
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257 | 259 | ); |
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258 | 260 | END COMPONENT; |
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259 | 261 | |
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260 | 262 | COMPONENT SYNC_FF |
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261 | 263 | GENERIC ( |
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262 | 264 | NB_FF_OF_SYNC : INTEGER); |
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263 | 265 | PORT ( |
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264 | 266 | clk : IN STD_LOGIC; |
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265 | 267 | rstn : IN STD_LOGIC; |
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266 | 268 | A : IN STD_LOGIC; |
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267 | 269 | A_sync : OUT STD_LOGIC); |
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268 | 270 | END COMPONENT; |
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269 | 271 | |
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270 | 272 | END; |
| This diff has been collapsed as it changes many lines, (606 lines changed) Show them Hide them | |||
| @@ -1,303 +1,303 | |||
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | LIBRARY lpp; | |
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4 | USE lpp.lpp_ad_conv.ALL; | |
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5 | USE lpp.iir_filter.ALL; | |
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6 | USE lpp.FILTERcfg.ALL; | |
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7 | USE lpp.lpp_memory.ALL; | |
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8 | USE lpp.lpp_top_lfr_pkg.ALL; | |
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9 | LIBRARY techmap; | |
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10 | USE techmap.gencomp.ALL; | |
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11 | ||
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12 | ENTITY lpp_top_acq IS | |
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13 | GENERIC( | |
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14 | tech : INTEGER := 0 | |
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15 | ); | |
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16 | PORT ( | |
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17 | -- ADS7886 | |
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18 | cnv_run : IN STD_LOGIC; | |
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19 | cnv : OUT STD_LOGIC; | |
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20 | sck : OUT STD_LOGIC; | |
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21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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22 | -- | |
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23 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
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24 | cnv_rstn : IN STD_LOGIC; | |
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25 | -- | |
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26 | clk : IN STD_LOGIC; -- 25 MHz | |
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27 | rstn : IN STD_LOGIC; | |
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28 | -- | |
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29 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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31 | -- | |
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32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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34 | -- | |
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35 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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36 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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37 | -- | |
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38 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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39 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
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40 | ); | |
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41 | END lpp_top_acq; | |
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42 | ||
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43 | ARCHITECTURE tb OF lpp_top_acq IS | |
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44 | ||
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45 | COMPONENT Downsampling | |
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46 | GENERIC ( | |
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47 | ChanelCount : INTEGER; | |
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48 | SampleSize : INTEGER; | |
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49 | DivideParam : INTEGER); | |
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50 | PORT ( | |
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51 | clk : IN STD_LOGIC; | |
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52 | rstn : IN STD_LOGIC; | |
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53 | sample_in_val : IN STD_LOGIC; | |
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54 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
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55 | sample_out_val : OUT STD_LOGIC; | |
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56 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
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57 | END COMPONENT; | |
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58 | ||
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59 | ----------------------------------------------------------------------------- | |
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60 | CONSTANT ChanelCount : INTEGER := 8; | |
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61 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
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62 | CONSTANT ncycle_cnv : INTEGER := 500; | |
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63 | ||
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64 | ----------------------------------------------------------------------------- | |
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65 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
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66 | SIGNAL sample_val : STD_LOGIC; | |
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67 | SIGNAL sample_val_delay : STD_LOGIC; | |
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68 | ----------------------------------------------------------------------------- | |
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69 | CONSTANT Coef_SZ : INTEGER := 9; | |
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70 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
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71 | CONSTANT CoefPerCel : INTEGER := 5; | |
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72 | CONSTANT Cels_count : INTEGER := 5; | |
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73 | ||
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74 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
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75 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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76 | -- | |
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77 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
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78 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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79 | -- | |
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80 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |
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81 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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82 | ----------------------------------------------------------------------------- | |
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83 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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84 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |
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85 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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86 | -- | |
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87 | SIGNAL sample_f0_val : STD_LOGIC; | |
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88 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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89 | ----------------------------------------------------------------------------- | |
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90 | SIGNAL sample_f1_val : STD_LOGIC; | |
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91 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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92 | -- | |
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93 | SIGNAL sample_f2_val : STD_LOGIC; | |
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94 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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95 | -- | |
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96 | SIGNAL sample_f3_val : STD_LOGIC; | |
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97 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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98 | ||
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99 | BEGIN | |
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100 | ||
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101 | -- component instantiation | |
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102 | ----------------------------------------------------------------------------- | |
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103 |
DIGITAL_acquisition : AD |
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104 | GENERIC MAP ( | |
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105 | ChanelCount => ChanelCount, | |
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106 | ncycle_cnv_high => ncycle_cnv_high, | |
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107 | ncycle_cnv => ncycle_cnv) | |
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108 | PORT MAP ( | |
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109 | cnv_clk => cnv_clk, -- | |
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110 | cnv_rstn => cnv_rstn, -- | |
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111 | cnv_run => cnv_run, -- | |
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112 | cnv => cnv, -- | |
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113 | clk => clk, -- | |
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114 | rstn => rstn, -- | |
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115 | sck => sck, -- | |
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116 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
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117 | sample => sample, | |
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118 | sample_val => sample_val); | |
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119 | ||
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120 | ----------------------------------------------------------------------------- | |
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121 | ||
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122 | PROCESS (clk, rstn) | |
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123 | BEGIN -- PROCESS | |
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124 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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125 | sample_val_delay <= '0'; | |
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126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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127 | sample_val_delay <= sample_val; | |
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128 | END IF; | |
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129 | END PROCESS; | |
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130 | ||
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131 | ----------------------------------------------------------------------------- | |
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132 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
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133 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
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134 | sample_filter_in(i, j) <= sample(i)(j); | |
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135 | END GENERATE; | |
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136 | ||
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137 | sample_filter_in(i, 16) <= sample(i)(15); | |
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138 | sample_filter_in(i, 17) <= sample(i)(15); | |
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139 | END GENERATE; | |
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140 | ||
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141 | coefs_v2 <= CoefsInitValCst_v2; | |
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142 | ||
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143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
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144 | GENERIC MAP ( | |
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145 | tech => 0, | |
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146 |
Mem_use => use_ |
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147 | Sample_SZ => 18, | |
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148 | Coef_SZ => Coef_SZ, | |
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149 | Coef_Nb => 25, -- TODO | |
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150 | Coef_sel_SZ => 5, -- TODO | |
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151 | Cels_count => Cels_count, | |
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152 | ChanelsCount => ChanelCount) | |
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153 | PORT MAP ( | |
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154 | rstn => rstn, | |
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155 | clk => clk, | |
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156 | virg_pos => 7, | |
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157 | coefs => coefs_v2, | |
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158 | sample_in_val => sample_val_delay, | |
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159 | sample_in => sample_filter_in, | |
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160 | sample_out_val => sample_filter_v2_out_val, | |
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161 | sample_out => sample_filter_v2_out); | |
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162 | ||
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163 | ----------------------------------------------------------------------------- | |
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164 | PROCESS (clk, rstn) | |
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165 | BEGIN -- PROCESS | |
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166 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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167 | sample_filter_v2_out_r_val <= '0'; | |
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168 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
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169 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |
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170 | sample_filter_v2_out_r(I, J) <= '0'; | |
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171 | END LOOP rst_all_bits; | |
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172 | END LOOP rst_all_chanel; | |
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173 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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174 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |
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175 | IF sample_filter_v2_out_val = '1' THEN | |
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176 | sample_filter_v2_out_r <= sample_filter_v2_out; | |
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177 | END IF; | |
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178 | END IF; | |
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179 | END PROCESS; | |
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180 | ||
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181 | ----------------------------------------------------------------------------- | |
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182 | -- F0 -- @24.576 kHz | |
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183 | ----------------------------------------------------------------------------- | |
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184 | Downsampling_f0 : Downsampling | |
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185 | GENERIC MAP ( | |
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186 | ChanelCount => ChanelCount, | |
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187 | SampleSize => 18, | |
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188 | DivideParam => 4) | |
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189 | PORT MAP ( | |
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190 | clk => clk, | |
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191 | rstn => rstn, | |
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192 | sample_in_val => sample_filter_v2_out_val , | |
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193 | sample_in => sample_filter_v2_out, | |
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194 | sample_out_val => sample_f0_val, | |
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195 | sample_out => sample_f0); | |
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196 | ||
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197 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
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198 | sample_f0_wdata(I) <= sample_f0(0, I); | |
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199 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |
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200 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |
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201 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | |
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202 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |
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203 | END GENERATE all_bit_sample_f0; | |
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204 | ||
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205 | sample_f0_wen <= NOT(sample_f0_val) & | |
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206 | NOT(sample_f0_val) & | |
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207 | NOT(sample_f0_val) & | |
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208 | NOT(sample_f0_val) & | |
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209 | NOT(sample_f0_val); | |
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210 | ||
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211 | ----------------------------------------------------------------------------- | |
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212 | -- F1 -- @4096 Hz | |
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213 | ----------------------------------------------------------------------------- | |
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214 | Downsampling_f1 : Downsampling | |
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215 | GENERIC MAP ( | |
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216 | ChanelCount => ChanelCount, | |
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217 | SampleSize => 18, | |
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218 | DivideParam => 6) | |
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219 | PORT MAP ( | |
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220 | clk => clk, | |
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221 | rstn => rstn, | |
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222 | sample_in_val => sample_f0_val , | |
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223 | sample_in => sample_f0, | |
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224 | sample_out_val => sample_f1_val, | |
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225 | sample_out => sample_f1); | |
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226 | ||
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227 | sample_f1_wen <= NOT(sample_f1_val) & | |
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228 | NOT(sample_f1_val) & | |
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229 | NOT(sample_f1_val) & | |
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230 | NOT(sample_f1_val) & | |
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231 | NOT(sample_f1_val); | |
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232 | ||
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233 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
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234 | sample_f1_wdata(I) <= sample_f1(0, I); | |
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235 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |
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236 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |
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237 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |
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238 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | |
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239 | END GENERATE all_bit_sample_f1; | |
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240 | ||
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241 | ----------------------------------------------------------------------------- | |
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242 | -- F2 -- @16 Hz | |
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243 | ----------------------------------------------------------------------------- | |
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244 | Downsampling_f2 : Downsampling | |
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245 | GENERIC MAP ( | |
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246 | ChanelCount => ChanelCount, | |
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247 | SampleSize => 18, | |
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248 | DivideParam => 256) | |
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249 | PORT MAP ( | |
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250 | clk => clk, | |
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251 | rstn => rstn, | |
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252 | sample_in_val => sample_f1_val , | |
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253 | sample_in => sample_f1, | |
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254 | sample_out_val => sample_f2_val, | |
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255 | sample_out => sample_f2); | |
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256 | ||
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257 | sample_f2_wen <= NOT(sample_f2_val) & | |
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258 | NOT(sample_f2_val) & | |
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259 | NOT(sample_f2_val) & | |
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260 | NOT(sample_f2_val) & | |
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261 | NOT(sample_f2_val); | |
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262 | ||
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263 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
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264 | sample_f2_wdata(I) <= sample_f2(0, I); | |
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265 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |
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266 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |
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267 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |
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268 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |
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269 | END GENERATE all_bit_sample_f2; | |
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270 | ||
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271 | ----------------------------------------------------------------------------- | |
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272 | -- F3 -- @256 Hz | |
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273 | ----------------------------------------------------------------------------- | |
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274 | Downsampling_f3 : Downsampling | |
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275 | GENERIC MAP ( | |
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276 | ChanelCount => ChanelCount, | |
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277 | SampleSize => 18, | |
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278 | DivideParam => 96) | |
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279 | PORT MAP ( | |
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280 | clk => clk, | |
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281 | rstn => rstn, | |
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282 | sample_in_val => sample_f0_val , | |
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283 | sample_in => sample_f0, | |
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284 | sample_out_val => sample_f3_val, | |
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285 | sample_out => sample_f3); | |
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286 | ||
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287 | sample_f3_wen <= (NOT sample_f3_val) & | |
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288 | (NOT sample_f3_val) & | |
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289 | (NOT sample_f3_val) & | |
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290 | (NOT sample_f3_val) & | |
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291 | (NOT sample_f3_val); | |
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292 | ||
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293 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
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294 | sample_f3_wdata(I) <= sample_f3(0, I); | |
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295 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |
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296 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |
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297 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |
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298 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |
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299 | END GENERATE all_bit_sample_f3; | |
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300 | ||
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301 | ||
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302 | ||
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303 | END tb; | |
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | LIBRARY lpp; | |
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4 | USE lpp.lpp_ad_conv.ALL; | |
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5 | USE lpp.iir_filter.ALL; | |
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6 | USE lpp.FILTERcfg.ALL; | |
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7 | USE lpp.lpp_memory.ALL; | |
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8 | USE lpp.lpp_top_lfr_pkg.ALL; | |
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9 | LIBRARY techmap; | |
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10 | USE techmap.gencomp.ALL; | |
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11 | ||
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12 | ENTITY lpp_top_acq IS | |
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13 | GENERIC( | |
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14 | tech : INTEGER := 0 | |
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15 | ); | |
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16 | PORT ( | |
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17 | -- ADS7886 | |
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18 | cnv_run : IN STD_LOGIC; | |
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19 | cnv : OUT STD_LOGIC; | |
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20 | sck : OUT STD_LOGIC; | |
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21 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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22 | -- | |
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23 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
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24 | cnv_rstn : IN STD_LOGIC; | |
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25 | -- | |
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26 | clk : IN STD_LOGIC; -- 25 MHz | |
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27 | rstn : IN STD_LOGIC; | |
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28 | -- | |
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29 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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31 | -- | |
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32 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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33 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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34 | -- | |
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35 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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36 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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37 | -- | |
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38 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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39 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
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40 | ); | |
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41 | END lpp_top_acq; | |
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42 | ||
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43 | ARCHITECTURE tb OF lpp_top_acq IS | |
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44 | ||
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45 | COMPONENT Downsampling | |
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46 | GENERIC ( | |
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47 | ChanelCount : INTEGER; | |
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48 | SampleSize : INTEGER; | |
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49 | DivideParam : INTEGER); | |
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50 | PORT ( | |
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51 | clk : IN STD_LOGIC; | |
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52 | rstn : IN STD_LOGIC; | |
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53 | sample_in_val : IN STD_LOGIC; | |
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54 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
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55 | sample_out_val : OUT STD_LOGIC; | |
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56 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
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57 | END COMPONENT; | |
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58 | ||
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59 | ----------------------------------------------------------------------------- | |
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60 | CONSTANT ChanelCount : INTEGER := 8; | |
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61 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
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62 | CONSTANT ncycle_cnv : INTEGER := 500; | |
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63 | ||
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64 | ----------------------------------------------------------------------------- | |
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65 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
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66 | SIGNAL sample_val : STD_LOGIC; | |
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67 | SIGNAL sample_val_delay : STD_LOGIC; | |
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68 | ----------------------------------------------------------------------------- | |
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69 | CONSTANT Coef_SZ : INTEGER := 9; | |
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70 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
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71 | CONSTANT CoefPerCel : INTEGER := 5; | |
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72 | CONSTANT Cels_count : INTEGER := 5; | |
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73 | ||
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74 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
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75 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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76 | -- | |
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77 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
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78 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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79 | -- | |
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80 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |
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81 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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82 | ----------------------------------------------------------------------------- | |
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83 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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84 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |
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85 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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86 | -- | |
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87 | SIGNAL sample_f0_val : STD_LOGIC; | |
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88 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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89 | ----------------------------------------------------------------------------- | |
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90 | SIGNAL sample_f1_val : STD_LOGIC; | |
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91 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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92 | -- | |
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93 | SIGNAL sample_f2_val : STD_LOGIC; | |
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94 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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95 | -- | |
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96 | SIGNAL sample_f3_val : STD_LOGIC; | |
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97 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
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98 | ||
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99 | BEGIN | |
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100 | ||
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101 | -- component instantiation | |
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102 | ----------------------------------------------------------------------------- | |
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103 | DIGITAL_acquisition : AD7688_drvr | |
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104 | GENERIC MAP ( | |
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105 | ChanelCount => ChanelCount, | |
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106 | ncycle_cnv_high => ncycle_cnv_high, | |
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107 | ncycle_cnv => ncycle_cnv) | |
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108 | PORT MAP ( | |
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109 | cnv_clk => cnv_clk, -- | |
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110 | cnv_rstn => cnv_rstn, -- | |
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111 | cnv_run => cnv_run, -- | |
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112 | cnv => cnv, -- | |
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113 | clk => clk, -- | |
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114 | rstn => rstn, -- | |
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115 | sck => sck, -- | |
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116 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
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117 | sample => sample, | |
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118 | sample_val => sample_val); | |
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119 | ||
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120 | ----------------------------------------------------------------------------- | |
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121 | ||
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122 | PROCESS (clk, rstn) | |
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123 | BEGIN -- PROCESS | |
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124 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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125 | sample_val_delay <= '0'; | |
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126 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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127 | sample_val_delay <= sample_val; | |
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128 | END IF; | |
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129 | END PROCESS; | |
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130 | ||
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131 | ----------------------------------------------------------------------------- | |
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132 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
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133 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
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134 | sample_filter_in(i, j) <= sample(i)(j); | |
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135 | END GENERATE; | |
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136 | ||
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137 | sample_filter_in(i, 16) <= sample(i)(15); | |
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138 | sample_filter_in(i, 17) <= sample(i)(15); | |
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139 | END GENERATE; | |
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140 | ||
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141 | coefs_v2 <= CoefsInitValCst_v2; | |
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142 | ||
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143 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
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144 | GENERIC MAP ( | |
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145 | tech => 0, | |
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146 | Mem_use => use_CEL, | |
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147 | Sample_SZ => 18, | |
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148 | Coef_SZ => Coef_SZ, | |
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149 | Coef_Nb => 25, -- TODO | |
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150 | Coef_sel_SZ => 5, -- TODO | |
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151 | Cels_count => Cels_count, | |
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152 | ChanelsCount => ChanelCount) | |
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153 | PORT MAP ( | |
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154 | rstn => rstn, | |
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155 | clk => clk, | |
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156 | virg_pos => 7, | |
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157 | coefs => coefs_v2, | |
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158 | sample_in_val => sample_val_delay, | |
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159 | sample_in => sample_filter_in, | |
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160 | sample_out_val => sample_filter_v2_out_val, | |
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161 | sample_out => sample_filter_v2_out); | |
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162 | ||
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163 | ----------------------------------------------------------------------------- | |
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164 | PROCESS (clk, rstn) | |
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165 | BEGIN -- PROCESS | |
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166 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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167 | sample_filter_v2_out_r_val <= '0'; | |
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168 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
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169 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |
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170 | sample_filter_v2_out_r(I, J) <= '0'; | |
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171 | END LOOP rst_all_bits; | |
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172 | END LOOP rst_all_chanel; | |
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173 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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174 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |
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175 | IF sample_filter_v2_out_val = '1' THEN | |
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176 | sample_filter_v2_out_r <= sample_filter_v2_out; | |
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177 | END IF; | |
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178 | END IF; | |
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179 | END PROCESS; | |
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180 | ||
|
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181 | ----------------------------------------------------------------------------- | |
|
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182 | -- F0 -- @24.576 kHz | |
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183 | ----------------------------------------------------------------------------- | |
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184 | Downsampling_f0 : Downsampling | |
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185 | GENERIC MAP ( | |
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186 | ChanelCount => ChanelCount, | |
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187 | SampleSize => 18, | |
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188 | DivideParam => 4) | |
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189 | PORT MAP ( | |
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190 | clk => clk, | |
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191 | rstn => rstn, | |
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192 | sample_in_val => sample_filter_v2_out_val , | |
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193 | sample_in => sample_filter_v2_out, | |
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194 | sample_out_val => sample_f0_val, | |
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195 | sample_out => sample_f0); | |
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196 | ||
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197 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
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198 | sample_f0_wdata(I) <= sample_f0(0, I); | |
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199 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |
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200 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |
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201 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | |
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202 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |
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203 | END GENERATE all_bit_sample_f0; | |
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204 | ||
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205 | sample_f0_wen <= NOT(sample_f0_val) & | |
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206 | NOT(sample_f0_val) & | |
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207 | NOT(sample_f0_val) & | |
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208 | NOT(sample_f0_val) & | |
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209 | NOT(sample_f0_val); | |
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210 | ||
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211 | ----------------------------------------------------------------------------- | |
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212 | -- F1 -- @4096 Hz | |
|
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213 | ----------------------------------------------------------------------------- | |
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214 | Downsampling_f1 : Downsampling | |
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215 | GENERIC MAP ( | |
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216 | ChanelCount => ChanelCount, | |
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217 | SampleSize => 18, | |
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218 | DivideParam => 6) | |
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219 | PORT MAP ( | |
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220 | clk => clk, | |
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221 | rstn => rstn, | |
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222 | sample_in_val => sample_f0_val , | |
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223 | sample_in => sample_f0, | |
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224 | sample_out_val => sample_f1_val, | |
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225 | sample_out => sample_f1); | |
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226 | ||
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227 | sample_f1_wen <= NOT(sample_f1_val) & | |
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228 | NOT(sample_f1_val) & | |
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229 | NOT(sample_f1_val) & | |
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230 | NOT(sample_f1_val) & | |
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231 | NOT(sample_f1_val); | |
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232 | ||
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233 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
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234 | sample_f1_wdata(I) <= sample_f1(0, I); | |
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235 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |
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236 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |
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237 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |
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238 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | |
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239 | END GENERATE all_bit_sample_f1; | |
|
|
240 | ||
|
|
241 | ----------------------------------------------------------------------------- | |
|
|
242 | -- F2 -- @16 Hz | |
|
|
243 | ----------------------------------------------------------------------------- | |
|
|
244 | Downsampling_f2 : Downsampling | |
|
|
245 | GENERIC MAP ( | |
|
|
246 | ChanelCount => ChanelCount, | |
|
|
247 | SampleSize => 18, | |
|
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248 | DivideParam => 256) | |
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249 | PORT MAP ( | |
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250 | clk => clk, | |
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251 | rstn => rstn, | |
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252 | sample_in_val => sample_f1_val , | |
|
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253 | sample_in => sample_f1, | |
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254 | sample_out_val => sample_f2_val, | |
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255 | sample_out => sample_f2); | |
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256 | ||
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257 | sample_f2_wen <= NOT(sample_f2_val) & | |
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258 | NOT(sample_f2_val) & | |
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259 | NOT(sample_f2_val) & | |
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260 | NOT(sample_f2_val) & | |
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261 | NOT(sample_f2_val); | |
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262 | ||
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263 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
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264 | sample_f2_wdata(I) <= sample_f2(0, I); | |
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265 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |
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266 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |
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267 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |
|
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268 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |
|
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269 | END GENERATE all_bit_sample_f2; | |
|
|
270 | ||
|
|
271 | ----------------------------------------------------------------------------- | |
|
|
272 | -- F3 -- @256 Hz | |
|
|
273 | ----------------------------------------------------------------------------- | |
|
|
274 | Downsampling_f3 : Downsampling | |
|
|
275 | GENERIC MAP ( | |
|
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276 | ChanelCount => ChanelCount, | |
|
|
277 | SampleSize => 18, | |
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278 | DivideParam => 96) | |
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279 | PORT MAP ( | |
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280 | clk => clk, | |
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281 | rstn => rstn, | |
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282 | sample_in_val => sample_f0_val , | |
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283 | sample_in => sample_f0, | |
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284 | sample_out_val => sample_f3_val, | |
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285 | sample_out => sample_f3); | |
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286 | ||
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287 | sample_f3_wen <= (NOT sample_f3_val) & | |
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288 | (NOT sample_f3_val) & | |
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289 | (NOT sample_f3_val) & | |
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290 | (NOT sample_f3_val) & | |
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291 | (NOT sample_f3_val); | |
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292 | ||
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293 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
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294 | sample_f3_wdata(I) <= sample_f3(0, I); | |
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295 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |
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296 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |
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297 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |
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298 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |
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299 | END GENERATE all_bit_sample_f3; | |
|
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300 | ||
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301 | ||
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|
302 | ||
|
|
303 | END tb; | |
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