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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
39 pindex : INTEGER := 4;
40 paddr : INTEGER := 4;
41 pmask : INTEGER := 16#fff#;
42 pirq : INTEGER := 0);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 -- IN
53 ready_matrix_f0_0 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60
61 -- OUT
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
68
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
76
77 END lpp_top_apbreg;
78
79 ARCHITECTURE beh OF lpp_top_apbreg IS
80
81 CONSTANT REVISION : INTEGER := 1;
82
83 CONSTANT pconfig : apb_config_type := (
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 1 => apb_iobar(paddr, pmask));
86
87 TYPE lpp_dma_regs IS RECORD
88 config_active_interruption_onNewMatrix : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 END RECORD;
101
102 SIGNAL reg : lpp_dma_regs;
103
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105
106 BEGIN -- beh
107
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
114
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
121
122 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 BEGIN -- PROCESS lpp_dma_top
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 reg.config_active_interruption_onNewMatrix <= '0';
127 reg.config_active_interruption_onError <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
133 reg.status_error_bad_component_error <= '0';
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
145
146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
148
149 paddr := "000000";
150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
151 prdata <= (OTHERS => '0');
152 IF apbi.psel(pindex) = '1' THEN
153 -- APB DMA READ --
154 CASE paddr(7 DOWNTO 2) IS
155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
156 prdata(1) <= reg.config_active_interruption_onError;
157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
158 prdata(1) <= reg.status_ready_matrix_f0_1;
159 prdata(2) <= reg.status_ready_matrix_f1;
160 prdata(3) <= reg.status_ready_matrix_f2;
161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
162 prdata(5) <= reg.status_error_bad_component_error;
163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
168 WHEN OTHERS => NULL;
169 END CASE;
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
171 -- APB DMA WRITE --
172 CASE paddr(7 DOWNTO 2) IS
173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
185 WHEN OTHERS => NULL;
186 END CASE;
187 END IF;
188 END IF;
189 END IF;
190 END PROCESS lpp_top_apbreg;
191
192 apbo.pirq <= (OTHERS => '0');
193 apbo.pindex <= pindex;
194 apbo.pconfig <= pconfig;
195 apbo.prdata <= prdata;
196
197
198 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY grlib;
4 USE grlib.amba.ALL;
5 USE grlib.stdlib.ALL;
6 USE grlib.devices.ALL;
7 USE GRLIB.DMA2AHB_Package.ALL;
8 LIBRARY lpp;
9 USE lpp.lpp_ad_conv.ALL;
10 USE lpp.iir_filter.ALL;
11 USE lpp.FILTERcfg.ALL;
12 USE lpp.lpp_memory.ALL;
13 USE lpp.lpp_top_lfr_pkg.ALL;
14 USE lpp.lpp_dma_pkg.ALL;
15 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_fft.ALL;
17 use lpp.lpp_matrix.all;
18 LIBRARY techmap;
19 USE techmap.gencomp.ALL;
20
21 ENTITY lpp_top_lfr IS
22 GENERIC(
23 tech : INTEGER := 0;
24 hindex_SpectralMatrix : INTEGER := 2;
25 pindex : INTEGER := 4;
26 paddr : INTEGER := 4;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 0
29 );
30 PORT (
31 -- ADS7886
32 cnv_run : IN STD_LOGIC;
33 cnv : OUT STD_LOGIC;
34 sck : OUT STD_LOGIC;
35 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
36 --
37 cnv_clk : IN STD_LOGIC; -- 49 MHz
38 cnv_rstn : IN STD_LOGIC;
39 --
40 clk : IN STD_LOGIC; -- 25 MHz
41 rstn : IN STD_LOGIC;
42 --
43 apbi : IN apb_slv_in_type;
44 apbo : OUT apb_slv_out_type;
45
46 -- AMBA AHB Master Interface
47 AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
48 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
49 );
50 END lpp_top_lfr;
51
52 ARCHITECTURE tb OF lpp_top_lfr IS
53
54 -----------------------------------------------------------------------------
55 -- f0
56 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
57 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 --
60 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
62 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
64 --
65 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
67 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
68 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 -----------------------------------------------------------------------------
70 -- f1
71 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
73 --
74 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
76 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 -----------------------------------------------------------------------------
79 -- f2
80 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 -----------------------------------------------------------------------------
83 -- f3
84 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 --
87 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 -----------------------------------------------------------------------------
92
93 -----------------------------------------------------------------------------
94 -- SPECTRAL MATRIX
95 -----------------------------------------------------------------------------
96 SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0);
97
98 SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL demux_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL demux_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101
102 SIGNAL fft_fifo_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL fft_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL fft_fifo_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
106
107 SIGNAL SP_fifo_data : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
108 SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
109
110 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL fifo_empty : STD_LOGIC;
112 SIGNAL fifo_ren : STD_LOGIC;
113 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL header_val : STD_LOGIC;
115 SIGNAL header_ack : STD_LOGIC;
116
117 -----------------------------------------------------------------------------
118 -- APB REG
119 -----------------------------------------------------------------------------
120 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
121 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
122 SIGNAL ready_matrix_f1 : STD_LOGIC;
123 SIGNAL ready_matrix_f2 : STD_LOGIC;
124 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
125 SIGNAL error_bad_component_error : STD_LOGIC;
126 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
128 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
129 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
130 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
131 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
132 SIGNAL status_error_bad_component_error : STD_LOGIC;
133 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
134 SIGNAL config_active_interruption_onError : STD_LOGIC;
135 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139
140 BEGIN
141
142 -----------------------------------------------------------------------------
143 -- CNA + FILTER
144 -----------------------------------------------------------------------------
145 lpp_top_acq_1 : lpp_top_acq
146 GENERIC MAP (
147 tech => tech)
148 PORT MAP (
149 cnv_run => cnv_run,
150 cnv => cnv,
151 sck => sck,
152 sdo => sdo,
153 cnv_clk => cnv_clk,
154 cnv_rstn => cnv_rstn,
155 clk => clk,
156 rstn => rstn,
157
158 sample_f0_0_wen => sample_f0_0_wen,
159 sample_f0_1_wen => sample_f0_1_wen,
160 sample_f0_wdata => sample_f0_wdata,
161 sample_f1_wen => sample_f1_wen,
162 sample_f1_wdata => sample_f1_wdata,
163 sample_f2_wen => sample_f2_wen,
164 sample_f2_wdata => sample_f2_wdata,
165 sample_f3_wen => sample_f3_wen,
166 sample_f3_wdata => sample_f3_wdata);
167
168 -----------------------------------------------------------------------------
169 -- FIFO
170 -----------------------------------------------------------------------------
171
172 lppFIFO_f0_0 : lppFIFOxN
173 GENERIC MAP (
174 tech => tech,
175 Data_sz => 16,
176 FifoCnt => 5,
177 Enable_ReUse => '0')
178 PORT MAP (
179 rst => rstn,
180 wclk => clk,
181 rclk => clk,
182 ReUse => (OTHERS => '0'),
183
184 wen => sample_f0_0_wen,
185 ren => sample_f0_0_ren,
186 wdata => sample_f0_wdata,
187 rdata => sample_f0_0_rdata,
188 full => sample_f0_0_full,
189 empty => sample_f0_0_empty);
190
191 lppFIFO_f0_1 : lppFIFOxN
192 GENERIC MAP (
193 tech => tech,
194 Data_sz => 16,
195 FifoCnt => 5,
196 Enable_ReUse => '0')
197 PORT MAP (
198 rst => rstn,
199 wclk => clk,
200 rclk => clk,
201 ReUse => (OTHERS => '0'),
202
203 wen => sample_f0_1_wen,
204 ren => sample_f0_1_ren,
205 wdata => sample_f0_wdata,
206 rdata => sample_f0_1_rdata,
207 full => sample_f0_1_full,
208 empty => sample_f0_1_empty);
209
210 lppFIFO_f1 : lppFIFOxN
211 GENERIC MAP (
212 tech => tech,
213 Data_sz => 16,
214 FifoCnt => 5,
215 Enable_ReUse => '0')
216 PORT MAP (
217 rst => rstn,
218 wclk => clk,
219 rclk => clk,
220 ReUse => (OTHERS => '0'),
221
222 wen => sample_f1_wen,
223 ren => sample_f1_ren,
224 wdata => sample_f1_wdata,
225 rdata => sample_f1_rdata,
226 full => sample_f1_full,
227 empty => sample_f1_empty);
228
229 lppFIFO_f3 : lppFIFOxN
230 GENERIC MAP (
231 tech => tech,
232 Data_sz => 16,
233 FifoCnt => 5,
234 Enable_ReUse => '0')
235 PORT MAP (
236 rst => rstn,
237 wclk => clk,
238 rclk => clk,
239 ReUse => (OTHERS => '0'),
240
241 wen => sample_f3_wen,
242 ren => sample_f3_ren,
243 wdata => sample_f3_wdata,
244 rdata => sample_f3_rdata,
245 full => sample_f3_full,
246 empty => sample_f3_empty);
247
248 -----------------------------------------------------------------------------
249 -- SPECTRAL MATRIX
250 -----------------------------------------------------------------------------
251 sample_f0_0_ren <= sample_ren(4 DOWNTO 0);
252 sample_f0_1_ren <= sample_ren(9 DOWNTO 5);
253 sample_f1_ren <= sample_ren(14 DOWNTO 10);
254 sample_f3_ren <= sample_ren(19 DOWNTO 15);
255
256 Demultiplex_1 : Demultiplex
257 GENERIC MAP (
258 Data_sz => 16)
259 PORT MAP (
260 clk => clk,
261 rstn => rstn,
262
263 Read => demux_ren,
264 EmptyF0a => sample_f0_0_empty,
265 EmptyF0b => sample_f0_0_empty,
266 EmptyF1 => sample_f1_empty,
267 EmptyF2 => sample_f3_empty,
268 DataF0a => sample_f0_0_rdata,
269 DataF0b => sample_f0_1_rdata,
270 DataF1 => sample_f1_rdata,
271 DataF2 => sample_f3_rdata,
272 Read_DEMUX => sample_ren,
273 Empty => demux_empty,
274 Data => demux_data);
275
276 FFT_1 : FFT
277 GENERIC MAP (
278 Data_sz => 16,
279 NbData => 256)
280 PORT MAP (
281 clkm => clk,
282 rstn => rstn,
283 FifoIN_Empty => demux_empty,
284 FifoIN_Data => demux_data,
285 FifoOUT_Full => fft_fifo_full,
286 Read => demux_ren,
287 Write => fft_fifo_wen,
288 ReUse => fft_fifo_reuse,
289 Data => fft_fifo_data);
290
291 lppFIFO_fft : lppFIFOxN
292 GENERIC MAP (
293 tech => tech,
294 Data_sz => 16,
295 FifoCnt => 5,
296 Enable_ReUse => '1')
297 PORT MAP (
298 rst => rstn,
299 wclk => clk,
300 rclk => clk,
301 ReUse => fft_fifo_reuse,
302 wen => fft_fifo_wen,
303 ren => SP_fifo_ren,
304 wdata => fft_fifo_data,
305 rdata => SP_fifo_data,
306 full => fft_fifo_full,
307 empty => OPEN);
308
309 MatriceSpectrale_1: MatriceSpectrale
310 GENERIC MAP (
311 Input_SZ => 16,
312 Result_SZ => 32)
313 PORT MAP (
314 clkm => clk,
315 rstn => rstn,
316
317 FifoIN_Full => fft_fifo_full,
318 FifoOUT_Full => , -- TODO
319 Data_IN => SP_fifo_data,
320 ACQ => , -- TODO
321 FlagError => , -- TODO
322 Pong => , -- TODO
323 Write => , -- TODO
324 Read => SP_fifo_ren,
325 Data_OUT => ); -- TODO
326
327
328 -----------------------------------------------------------------------------
329 -- DMA SPECTRAL MATRIX
330 -----------------------------------------------------------------------------
331 lpp_dma_ip_1 : lpp_dma_ip
332 GENERIC MAP (
333 tech => tech,
334 hindex => hindex_SpectralMatrix)
335 PORT MAP (
336 HCLK => clk,
337 HRESETn => rstn,
338 AHB_Master_In => AHB_DMA_SpectralMatrix_In,
339 AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
340
341 -- Connect to Spectral Matrix --
342 fifo_data => fifo_data,
343 fifo_empty => fifo_empty,
344 fifo_ren => fifo_ren,
345 header => header,
346 header_val => header_val,
347 header_ack => header_ack,
348
349 -- APB REG
350
351 ready_matrix_f0_0 => ready_matrix_f0_0,
352 ready_matrix_f0_1 => ready_matrix_f0_1,
353 ready_matrix_f1 => ready_matrix_f1,
354 ready_matrix_f2 => ready_matrix_f2,
355 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
356 error_bad_component_error => error_bad_component_error,
357 debug_reg => debug_reg,
358 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
359 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
360 status_ready_matrix_f1 => status_ready_matrix_f1,
361 status_ready_matrix_f2 => status_ready_matrix_f2,
362 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
363 status_error_bad_component_error => status_error_bad_component_error,
364 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
365 config_active_interruption_onError => config_active_interruption_onError,
366 addr_matrix_f0_0 => addr_matrix_f0_0,
367 addr_matrix_f0_1 => addr_matrix_f0_1,
368 addr_matrix_f1 => addr_matrix_f1,
369 addr_matrix_f2 => addr_matrix_f2);
370
371 lpp_top_apbreg_1 : lpp_top_apbreg
372 GENERIC MAP (
373 pindex => pindex,
374 paddr => paddr,
375 pmask => pmask,
376 pirq => pirq)
377 PORT MAP (
378 HCLK => clk,
379 HRESETn => rstn,
380 apbi => apbi,
381 apbo => apbo,
382
383 ready_matrix_f0_0 => ready_matrix_f0_0,
384 ready_matrix_f0_1 => ready_matrix_f0_1,
385 ready_matrix_f1 => ready_matrix_f1,
386 ready_matrix_f2 => ready_matrix_f2,
387 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
388 error_bad_component_error => error_bad_component_error,
389 debug_reg => debug_reg,
390 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
391 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
392 status_ready_matrix_f1 => status_ready_matrix_f1,
393 status_ready_matrix_f2 => status_ready_matrix_f2,
394 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
395 status_error_bad_component_error => status_error_bad_component_error,
396 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
397 config_active_interruption_onError => config_active_interruption_onError,
398 addr_matrix_f0_0 => addr_matrix_f0_0,
399 addr_matrix_f0_1 => addr_matrix_f0_1,
400 addr_matrix_f1 => addr_matrix_f1,
401 addr_matrix_f2 => addr_matrix_f2);
402
403
404 --TODO : add the irq alert for DMA matrix transfert ending
405 --TODO : add 5 bit register into APB to control the DATA SHIPING
406 --TODO : add Spectral Matrix (FFT + SP)
407 --TODO : add DMA for WaveForms Picker
408 --TODO : add APB Reg to control WaveForms Picker
409 --TODO : add WaveForms Picker
410
411 END tb;
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@@ -4,7 +4,6 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
4 DESIGNSDIR=designs/
5
5
6
6
7
8 .PHONY:doc
7 .PHONY:doc
9
8
10
9
@@ -54,6 +53,7 Patch-GRLIB: init doc
54
53
55 link:
54 link:
56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
55 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57
57
58 dist: init
58 dist: init
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
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@@ -159,32 +159,32 BEGIN
159 sample_filter_in(i, 17) <= sample(i)(15);
159 sample_filter_in(i, 17) <= sample(i)(15);
160 END GENERATE;
160 END GENERATE;
161
161
162 coefs <= CoefsInitValCst;
162 --coefs <= CoefsInitValCst;
163 coefs_JC <= CoefsInitValCst_JC;
163 coefs_JC <= CoefsInitValCst_v2;
164
164
165 FILTER : IIR_CEL_CTRLR
165 --FILTER : IIR_CEL_CTRLR
166 GENERIC MAP (
166 -- GENERIC MAP (
167 tech => 0,
167 -- tech => 0,
168 Sample_SZ => 18,
168 -- Sample_SZ => 18,
169 ChanelsCount => ChanelCount,
169 -- ChanelsCount => ChanelCount,
170 Coef_SZ => Coef_SZ,
170 -- Coef_SZ => Coef_SZ,
171 CoefCntPerCel => CoefCntPerCel,
171 -- CoefCntPerCel => CoefCntPerCel,
172 Cels_count => Cels_count,
172 -- Cels_count => Cels_count,
173 Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
173 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
174 PORT MAP (
174 -- PORT MAP (
175 reset => rstn,
175 -- reset => rstn,
176 clk => clk,
176 -- clk => clk,
177 sample_clk => sample_val_delay,
177 -- sample_clk => sample_val_delay,
178 sample_in => sample_filter_in,
178 -- sample_in => sample_filter_in,
179 sample_out => sample_filter_out,
179 -- sample_out => sample_filter_out,
180 virg_pos => 7,
180 -- virg_pos => 7,
181 GOtest => OPEN,
181 -- GOtest => OPEN,
182 coefs => coefs);
182 -- coefs => coefs);
183
183
184 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
184 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
185 GENERIC MAP (
185 GENERIC MAP (
186 tech => 0,
186 tech => 0,
187 Mem_use => use_CEL,
187 Mem_use => use_RAM,
188 Sample_SZ => 18,
188 Sample_SZ => 18,
189 Coef_SZ => Coef_SZ,
189 Coef_SZ => Coef_SZ,
190 Coef_Nb => 25, -- TODO
190 Coef_Nb => 25, -- TODO
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@@ -19,7 +19,7 vcom -quiet -93 -work lpp ../../lib/lpp/
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
22 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
23
23
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
@@ -30,9 +30,10 vcom -quiet -93 -work lpp ../../lib/lpp/
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
32
32
33
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
34
34
35 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
36
37
37 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
@@ -41,8 +42,8 vcom -quiet -93 -work lpp ../../lib/lpp/
41 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43
44
44 vsim work.TB_Data_Acquisition
45 #vsim work.TB_Data_Acquisition
45
46
46 log -r *
47 #log -r *
47 do wave_data_acquisition.do
48 #do wave_data_acquisition.do
48 run 5 ms No newline at end of file
49 #run 5 ms No newline at end of file
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@@ -108,7 +108,7 constant a4_2 : std_logic_vector
108
108
109 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
109 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
110
110
111 constant CoefsInitValCst_JC : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
111 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
112 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
112 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
113 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
113 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
114 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
114 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
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@@ -169,8 +169,10 BEGIN
169
169
170 IF (sample_bit_counter MOD 2) = 1 THEN
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 shift_reg(l)(15) <= sdo(l);
172 --shift_reg(l)(15) <= sdo(l);
173 shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
174 END LOOP;
176 END LOOP;
175 SCK <= '0';
177 SCK <= '0';
176 ELSE
178 ELSE
@@ -180,8 +182,10 BEGIN
180 IF sample_bit_counter = 31 THEN
182 IF sample_bit_counter = 31 THEN
181 sample_val <= '1';
183 sample_val <= '1';
182 FOR l IN 0 TO ChanelCount-1 LOOP
184 FOR l IN 0 TO ChanelCount-1 LOOP
183 sample(l)(15) <= sdo(l);
185 --sample(l)(15) <= sdo(l);
184 sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
185 END LOOP;
189 END LOOP;
186 ELSE
190 ELSE
187 sample_val <= '0';
191 sample_val <= '0';
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@@ -104,14 +104,10 BEGIN
104 -- LPP DMA IP
104 -- LPP DMA IP
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106
106
107 lpp_dma_ip_1: ENTITY work.lpp_dma_ip
107 lpp_dma_ip_1: lpp_dma_ip
108 GENERIC MAP (
108 GENERIC MAP (
109 tech => tech,
109 tech => tech,
110 hindex => hindex,
110 hindex => hindex)
111 pindex => pindex,
112 paddr => paddr,
113 pmask => pmask,
114 pirq => pirq)
115 PORT MAP (
111 PORT MAP (
116 HCLK => HCLK,
112 HCLK => HCLK,
117 HRESETn => HRESETn,
113 HRESETn => HRESETn,
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@@ -45,11 +45,8 USE techmap.gencomp.ALL;
45 ENTITY lpp_dma_ip IS
45 ENTITY lpp_dma_ip IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2;
48 hindex : INTEGER := 2
49 pindex : INTEGER := 4;
49 );
50 paddr : INTEGER := 4;
51 pmask : INTEGER := 16#fff#;
52 pirq : INTEGER := 0);
53 PORT (
50 PORT (
54 -- AMBA AHB system signals
51 -- AMBA AHB system signals
55 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
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@@ -164,11 +164,7 PACKAGE lpp_dma_pkg IS
164 COMPONENT lpp_dma_ip
164 COMPONENT lpp_dma_ip
165 GENERIC (
165 GENERIC (
166 tech : INTEGER;
166 tech : INTEGER;
167 hindex : INTEGER;
167 hindex : INTEGER);
168 pindex : INTEGER;
169 paddr : INTEGER;
170 pmask : INTEGER;
171 pirq : INTEGER);
172 PORT (
168 PORT (
173 HCLK : IN STD_ULOGIC;
169 HCLK : IN STD_ULOGIC;
174 HRESETn : IN STD_ULOGIC;
170 HRESETn : IN STD_ULOGIC;
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@@ -20,10 +20,10 ENTITY lpp_top_acq IS
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC; -- clk 49 MHz
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -72,16 +72,14 ARCHITECTURE tb OF lpp_top_acq IS
72 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
74
74
75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
77 --
80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 --
80 --
83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
86 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
87 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out_val : STD_LOGIC;
@@ -145,27 +143,7 BEGIN
145 sample_filter_in(i, 17) <= sample(i)(15);
143 sample_filter_in(i, 17) <= sample(i)(15);
146 END GENERATE;
144 END GENERATE;
147
145
148 -- coefs <= CoefsInitValCst;
146 coefs_v2 <= CoefsInitValCst_v2;
149 coefs_JC <= CoefsInitValCst_JC;
150
151 --FILTER : IIR_CEL_CTRLR
152 -- GENERIC MAP (
153 -- tech => 0,
154 -- Sample_SZ => 18,
155 -- ChanelsCount => ChanelCount,
156 -- Coef_SZ => Coef_SZ,
157 -- CoefCntPerCel => CoefCntPerCel,
158 -- Cels_count => Cels_count,
159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
160 -- PORT MAP (
161 -- reset => rstn,
162 -- clk => clk,
163 -- sample_clk => sample_val_delay,
164 -- sample_in => sample_filter_in,
165 -- sample_out => sample_filter_out,
166 -- virg_pos => 7,
167 -- GOtest => OPEN,
168 -- coefs => coefs);
169
147
170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
148 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 GENERIC MAP (
149 GENERIC MAP (
@@ -181,26 +159,26 BEGIN
181 rstn => rstn,
159 rstn => rstn,
182 clk => clk,
160 clk => clk,
183 virg_pos => 7,
161 virg_pos => 7,
184 coefs => coefs_JC,
162 coefs => coefs_v2,
185 sample_in_val => sample_val_delay,
163 sample_in_val => sample_val_delay,
186 sample_in => sample_filter_in,
164 sample_in => sample_filter_in,
187 sample_out_val => sample_filter_JC_out_val,
165 sample_out_val => sample_filter_v2_out_val,
188 sample_out => sample_filter_JC_out);
166 sample_out => sample_filter_v2_out);
189
167
190 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
191 PROCESS (clk, rstn)
169 PROCESS (clk, rstn)
192 BEGIN -- PROCESS
170 BEGIN -- PROCESS
193 IF rstn = '0' THEN -- asynchronous reset (active low)
171 IF rstn = '0' THEN -- asynchronous reset (active low)
194 sample_filter_JC_out_r_val <= '0';
172 sample_filter_v2_out_r_val <= '0';
195 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
173 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
196 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
174 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
197 sample_filter_JC_out_r(I, J) <= '0';
175 sample_filter_v2_out_r(I, J) <= '0';
198 END LOOP rst_all_bits;
176 END LOOP rst_all_bits;
199 END LOOP rst_all_chanel;
177 END LOOP rst_all_chanel;
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
178 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
179 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
202 IF sample_filter_JC_out_val = '1' THEN
180 IF sample_filter_v2_out_val = '1' THEN
203 sample_filter_JC_out_r <= sample_filter_JC_out;
181 sample_filter_v2_out_r <= sample_filter_v2_out;
204 END IF;
182 END IF;
205 END IF;
183 END IF;
206 END PROCESS;
184 END PROCESS;
@@ -216,8 +194,8 BEGIN
216 PORT MAP (
194 PORT MAP (
217 clk => clk,
195 clk => clk,
218 rstn => rstn,
196 rstn => rstn,
219 sample_in_val => sample_filter_JC_out_val ,
197 sample_in_val => sample_filter_v2_out_val ,
220 sample_in => sample_filter_JC_out,
198 sample_in => sample_filter_v2_out,
221 sample_out_val => sample_f0_val,
199 sample_out_val => sample_f0_val,
222 sample_out => sample_f0);
200 sample_out => sample_f0);
223
201
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@@ -1,5 +1,9
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6
3 LIBRARY lpp;
7 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
@@ -33,4 +37,36 PACKAGE lpp_top_lfr_pkg IS
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
37 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
34 END COMPONENT;
38 END COMPONENT;
35
39
40 COMPONENT lpp_top_apbreg
41 GENERIC (
42 pindex : INTEGER;
43 paddr : INTEGER;
44 pmask : INTEGER;
45 pirq : INTEGER);
46 PORT (
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51 ready_matrix_f0_0 : IN STD_LOGIC;
52 ready_matrix_f0_1 : IN STD_LOGIC;
53 ready_matrix_f1 : IN STD_LOGIC;
54 ready_matrix_f2 : IN STD_LOGIC;
55 error_anticipating_empty_fifo : IN STD_LOGIC;
56 error_bad_component_error : IN STD_LOGIC;
57 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 status_ready_matrix_f0_0 : OUT STD_LOGIC;
59 status_ready_matrix_f0_1 : OUT STD_LOGIC;
60 status_ready_matrix_f1 : OUT STD_LOGIC;
61 status_ready_matrix_f2 : OUT STD_LOGIC;
62 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
63 status_error_bad_component_error : OUT STD_LOGIC;
64 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
65 config_active_interruption_onError : OUT STD_LOGIC;
66 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
70 END COMPONENT;
71
36 END lpp_top_lfr_pkg; No newline at end of file
72 END lpp_top_lfr_pkg;
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@@ -1,2 +1,3
1 lpp_top_acq.vhd
1 lpp_top_acq.vhd
2 lpp_top_lfr.vhd
2 lpp_top_lfr_pkg.vhd
3 lpp_top_lfr_pkg.vhd
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