##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Modif (dma fifo ...)
martin -
r195:2a219a64fd0a martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,90
1 -- FillFifo.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FillFifo is
7 generic(
8 Data_sz : integer range 1 to 32 := 16;
9 Fifo_cnt : integer range 1 to 8 := 5
10 );
11 port(
12 clk : in std_logic;
13 raz : in std_logic;
14 write : out std_logic_vector(Fifo_cnt-1 downto 0);
15 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
16 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
17 );
18 end entity;
19
20
21 architecture ar_FillFifo of FillFifo is
22
23 signal i : integer := 0;
24
25 type etat is (eX,e0,e00);
26 signal ect : etat;
27
28 type Tbl is array(natural range <>) of std_logic_vector(Data_sz-1 downto 0);
29
30 --constant TblA : Tbl (0 to 255) := (X"FFFF",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE",X"0000",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",
31 --X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE");
32
33 constant TblA : Tbl (0 to 255) := (X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
34 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
35 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
36
37 constant TblB : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
38 X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
39 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
40
41 constant TblC : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
42 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
43 X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
44
45 constant TblD : Tbl (0 to 255) := (X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
46 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
47 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
48
49 constant TblE : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
50 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
51 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
52
53 begin
54
55 process(clk,raz)
56 begin
57 if(raz='0')then
58 i <= 0;
59 Write <= (others => '1');
60 Reuse <= (others => '0');
61 ect <= e00;
62
63 elsif(clk'event and clk='1')then
64
65 case ect is
66
67 when e00 =>
68 Write <= (others => '0');
69 ect <= e0;
70
71 when e0 =>
72 if(i=255)then
73 Write <= (others => '1');
74 Reuse <= (others => '1');
75 ect <= eX;
76 else
77 i <= i+1;
78 ect <= e0;
79 end if;
80
81 when eX =>
82 null;
83
84 end case;
85 end if;
86 end process;
87
88 data <= TblE(i) & TblD(i) & TblC(i) & TblB(i) & TblA(i);
89
90 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,93 +1,100
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM_CEL is
27 port( WD : in std_logic_vector(15 downto 0); RD : out
28 std_logic_vector(15 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
32 end RAM_CEL;
33
34
35
36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"0000");
39 signal RD_int : std_logic_vector(15 downto 0);
40
41 begin
42
43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
44
45
46 process(RWclk,reset)
47 begin
48 if reset = '0' then
49 RD <= (X"0000");
50 rst:for i in 0 to 255 loop
51 RAMarray(i) <= (others => '0');
52 end loop;
53
54 elsif RWclk'event and RWclk = '1' then
55 if REN = '0' then
56 RD <= RD_int;
57 end if;
58
59 if WEN = '0' then
60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
61 end if;
62
63 end if;
64 end process;
65 end ar_RAM_CEL;
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM_CEL is
27 generic(DataSz : integer range 1 to 32 := 8;
28 abits : integer range 2 to 12 := 8);
29 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
30 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
31 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
32 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
33 ) ;
34 end RAM_CEL;
35
36
37
38 architecture ar_RAM_CEL of RAM_CEL is
39
40 constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0');
41 constant MAX : integer := 2**(abits);
42
43 type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0);
44
45 signal RAMarray : RAMarrayT:=(others => VectInit);
46 signal RD_int : std_logic_vector(DataSz-1 downto 0);
47
48 begin
49
50 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
51
52
53 process(RWclk,reset)
54 begin
55 if reset = '0' then
56 RD <= VectInit;
57 rst:for i in 0 to MAX-1 loop
58 RAMarray(i) <= (others => '0');
59 end loop;
60
61 elsif RWclk'event and RWclk = '1' then
62 if REN = '0' then
63 RD <= RD_int;
64 end if;
65
66 if WEN = '0' then
67 RAMarray(to_integer(unsigned(WADDR))) <= WD;
68 end if;
69
70 end if;
71 end process;
72 end ar_RAM_CEL;
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Show file before | Show file after | Hide comments
@@ -1,302 +1,300
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY ieee;
23 23 USE ieee.std_logic_1164.ALL;
24 24 LIBRARY grlib;
25 25 USE grlib.amba.ALL;
26 26 USE grlib.stdlib.ALL;
27 27 USE grlib.devices.ALL;
28 28 LIBRARY lpp;
29 29
30 30
31 31
32 32
33 33 PACKAGE iir_filter IS
34 34
35 35
36 36 --===========================================================|
37 37 --================A L U C O N T R O L======================|
38 38 --===========================================================|
39 39 CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
40 40 CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
41 41 CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
42 42 CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
43 43 CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
44 44 CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
45 45
46 46 --____
47 47 --RAM |
48 48 --____|
49 49 CONSTANT use_RAM : INTEGER := 1;
50 50 CONSTANT use_CEL : INTEGER := 0;
51 51
52 52
53 53 --===========================================================|
54 54 --=============C O E F S ====================================|
55 55 --===========================================================|
56 56 -- create a specific type of data for coefs to avoid errors |
57 57 --===========================================================|
58 58
59 59 TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
60 60
61 61 TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
62 62
63 63 TYPE in_IIR_CEL_reg IS RECORD
64 64 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 65 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 66 END RECORD;
67 67
68 68 TYPE out_IIR_CEL_reg IS RECORD
69 69 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 71 END RECORD;
72 72
73 73
74 74 COMPONENT APB_IIR_CEL IS
75 75 GENERIC (
76 76 tech : INTEGER := 0;
77 77 pindex : INTEGER := 0;
78 78 paddr : INTEGER := 0;
79 79 pmask : INTEGER := 16#fff#;
80 80 pirq : INTEGER := 0;
81 81 abits : INTEGER := 8;
82 82 Sample_SZ : INTEGER := 16;
83 83 ChanelsCount : INTEGER := 6;
84 84 Coef_SZ : INTEGER := 9;
85 85 CoefCntPerCel : INTEGER := 6;
86 86 Cels_count : INTEGER := 5;
87 87 virgPos : INTEGER := 7;
88 88 Mem_use : INTEGER := use_RAM
89 89 );
90 90 PORT (
91 91 rst : IN STD_LOGIC;
92 92 clk : IN STD_LOGIC;
93 93 apbi : IN apb_slv_in_type;
94 94 apbo : OUT apb_slv_out_type;
95 95 sample_clk : IN STD_LOGIC;
96 96 sample_clk_out : OUT STD_LOGIC;
97 97 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
98 98 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
99 99 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
100 100 );
101 101 END COMPONENT;
102 102
103 103
104 104 COMPONENT Top_IIR IS
105 105 GENERIC(
106 106 Sample_SZ : INTEGER := 18;
107 107 ChanelsCount : INTEGER := 1;
108 108 Coef_SZ : INTEGER := 9;
109 109 CoefCntPerCel : INTEGER := 6;
110 110 Cels_count : INTEGER := 5);
111 111 PORT(
112 112 reset : IN STD_LOGIC;
113 113 clk : IN STD_LOGIC;
114 114 sample_clk : IN STD_LOGIC;
115 115 -- BP : in std_logic;
116 116 -- BPinput : in std_logic_vector(3 downto 0);
117 117 LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
118 118 INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
119 119 OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
120 120 );
121 121 END COMPONENT;
122 122
123 123 COMPONENT IIR_CEL_CTRLR_v2
124 124 GENERIC (
125 125 tech : INTEGER;
126 126 Mem_use : INTEGER;
127 127 Sample_SZ : INTEGER;
128 128 Coef_SZ : INTEGER;
129 129 Coef_Nb : INTEGER;
130 130 Coef_sel_SZ : INTEGER;
131 131 Cels_count : INTEGER;
132 132 ChanelsCount : INTEGER);
133 133 PORT (
134 134 rstn : IN STD_LOGIC;
135 135 clk : IN STD_LOGIC;
136 136 virg_pos : IN INTEGER;
137 137 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
138 138 sample_in_val : IN STD_LOGIC;
139 139 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 140 sample_out_val : OUT STD_LOGIC;
141 141 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
142 142 END COMPONENT;
143 143
144 144
145 145 --component FilterCTRLR is
146 146 --port(
147 147 -- reset : in std_logic;
148 148 -- clk : in std_logic;
149 149 -- sample_clk : in std_logic;
150 150 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
151 151 -- sample_in : in samplT;
152 152 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
153 153 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
154 154 --);
155 155 --end component;
156 156
157 157
158 158 --component FILTER_RAM_CTRLR is
159 159 --port(
160 160 -- reset : in std_logic;
161 161 -- clk : in std_logic;
162 162 -- run : in std_logic;
163 163 -- GO_0 : in std_logic;
164 164 -- B_A : in std_logic;
165 165 -- writeForce : in std_logic;
166 166 -- next_blk : in std_logic;
167 167 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
168 168 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
169 169 --);
170 170 --end component;
171 171
172 172
173 173 COMPONENT IIR_CEL_CTRLR IS
174 174 GENERIC(
175 175 tech : INTEGER := 0;
176 176 Sample_SZ : INTEGER := 16;
177 177 ChanelsCount : INTEGER := 1;
178 178 Coef_SZ : INTEGER := 9;
179 179 CoefCntPerCel : INTEGER := 3;
180 180 Cels_count : INTEGER := 5;
181 181 Mem_use : INTEGER := use_RAM
182 182 );
183 183 PORT(
184 184 reset : IN STD_LOGIC;
185 185 clk : IN STD_LOGIC;
186 186 sample_clk : IN STD_LOGIC;
187 187 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
188 188 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
189 189 virg_pos : IN INTEGER;
190 190 GOtest : OUT STD_LOGIC;
191 191 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
192 192 );
193 193 END COMPONENT;
194 194
195 195
196 196 COMPONENT RAM IS
197 197 GENERIC(
198 198 Input_SZ_1 : INTEGER := 8
199 199 );
200 200 PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
201 201 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
202 202 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
203 203 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC
204 204 ) ;
205 205 END COMPONENT;
206 206
207 COMPONENT RAM_CEL
208 GENERIC (
209 Sample_SZ : INTEGER);
210 PORT (
211 WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
212 RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
213 WEN, REN : IN STD_LOGIC;
214 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
215 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
216 RWCLK, RESET : IN STD_LOGIC);
217 END COMPONENT;
207 COMPONENT RAM_CEL is
208 generic(DataSz : integer range 1 to 32 := 8;
209 abits : integer range 2 to 12 := 8);
210 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
211 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
212 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
213 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
214 ) ;
215 end COMPONENT;
218 216
219 217 COMPONENT RAM_CEL_N
220 218 GENERIC (
221 219 size : INTEGER);
222 220 PORT (
223 221 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
224 222 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
225 223 WEN, REN : IN STD_LOGIC;
226 224 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
227 225 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
228 226 RWCLK, RESET : IN STD_LOGIC);
229 227 END COMPONENT;
230 228
231 229 COMPONENT IIR_CEL_FILTER IS
232 230 GENERIC(
233 231 tech : INTEGER := 0;
234 232 Sample_SZ : INTEGER := 16;
235 233 ChanelsCount : INTEGER := 1;
236 234 Coef_SZ : INTEGER := 9;
237 235 CoefCntPerCel : INTEGER := 3;
238 236 Cels_count : INTEGER := 5;
239 237 Mem_use : INTEGER := use_RAM);
240 238 PORT(
241 239 reset : IN STD_LOGIC;
242 240 clk : IN STD_LOGIC;
243 241 sample_clk : IN STD_LOGIC;
244 242 regs_in : IN in_IIR_CEL_reg;
245 243 regs_out : IN out_IIR_CEL_reg;
246 244 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
247 245 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
248 246 GOtest : OUT STD_LOGIC;
249 247 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
250 248
251 249 );
252 250 END COMPONENT;
253 251
254 252
255 253 COMPONENT RAM_CTRLR2 IS
256 254 GENERIC(
257 255 tech : INTEGER := 0;
258 256 Input_SZ_1 : INTEGER := 16;
259 257 Mem_use : INTEGER := use_RAM
260 258 );
261 259 PORT(
262 260 reset : IN STD_LOGIC;
263 261 clk : IN STD_LOGIC;
264 262 WD_sel : IN STD_LOGIC;
265 263 Read : IN STD_LOGIC;
266 264 WADDR_sel : IN STD_LOGIC;
267 265 count : IN STD_LOGIC;
268 266 SVG_ADDR : IN STD_LOGIC;
269 267 Write : IN STD_LOGIC;
270 268 GO_0 : IN STD_LOGIC;
271 269 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
272 270 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
273 271 );
274 272 END COMPONENT;
275 273
276 274 COMPONENT APB_IIR_Filter IS
277 275 GENERIC (
278 276 tech : INTEGER := 0;
279 277 pindex : INTEGER := 0;
280 278 paddr : INTEGER := 0;
281 279 pmask : INTEGER := 16#fff#;
282 280 pirq : INTEGER := 0;
283 281 abits : INTEGER := 8;
284 282 Sample_SZ : INTEGER := 16;
285 283 ChanelsCount : INTEGER := 1;
286 284 Coef_SZ : INTEGER := 9;
287 285 CoefCntPerCel : INTEGER := 6;
288 286 Cels_count : INTEGER := 5;
289 287 virgPos : INTEGER := 3;
290 288 Mem_use : INTEGER := use_RAM
291 289 );
292 290 PORT (
293 291 rst : IN STD_LOGIC;
294 292 clk : IN STD_LOGIC;
295 293 apbi : IN apb_slv_in_type;
296 294 apbo : OUT apb_slv_out_type;
297 295 sample_clk_out : OUT STD_LOGIC;
298 296 GOtest : OUT STD_LOGIC;
299 297 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
300 298 );
301 299 END COMPONENT;
302 300 END;
Show file before | Show file after | Hide comments
@@ -1,111 +1,188
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 entity HeaderBuilder is
27 27 generic(
28 28 Data_sz : integer := 32);
29 29 port(
30 30 clkm : in std_logic;
31 31 rstn : in std_logic;
32 32
33 33 pong : in std_logic;
34 34 Statu : in std_logic_vector(3 downto 0);
35 35 Matrix_Type : in std_logic_vector(1 downto 0);
36 36 Matrix_Write : in std_logic;
37 37 Valid : out std_logic;
38 38
39 39 dataIN : in std_logic_vector((2*Data_sz)-1 downto 0);
40 40 emptyIN : in std_logic_vector(1 downto 0);
41 41 RenOUT : out std_logic_vector(1 downto 0);
42 42
43 43 dataOUT : out std_logic_vector(Data_sz-1 downto 0);
44 44 emptyOUT : out std_logic;
45 45 RenIN : in std_logic;
46 46
47 47 header : out std_logic_vector(Data_sz-1 DOWNTO 0);
48 48 header_val : out std_logic;
49 49 header_ack : in std_logic
50 50 );
51 51 end entity;
52 52
53 53
54 54 architecture ar_HeaderBuilder of HeaderBuilder is
55 55
56 56 signal Matrix_Param : std_logic_vector(3 downto 0);
57 57 signal Write_reg : std_logic;
58 58 signal Data_cpt : integer;
59 59 signal MAX : integer;
60 signal pong_reg : std_logic;
60 61
62 type etat is (idle0,idle1,pong0,pong1);
63 signal ect : etat;
61 64
62 65 begin
63 66
64 67 process (clkm,rstn)
65 68 begin
66 69 if(rstn='0')then
70 ect <= idle0;
67 71 Valid <= '0';
72 pong_reg <= '0';
73 header_val <= '0';
74 header(5 downto 0) <= (others => '0');
68 75 Write_reg <= '0';
69 76 Data_cpt <= 0;
70 MAX <= 0;
77 MAX <= 128;
71 78
72 79
73 80 elsif(clkm' event and clkm='1')then
74 81 Write_reg <= Matrix_Write;
82 pong_reg <= pong;
75 83
76 84 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 85 MAX <= 128;
78 86 else
79 87 MAX <= 256;
80 88 end if;
81 89
82 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
84 Data_cpt <= 0;
85 Valid <= '1';
86 header_val <= '1';
87 else
88 Data_cpt <= Data_cpt + 1;
89 Valid <= '0';
90 end if;
90 -- if(Write_reg = '0' and Matrix_Write = '1')then
91 -- if(Data_cpt = MAX)then
92 -- Data_cpt <= 0;
93 -- Valid <= '1';
94 -- header_val <= '1';
95 -- else
96 -- Data_cpt <= Data_cpt + 1;
97 -- Valid <= '0';
98 -- end if;
99 -- end if;
100
101 if(Write_reg = '0' and Matrix_Write = '1')then
102 Data_cpt <= Data_cpt + 1;
103 Valid <= '0';
104 elsif(Data_cpt = MAX)then
105 Data_cpt <= 0;
106 Valid <= '1';
107 header_val <= '1';
108 else
109 Valid <= '0';
91 110 end if;
92 111
93 if(header_ack = '1')then
94 header_val <= '0';
95 end if;
96
112 -- if(header_ack = '1')then
113 -- header_val <= '0';
114 -- end if;
115
116 -- if(emptyIN = "10")then
117 -- ping <= '0';
118 -- elsif(emptyIN = "01")then
119 -- ping <= '1';
120 -- else
121 -- ping <= ping;
122 -- end if;
123
124
125 case ect is
126
127 when idle0 =>
128 if(header_ack = '1')then
129 header_val <= '0';
130 --if(pong = '1')then
131 ect <= pong0;
132 --elsif(pong = '0')then
133 --ect <= pong1;
134 --end if;
135 end if;
136
137 when pong0 =>
138 header(1 downto 0) <= Matrix_Type;
139 header(5 downto 2) <= Matrix_Param;
140 if(emptyIN(0) = '1')then
141 ect <= idle1;
142 end if;
143
144 when idle1 =>
145 if(header_ack = '1')then
146 header_val <= '0';
147 ect <= pong1;
148 end if;
149
150 when pong1 =>
151 header(1 downto 0) <= Matrix_Type;
152 header(5 downto 2) <= Matrix_Param;
153 if(emptyIN(1) = '1')then
154 ect <= idle0;
155 end if;
156
157 end case;
97 158 end if;
98 159 end process;
99 160
100 161 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101 162
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
163 --header(1 downto 0) <= Matrix_Type;
164 --header(5 downto 2) <= Matrix_Param;
104 165 header(31 downto 6) <= (others => '0');
105 166
106 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
107 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
167 with ect select
168 dataOUT <= dataIN(Data_sz-1 downto 0) when pong0,
169 dataIN(Data_sz-1 downto 0) when idle0,
170 dataIN((2*Data_sz)-1 downto Data_sz) when pong1,
171 dataIN((2*Data_sz)-1 downto Data_sz) when idle1,
172 (others => '0') when others;
108 173
109 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
174 with ect select
175 emptyOUT <= emptyIN(0) when pong0,
176 emptyIN(0) when idle0,
177 emptyIN(1) when pong1,
178 emptyIN(1) when idle1,
179 '1' when others;
180
181 with ect select
182 RenOUT <= '1' & RenIN when pong0,
183 '1' & RenIN when idle0,
184 RenIN & '1' when pong1,
185 RenIN & '1' when idle1,
186 "11" when others;
110 187
111 188 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,352 +1,365
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_amba.ALL;
38 38 USE lpp.apb_devices_list.ALL;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_dma_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
44 44
45 45 ENTITY lpp_dma_ip IS
46 46 GENERIC (
47 47 tech : INTEGER := inferred;
48 48 hindex : INTEGER := 2
49 49 );
50 50 PORT (
51 51 -- AMBA AHB system signals
52 52 HCLK : IN STD_ULOGIC;
53 53 HRESETn : IN STD_ULOGIC;
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 -- fifo interface
60 60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 fifo_empty : IN STD_LOGIC;
62 62 fifo_ren : OUT STD_LOGIC;
63 63
64 64 -- header
65 65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 66 header_val : IN STD_LOGIC;
67 67 header_ack : OUT STD_LOGIC;
68 68
69 69 -- Reg out
70 70 ready_matrix_f0_0 : OUT STD_LOGIC;
71 71 ready_matrix_f0_1 : OUT STD_LOGIC;
72 72 ready_matrix_f1 : OUT STD_LOGIC;
73 73 ready_matrix_f2 : OUT STD_LOGIC;
74 74 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 75 error_bad_component_error : OUT STD_LOGIC;
76 76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 77
78 78 -- Reg In
79 79 status_ready_matrix_f0_0 :IN STD_LOGIC;
80 80 status_ready_matrix_f0_1 :IN STD_LOGIC;
81 81 status_ready_matrix_f1 :IN STD_LOGIC;
82 82 status_ready_matrix_f2 :IN STD_LOGIC;
83 83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
84 84 status_error_bad_component_error :IN STD_LOGIC;
85 85
86 86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 87 config_active_interruption_onError : IN STD_LOGIC;
88 88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 92 );
93 93 END;
94 94
95 95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
96 96 -----------------------------------------------------------------------------
97 97 SIGNAL DMAIn : DMA_In_Type;
98 98 SIGNAL header_dmai : DMA_In_Type;
99 99 SIGNAL component_dmai : DMA_In_Type;
100 100 SIGNAL DMAOut : DMA_OUt_Type;
101 101 -----------------------------------------------------------------------------
102 102
103 103 -----------------------------------------------------------------------------
104 104 -----------------------------------------------------------------------------
105 105 TYPE state_DMAWriteBurst IS (IDLE,
106 CHECK_COMPONENT_TYPE,
106 107 TRASH_FIFO,
107 108 WAIT_HEADER_ACK,
108 109 SEND_DATA,
109 110 WAIT_DATA_ACK,
110 111 CHECK_LENGTH
111 112 );
112 113 SIGNAL state : state_DMAWriteBurst := IDLE;
113 114
114 115 SIGNAL nbSend : INTEGER;
115 116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 119 SIGNAL header_check_ok : STD_LOGIC;
119 120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 121 SIGNAL send_matrix : STD_LOGIC;
121 122 SIGNAL request : STD_LOGIC;
122 123 SIGNAL remaining_data_request : INTEGER;
123 124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 125 -----------------------------------------------------------------------------
125 126 -----------------------------------------------------------------------------
126 127 SIGNAL header_select : STD_LOGIC;
127 128
128 129 SIGNAL header_send : STD_LOGIC;
129 130 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 131 SIGNAL header_send_ok : STD_LOGIC;
131 132 SIGNAL header_send_ko : STD_LOGIC;
132 133
133 134 SIGNAL component_send : STD_LOGIC;
134 135 SIGNAL component_send_ok : STD_LOGIC;
135 136 SIGNAL component_send_ko : STD_LOGIC;
136 137 -----------------------------------------------------------------------------
137 138 SIGNAL fifo_ren_trash : STD_LOGIC;
138 139 SIGNAL component_fifo_ren : STD_LOGIC;
139 140
140 141 -----------------------------------------------------------------------------
141 142 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 143
143 144 BEGIN
144 145
145 146 -----------------------------------------------------------------------------
146 147 -- DMA to AHB interface
147 148 -----------------------------------------------------------------------------
148 149
149 150 DMA2AHB_1 : DMA2AHB
150 151 GENERIC MAP (
151 152 hindex => hindex,
152 153 vendorid => VENDOR_LPP,
153 154 deviceid => 0,
154 155 version => 0,
155 156 syncrst => 1,
156 157 boundary => 1) -- FIX 11/01/2013
157 158 PORT MAP (
158 159 HCLK => HCLK,
159 160 HRESETn => HRESETn,
160 161 DMAIn => DMAIn,
161 162 DMAOut => DMAOut,
162 163 AHBIn => AHB_Master_In,
163 164 AHBOut => AHB_Master_Out);
164 165
165 166 debug_reg <= debug_reg_s;
166 167
167 168 debug_info: PROCESS (HCLK, HRESETn)
168 169 BEGIN -- PROCESS debug_info
169 170 IF HRESETn = '0' THEN -- asynchronous reset (active low)
170 171 debug_reg_s <= (OTHERS => '0');
171 172 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
172 173 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
173 174 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
174 175 IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF;
175 176 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
176 177 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
177 178 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
178 179 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
179 180
180 181 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
181 182 END IF;
182 183 END PROCESS debug_info;
183 184
184 185
185 matrix_type <= header(1 DOWNTO 0);
186 component_type <= header(5 DOWNTO 2);
186
187 187
188 188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
190 190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
191 191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 192 '0';
193 193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
195 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
196 196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 197 '0';
198 198
199 199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
200 200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
201 201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
202 202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
203 203 (OTHERS => '0');
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- DMA control
207 207 -----------------------------------------------------------------------------
208 208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 209 BEGIN -- PROCESS DMAWriteBurst_p
210 210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 matrix_type <= (others => '0');
212 component_type <= (others => '0');
211 213 state <= IDLE;
212 214 header_ack <= '0';
213 215 ready_matrix_f0_0 <= '0';
214 216 ready_matrix_f0_1 <= '0';
215 217 ready_matrix_f1 <= '0';
216 218 ready_matrix_f2 <= '0';
217 219 error_anticipating_empty_fifo <= '0';
218 220 error_bad_component_error <= '0';
219 component_type_pre <= "1110";
221 component_type_pre <= "0000";
220 222 fifo_ren_trash <= '1';
221 223 component_send <= '0';
222 224 address <= (OTHERS => '0');
223 225 header_select <= '0';
224 226 header_send <= '0';
225 227 header_data <= (OTHERS => '0');
226 228 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
227 229
228 230 CASE state IS
229 WHEN IDLE =>
231 WHEN IDLE =>
232 matrix_type <= header(1 DOWNTO 0);
233 --component_type <= header(5 DOWNTO 2);
234
230 235 ready_matrix_f0_0 <= '0';
231 236 ready_matrix_f0_1 <= '0';
232 237 ready_matrix_f1 <= '0';
233 238 ready_matrix_f2 <= '0';
234 239 error_bad_component_error <= '0';
235 240 header_select <= '1';
236 241 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
242 matrix_type <= header(1 DOWNTO 0);
243 component_type <= header(5 DOWNTO 2);
244 component_type_pre <= component_type;
245 state <= CHECK_COMPONENT_TYPE;
246 END IF;
247
248 WHEN CHECK_COMPONENT_TYPE =>
237 249 IF header_check_ok = '1' THEN
238 header_data <= header;
239 component_type_pre <= header(5 DOWNTO 2);
240 250 header_ack <= '1';
241 251 --
242 252 header_send <= '1';
243 253 IF component_type = "0000" THEN
244 254 address <= address_matrix;
245 255 END IF;
246 256 header_data <= header;
247 257 --
248 258 state <= WAIT_HEADER_ACK;
249 259 ELSE
250 error_bad_component_error <= '1';
251 component_type_pre <= "1110";
260 error_bad_component_error <= '1';
261 component_type_pre <= "0000";
252 262 header_ack <= '1';
253 263 state <= TRASH_FIFO;
254 264 END IF;
255 END IF;
265
256 266
257 267 WHEN TRASH_FIFO =>
268 header_ack <= '0';
258 269 error_bad_component_error <= '0';
259 270 error_anticipating_empty_fifo <= '0';
260 271 IF fifo_empty = '1' THEN
261 272 state <= IDLE;
262 273 fifo_ren_trash <= '1';
263 274 ELSE
264 275 fifo_ren_trash <= '0';
265 276 END IF;
266
277
267 278 WHEN WAIT_HEADER_ACK =>
279 header_ack <= '0';
268 280 header_send <= '0';
269 281 IF header_send_ko = '1' THEN
270 282 state <= TRASH_FIFO;
271 283 error_anticipating_empty_fifo <= '1';
272 284 -- TODO : error sending header
273 285 ELSIF header_send_ok = '1' THEN
274 286 header_select <= '0';
275 287 state <= SEND_DATA;
276 288 address <= address + 4;
277 289 END IF;
278 290
279 291 WHEN SEND_DATA =>
280 292 IF fifo_empty = '1' THEN
281 293 state <= IDLE;
282 IF component_type = "1110" THEN
294 IF component_type = "1110" THEN --"1110" -- JC
283 295 CASE matrix_type IS
284 296 WHEN "00" => ready_matrix_f0_0 <= '1';
285 297 WHEN "01" => ready_matrix_f0_1 <= '1';
286 298 WHEN "10" => ready_matrix_f1 <= '1';
287 299 WHEN "11" => ready_matrix_f2 <= '1';
288 300 WHEN OTHERS => NULL;
289 301 END CASE;
302
290 303 END IF;
291 304 ELSE
292 305 component_send <= '1';
293 306 address <= address;
294 307 state <= WAIT_DATA_ACK;
295 308 END IF;
296 309
297 310 WHEN WAIT_DATA_ACK =>
298 311 component_send <= '0';
299 312 IF component_send_ok = '1' THEN
300 313 address <= address + 64;
301 314 state <= SEND_DATA;
302 315 ELSIF component_send_ko = '1' THEN
303 316 error_anticipating_empty_fifo <= '0';
304 317 state <= TRASH_FIFO;
305 318 END IF;
306 319
307 320 WHEN CHECK_LENGTH =>
308 321 state <= IDLE;
309 322 WHEN OTHERS => NULL;
310 323 END CASE;
311 324
312 325 END IF;
313 326 END PROCESS DMAWriteFSM_p;
314 327
315 328 -----------------------------------------------------------------------------
316 329 -- SEND 1 word by DMA
317 330 -----------------------------------------------------------------------------
318 331 lpp_dma_send_1word_1 : lpp_dma_send_1word
319 332 PORT MAP (
320 333 HCLK => HCLK,
321 334 HRESETn => HRESETn,
322 335 DMAIn => header_dmai,
323 336 DMAOut => DMAOut,
324 337
325 338 send => header_send,
326 339 address => address,
327 340 data => header_data,
328 341 send_ok => header_send_ok,
329 342 send_ko => header_send_ko
330 343 );
331 344
332 345 -----------------------------------------------------------------------------
333 346 -- SEND 16 word by DMA (in burst mode)
334 347 -----------------------------------------------------------------------------
335 348 lpp_dma_send_16word_1 : lpp_dma_send_16word
336 349 PORT MAP (
337 350 HCLK => HCLK,
338 351 HRESETn => HRESETn,
339 352 DMAIn => component_dmai,
340 353 DMAOut => DMAOut,
341 354
342 355 send => component_send,
343 356 address => address,
344 357 data => fifo_data,
345 358 ren => component_fifo_ren,
346 359 send_ok => component_send_ok,
347 360 send_ko => component_send_ko);
348 361
349 362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
350 363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
351 364
352 365 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (525 lines changed) Show them Hide them
@@ -1,263 +1,264
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 -- APB_FIFO.vhd
23 library ieee;
24 use ieee.std_logic_1164.all;
25 use IEEE.numeric_std.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library grlib;
29 use grlib.amba.all;
30 use grlib.stdlib.all;
31 use grlib.devices.all;
32 library lpp;
33 use lpp.lpp_amba.all;
34 use lpp.apb_devices_list.all;
35 use lpp.lpp_memory.all;
36
37
38 entity APB_FIFO is
39 generic (
40 tech : integer := apa3;
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
50 R : integer := 1;
51 W : integer := 1
52 );
53 port (
54 clk : in std_logic; --! Horloge du composant
55 rst : in std_logic; --! Reset general du composant
56 rclk : in std_logic;
57 wclk : in std_logic;
58 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 );
70 end entity;
71
72 architecture ar_APB_FIFO of APB_FIFO is
73
74 constant REVISION : integer := 1;
75
76 constant pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
78 1 => apb_iobar(paddr, pmask));
79
80 type FIFO_ctrlr_Reg is record
81 FIFO_Ctrl : std_logic_vector(31 downto 0);
82 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
83 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
84 end record;
85
86 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
87 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
88 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
89
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
109
110 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
111 signal regData : fifodatabus;
112 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
113
114 type state_t is (idle,Read);
115 signal fiforeadfsmst : state_t;
116
117 begin
118
119 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
120 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
121 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
122
123
124 Writeint : if W /= 0 generate
125 FIFO_ID(4) <= '1';
126 sWen <= sWen_APB;
127 sReUse <= sReUse_APB;
128 sWclk <= clk;
129 Wrapb: for i in 0 to FifoCnt-1 generate
130 sWDATA(i) <= Rec(i).FIFO_Wdata;
131 end generate;
132 end generate;
133
134 Writeext : if W = 0 generate
135 FIFO_ID(4) <= '0';
136 sWen <= WEN;
137 sReUse <= ReUse;
138 sWclk <= Wclk;
139 Wrext: for i in 0 to FifoCnt-1 generate
140 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
141 end generate;
142 end generate;
143
144 Readint : if R /= 0 generate
145 FIFO_ID(5) <= '1';
146 sRen <= sRen_APB;
147 srclk <= clk;
148 Rdapb: for i in 0 to FifoCnt-1 generate
149 Rec(i).FIFO_Rdata <= sRDATA(i);
150 end generate;
151 end generate;
152
153 Readext : if R = 0 generate
154 FIFO_ID(5) <= '0';
155 sRen <= REN;
156 srclk <= rclk;
157 Drext: for i in 0 to FifoCnt-1 generate
158 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
159 end generate;
160 end generate;
161
162 ctrlregs: for i in 0 to FifoCnt-1 generate
163 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
164 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
165 Rec(i).FIFO_Ctrl(16) <= sFull(i);
166 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
167 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
168 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
169 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
170 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
171 end generate;
172
173 Empty <= sEmpty;
174 Full <= sFull;
175
176 fifos: for i in 0 to FifoCnt-1 generate
177 FIFO0 : lpp_fifo
178 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
179 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
180 end generate;
181
182 process(rst,clk)
183 begin
184 if(rst='0')then
185 rstloop1: for i in 0 to FifoCnt-1 loop
186 Rec(i).FIFO_Wdata <= (others => '0');
187 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
188 sWen_APB(i) <= '1';
189 end loop;
190 elsif(clk'event and clk='1')then
191
192 --APB Write OP
193 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
194 writelp: for i in 0 to FifoCnt-1 loop
195 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
196 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
197 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
198 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
199 sWen_APB(i) <= '0';
200 end if;
201 end loop;
202 else
203 sWen_APB <= (others =>'1');
204 end if;
205
206 --APB Read OP
207 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
208 if(apbi.paddr(abits-1 downto 2)="000000") then
209 PRdata <= FIFO_ID;
210 else
211 readlp: for i in 0 to FifoCnt-1 loop
212 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
213 PRdata <= Rec(i).FIFO_Ctrl;
214 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
215 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
216 end if;
217 end loop;
218 end if;
219 end if;
220 end if;
221
222 apbo.pconfig <= pconfig;
223
224 end process;
225 apbo.prdata <= PRdata when apbi.penable = '1';
226
227 process(rst,clk)
228 begin
229 if(rst='0')then
230 fiforeadfsmst <= idle;
231 rstloop: for i in 0 to FifoCnt-1 loop
232 sRen_APB(i) <= '1';
233 autoloaded(i) <= '1';
234 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
235 end loop;
236 elsif clk'event and clk = '1' then
237 sEmpty_d <= sEmpty;
238 case fiforeadfsmst is
239 when idle =>
240 idlelp: for i in 0 to FifoCnt-1 loop
241 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
242 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
243 autoloaded(i) <= '0';
244 else
245 autoloaded(i) <= '1';
246 end if;
247 sRen_APB(i) <= '0';
248 fiforeadfsmst <= read;
249 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
250 else
251 sRen_APB(i) <= '1';
252 end if;
253 end loop;
254 when read =>
255 sRen_APB <= (others => '1');
256 fiforeadfsmst <= idle;
257 when others =>
258 fiforeadfsmst <= idle;
259 end case;
260 end if;
261 end process;
262
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 -- APB_FIFO.vhd
23 library ieee;
24 use ieee.std_logic_1164.all;
25 use IEEE.numeric_std.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library grlib;
29 use grlib.amba.all;
30 use grlib.stdlib.all;
31 use grlib.devices.all;
32 library lpp;
33 use lpp.lpp_amba.all;
34 use lpp.apb_devices_list.all;
35 use lpp.lpp_memory.all;
36 use lpp.iir_filter.all;
37
38 entity APB_FIFO is
39 generic (
40 tech : integer := apa3;
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
50 Mem_use : integer := use_RAM;
51 R : integer := 1;
52 W : integer := 1
53 );
54 port (
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
71 end entity;
72
73 architecture ar_APB_FIFO of APB_FIFO is
74
75 constant REVISION : integer := 1;
76
77 constant pconfig : apb_config_type := (
78 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
79 1 => apb_iobar(paddr, pmask));
80
81 type FIFO_ctrlr_Reg is record
82 FIFO_Ctrl : std_logic_vector(31 downto 0);
83 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
84 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
85 end record;
86
87 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
88 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
89 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
90
91 signal Rec : FIFO_ctrlr_Reg_Vec;
92 signal PRdata : std_logic_vector(31 downto 0);
93 signal FIFO_ID : std_logic_vector(31 downto 0);
94 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
95 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
97 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
98 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
100 signal sRclk : std_logic;
101 signal sWclk : std_logic;
102 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
104 signal sRDATA : fifodatabus;
105 signal sWDATA : fifodatabus;
106 signal sWADDR : fifoaddressbus;
107 signal sRADDR : fifoaddressbus;
108 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
109 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
110
111 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
112 signal regData : fifodatabus;
113 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
114
115 type state_t is (idle,Read);
116 signal fiforeadfsmst : state_t;
117
118 begin
119
120 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
121 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
122 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
123
124
125 Writeint : if W /= 0 generate
126 FIFO_ID(4) <= '1';
127 sWen <= sWen_APB;
128 sReUse <= sReUse_APB;
129 sWclk <= clk;
130 Wrapb: for i in 0 to FifoCnt-1 generate
131 sWDATA(i) <= Rec(i).FIFO_Wdata;
132 end generate;
133 end generate;
134
135 Writeext : if W = 0 generate
136 FIFO_ID(4) <= '0';
137 sWen <= WEN;
138 sReUse <= ReUse;
139 sWclk <= Wclk;
140 Wrext: for i in 0 to FifoCnt-1 generate
141 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
142 end generate;
143 end generate;
144
145 Readint : if R /= 0 generate
146 FIFO_ID(5) <= '1';
147 sRen <= sRen_APB;
148 srclk <= clk;
149 Rdapb: for i in 0 to FifoCnt-1 generate
150 Rec(i).FIFO_Rdata <= sRDATA(i);
151 end generate;
152 end generate;
153
154 Readext : if R = 0 generate
155 FIFO_ID(5) <= '0';
156 sRen <= REN;
157 srclk <= rclk;
158 Drext: for i in 0 to FifoCnt-1 generate
159 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
160 end generate;
161 end generate;
162
163 ctrlregs: for i in 0 to FifoCnt-1 generate
164 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
165 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
166 Rec(i).FIFO_Ctrl(16) <= sFull(i);
167 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
168 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
169 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
170 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
171 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
172 end generate;
173
174 Empty <= sEmpty;
175 Full <= sFull;
176
177 fifos: for i in 0 to FifoCnt-1 generate
178 FIFO0 : lpp_fifo
179 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
180 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
181 end generate;
182
183 process(rst,clk)
184 begin
185 if(rst='0')then
186 rstloop1: for i in 0 to FifoCnt-1 loop
187 Rec(i).FIFO_Wdata <= (others => '0');
188 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
189 sWen_APB(i) <= '1';
190 end loop;
191 elsif(clk'event and clk='1')then
192
193 --APB Write OP
194 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
195 writelp: for i in 0 to FifoCnt-1 loop
196 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
197 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
198 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
199 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
200 sWen_APB(i) <= '0';
201 end if;
202 end loop;
203 else
204 sWen_APB <= (others =>'1');
205 end if;
206
207 --APB Read OP
208 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
209 if(apbi.paddr(abits-1 downto 2)="000000") then
210 PRdata <= FIFO_ID;
211 else
212 readlp: for i in 0 to FifoCnt-1 loop
213 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
214 PRdata <= Rec(i).FIFO_Ctrl;
215 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
216 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
217 end if;
218 end loop;
219 end if;
220 end if;
221 end if;
222
223 apbo.pconfig <= pconfig;
224
225 end process;
226 apbo.prdata <= PRdata when apbi.penable = '1';
227
228 process(rst,clk)
229 begin
230 if(rst='0')then
231 fiforeadfsmst <= idle;
232 rstloop: for i in 0 to FifoCnt-1 loop
233 sRen_APB(i) <= '1';
234 autoloaded(i) <= '1';
235 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
236 end loop;
237 elsif clk'event and clk = '1' then
238 sEmpty_d <= sEmpty;
239 case fiforeadfsmst is
240 when idle =>
241 idlelp: for i in 0 to FifoCnt-1 loop
242 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
243 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
244 autoloaded(i) <= '0';
245 else
246 autoloaded(i) <= '1';
247 end if;
248 sRen_APB(i) <= '0';
249 fiforeadfsmst <= read;
250 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
251 else
252 sRen_APB(i) <= '1';
253 end if;
254 end loop;
255 when read =>
256 sRen_APB <= (others => '1');
257 fiforeadfsmst <= idle;
258 when others =>
259 fiforeadfsmst <= idle;
260 end case;
261 end if;
262 end process;
263
263 264 end ar_APB_FIFO; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,64 +1,66
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity lppFIFOxN is
31 generic(
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
34 Addr_sz : integer range 1 to 32 := 8;
35 FifoCnt : integer := 1;
36 Enable_ReUse : std_logic := '0'
37 );
38 port(
39 rst : in std_logic;
40 wclk : in std_logic;
41 rclk : in std_logic;
42 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
43 wen : in std_logic_vector(FifoCnt-1 downto 0);
44 ren : in std_logic_vector(FifoCnt-1 downto 0);
45 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
46 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
47 full : out std_logic_vector(FifoCnt-1 downto 0);
48 empty : out std_logic_vector(FifoCnt-1 downto 0)
49 );
50 end entity;
51
52
53 architecture ar_lppFIFOxN of lppFIFOxN is
54
55 begin
56
57 fifos: for i in 0 to FifoCnt-1 generate
58 FIFO0 : lpp_fifo
59 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
60 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
61 end generate;
62
63 end architecture;
64
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
28 library techmap;
29 use techmap.gencomp.all;
30
31 entity lppFIFOxN is
32 generic(
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 1 to 32 := 8;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
39 );
40 port(
41 rst : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
51 );
52 end entity;
53
54
55 architecture ar_lppFIFOxN of lppFIFOxN is
56
57 begin
58
59 fifos: for i in 0 to FifoCnt-1 generate
60 FIFO0 : lpp_fifo
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
63 end generate;
64
65 end architecture;
66
Show file before | Show file after | Hide comments
@@ -1,174 +1,180
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library lpp;
26 26 use lpp.lpp_memory.all;
27 27 use lpp.iir_filter.all;
28 28 library techmap;
29 29 use techmap.gencomp.all;
30 30
31 31 entity lpp_fifo is
32 32 generic(
33 33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
34 35 Enable_ReUse : std_logic := '0';
35 36 DataSz : integer range 1 to 32 := 8;
36 37 abits : integer range 2 to 12 := 8
37 38 );
38 39 port(
39 40 rstn : in std_logic;
40 41 ReUse : in std_logic;
41 42 rclk : in std_logic;
42 43 ren : in std_logic;
43 44 rdata : out std_logic_vector(DataSz-1 downto 0);
44 45 empty : out std_logic;
45 46 raddr : out std_logic_vector(abits-1 downto 0);
46 47 wclk : in std_logic;
47 48 wen : in std_logic;
48 49 wdata : in std_logic_vector(DataSz-1 downto 0);
49 50 full : out std_logic;
50 51 waddr : out std_logic_vector(abits-1 downto 0)
51 52 );
52 53 end entity;
53 54
54 55
55 56 architecture ar_lpp_fifo of lpp_fifo is
56 57
57 58 signal sFull : std_logic;
58 59 signal sFull_s : std_logic;
59 60 signal sEmpty_s : std_logic;
60 61
61 62 signal sEmpty : std_logic;
62 63 signal sREN : std_logic;
63 64 signal sWEN : std_logic;
64 65 signal sRE : std_logic;
65 66 signal sWE : std_logic;
66 67
67 68 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
68 69 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 70 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 71 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
71 72
72 73 begin
73 74
74 75 --==================================================================================
75 76 -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
76 77 -- A l'inverse de RAM_CEL !!!
77 78 --==================================================================================
78 SRAM : syncram_2p
79 generic map(tech,abits,DataSz)
80 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
79 memRAM : IF Mem_use = use_RAM GENERATE
80 SRAM : syncram_2p
81 generic map(tech,abits,DataSz)
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
83 END GENERATE;
81 84 --==================================================================================
82 --RAM0: entity work.RAM_CEL
83 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
85 memCEL : IF Mem_use = use_CEL GENERATE
86 CRAM : RAM_CEL
87 generic map(DataSz,abits)
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
89 END GENERATE;
84 90 --==================================================================================
85 91
86 92 --=============================
87 93 -- Read section
88 94 --=============================
89 95 sREN <= REN or sEmpty;
90 96 sRE <= not sREN;
91 97
92 98 sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else
93 99 '1' when sEmpty = '1' and Wen = '1' else
94 100 '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else
95 101 '0';
96 102
97 103 Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1);
98 104
99 105 process (rclk,rstn)
100 106 begin
101 107 if(rstn='0')then
102 108 Raddr_vect <= (others =>'0');
103 109 sempty <= '1';
104 110 elsif(rclk'event and rclk='1')then
105 111 sEmpty <= sempty_s;
106 112
107 113 if(sREN='0' and sempty = '0')then
108 114 Raddr_vect <= Raddr_vect_s;
109 115 end if;
110 116
111 117 end if;
112 118 end process;
113 119
114 120 --=============================
115 121 -- Write section
116 122 --=============================
117 123 sWEN <= WEN or sFull;
118 124 sWE <= not sWEN;
119 125
120 126 sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else
121 127 '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else
122 128 '1' when sFull = '1' and REN = '1' else
123 129 '0';
124 130
125 131 Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1);
126 132
127 133 process (wclk,rstn)
128 134 begin
129 135 if(rstn='0')then
130 136 Waddr_vect <= (others =>'0');
131 137 sfull <= '0';
132 138 elsif(wclk'event and wclk='1')then
133 139 sfull <= sfull_s;
134 140
135 141 if(sWEN='0' and sfull='0')then
136 142 Waddr_vect <= Waddr_vect_s;
137 143 end if;
138 144
139 145 end if;
140 146 end process;
141 147
142 148
143 149 full <= sFull_s;
144 150 empty <= sEmpty_s;
145 151 waddr <= Waddr_vect;
146 152 raddr <= Raddr_vect;
147 153
148 154 end architecture;
149 155
150 156
151 157
152 158
153 159
154 160
155 161
156 162
157 163
158 164
159 165
160 166
161 167
162 168
163 169
164 170
165 171
166 172
167 173
168 174
169 175
170 176
171 177
172 178
173 179
174 180
Show file before | Show file after | Hide comments
@@ -1,177 +1,163
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 library gaisler;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
32 library techmap;
33 use techmap.gencomp.all;
34
35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36
37 package lpp_memory is
38
39 component APB_FIFO is
40 generic (
41 tech : integer := apa3;
42 pindex : integer := 0;
43 paddr : integer := 0;
44 pmask : integer := 16#fff#;
45 pirq : integer := 0;
46 abits : integer := 8;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
51 R : integer := 1;
52 W : integer := 1
53 );
54 port (
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
71 end component;
72
73
74 component lpp_fifo is
75 generic(
76 tech : integer := 0;
77 Enable_ReUse : std_logic := '0';
78 DataSz : integer range 1 to 32 := 8;
79 abits : integer range 2 to 12 := 8
80 );
81 port(
82 rstn : in std_logic;
83 ReUse : in std_logic; --27/01/12
84 rclk : in std_logic;
85 ren : in std_logic;
86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 empty : out std_logic;
88 raddr : out std_logic_vector(abits-1 downto 0);
89 wclk : in std_logic;
90 wen : in std_logic;
91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 full : out std_logic;
93 waddr : out std_logic_vector(abits-1 downto 0)
94 );
95 end component;
96
97
98 component lppFIFOxN is
99 generic(
100 tech : integer := 0;
101 Data_sz : integer range 1 to 32 := 8;
102 Addr_sz : integer range 1 to 32 := 8;
103 FifoCnt : integer := 1;
104 Enable_ReUse : std_logic := '0'
105 );
106 port(
107 rst : in std_logic;
108 wclk : in std_logic;
109 rclk : in std_logic;
110 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
111 wen : in std_logic_vector(FifoCnt-1 downto 0);
112 ren : in std_logic_vector(FifoCnt-1 downto 0);
113 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
115 full : out std_logic_vector(FifoCnt-1 downto 0);
116 empty : out std_logic_vector(FifoCnt-1 downto 0)
117 );
118 end component;
119
120 component lppFIFOx5 is
121 generic(
122 tech : integer := 0;
123 Data_sz : integer range 1 to 32 := 16;
124 Addr_sz : integer range 2 to 12 := 8;
125 Enable_ReUse : std_logic := '0'
126 );
127 port(
128 rst : in std_logic;
129 wclk : in std_logic;
130 rclk : in std_logic;
131 ReUse : in std_logic_vector(4 downto 0);
132 wen : in std_logic_vector(4 downto 0);
133 ren : in std_logic_vector(4 downto 0);
134 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
135 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
136 full : out std_logic_vector(4 downto 0);
137 empty : out std_logic_vector(4 downto 0)
138 );
139 end component;
140
141 component Bridge is
142 port(
143 clk : in std_logic;
144 raz : in std_logic;
145 EmptyUp : in std_logic;
146 FullDwn : in std_logic;
147 WriteDwn : out std_logic;
148 ReadUp : out std_logic
149 );
150 end component;
151
152 component ssram_plugin is
153 generic (tech : integer := 0);
154 port
155 (
156 clk : in std_logic;
157 mem_ctrlr_o : in memory_out_type;
158 SSRAM_CLK : out std_logic;
159 nBWa : out std_logic;
160 nBWb : out std_logic;
161 nBWc : out std_logic;
162 nBWd : out std_logic;
163 nBWE : out std_logic;
164 nADSC : out std_logic;
165 nADSP : out std_logic;
166 nADV : out std_logic;
167 nGW : out std_logic;
168 nCE1 : out std_logic;
169 CE2 : out std_logic;
170 nCE3 : out std_logic;
171 nOE : out std_logic;
172 MODE : out std_logic;
173 ZZ : out std_logic
174 );
175 end component;
176
177 end;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
30 library gaisler;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
33 library techmap;
34 use techmap.gencomp.all;
35
36 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
37
38 package lpp_memory is
39
40 component APB_FIFO is
41 generic (
42 tech : integer := apa3;
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
54 W : integer := 1
55 );
56 port (
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
73 end component;
74
75
76 component lpp_fifo is
77 generic(
78 tech : integer := 0;
79 Mem_use : integer := use_RAM;
80 Enable_ReUse : std_logic := '0';
81 DataSz : integer range 1 to 32 := 8;
82 abits : integer range 2 to 12 := 8
83 );
84 port(
85 rstn : in std_logic;
86 ReUse : in std_logic; --27/01/12
87 rclk : in std_logic;
88 ren : in std_logic;
89 rdata : out std_logic_vector(DataSz-1 downto 0);
90 empty : out std_logic;
91 raddr : out std_logic_vector(abits-1 downto 0);
92 wclk : in std_logic;
93 wen : in std_logic;
94 wdata : in std_logic_vector(DataSz-1 downto 0);
95 full : out std_logic;
96 waddr : out std_logic_vector(abits-1 downto 0)
97 );
98 end component;
99
100
101 component lppFIFOxN is
102 generic(
103 tech : integer := 0;
104 Mem_use : integer := use_RAM;
105 Data_sz : integer range 1 to 32 := 8;
106 Addr_sz : integer range 1 to 32 := 8;
107 FifoCnt : integer := 1;
108 Enable_ReUse : std_logic := '0'
109 );
110 port(
111 rst : in std_logic;
112 wclk : in std_logic;
113 rclk : in std_logic;
114 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
115 wen : in std_logic_vector(FifoCnt-1 downto 0);
116 ren : in std_logic_vector(FifoCnt-1 downto 0);
117 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
118 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
119 full : out std_logic_vector(FifoCnt-1 downto 0);
120 empty : out std_logic_vector(FifoCnt-1 downto 0)
121 );
122 end component;
123
124 component FillFifo is
125 generic(
126 Data_sz : integer range 1 to 32 := 16;
127 Fifo_cnt : integer range 1 to 8 := 5
128 );
129 port(
130 clk : in std_logic;
131 raz : in std_logic;
132 write : out std_logic_vector(Fifo_cnt-1 downto 0);
133 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
134 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
135 );
136 end component;
137
138 component ssram_plugin is
139 generic (tech : integer := 0);
140 port
141 (
142 clk : in std_logic;
143 mem_ctrlr_o : in memory_out_type;
144 SSRAM_CLK : out std_logic;
145 nBWa : out std_logic;
146 nBWb : out std_logic;
147 nBWc : out std_logic;
148 nBWd : out std_logic;
149 nBWE : out std_logic;
150 nADSC : out std_logic;
151 nADSP : out std_logic;
152 nADV : out std_logic;
153 nGW : out std_logic;
154 nCE1 : out std_logic;
155 CE2 : out std_logic;
156 nCE3 : out std_logic;
157 nOE : out std_logic;
158 MODE : out std_logic;
159 ZZ : out std_logic
160 );
161 end component;
162
163 end;
Show file before | Show file after | Hide comments
@@ -1,303 +1,304
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 LIBRARY lpp;
4 4 USE lpp.lpp_ad_conv.ALL;
5 5 USE lpp.iir_filter.ALL;
6 6 USE lpp.FILTERcfg.ALL;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.lpp_top_lfr_pkg.ALL;
9 9 LIBRARY techmap;
10 10 USE techmap.gencomp.ALL;
11 11
12 12 ENTITY lpp_top_acq IS
13 13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0;
15 Mem_use : integer := use_RAM
15 16 );
16 17 PORT (
17 18 -- ADS7886
18 19 cnv_run : IN STD_LOGIC;
19 20 cnv : OUT STD_LOGIC;
20 21 sck : OUT STD_LOGIC;
21 22 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 23 --
23 24 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 25 cnv_rstn : IN STD_LOGIC;
25 26 --
26 27 clk : IN STD_LOGIC; -- 25 MHz
27 28 rstn : IN STD_LOGIC;
28 29 --
29 30 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 32 --
32 33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 34 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 35 --
35 36 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 37 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 38 --
38 39 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 40 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
40 41 );
41 42 END lpp_top_acq;
42 43
43 44 ARCHITECTURE tb OF lpp_top_acq IS
44 45
45 46 COMPONENT Downsampling
46 47 GENERIC (
47 48 ChanelCount : INTEGER;
48 49 SampleSize : INTEGER;
49 50 DivideParam : INTEGER);
50 51 PORT (
51 52 clk : IN STD_LOGIC;
52 53 rstn : IN STD_LOGIC;
53 54 sample_in_val : IN STD_LOGIC;
54 55 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 56 sample_out_val : OUT STD_LOGIC;
56 57 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 58 END COMPONENT;
58 59
59 60 -----------------------------------------------------------------------------
60 61 CONSTANT ChanelCount : INTEGER := 8;
61 62 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 63 CONSTANT ncycle_cnv : INTEGER := 500;
63 64
64 65 -----------------------------------------------------------------------------
65 66 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 67 SIGNAL sample_val : STD_LOGIC;
67 68 SIGNAL sample_val_delay : STD_LOGIC;
68 69 -----------------------------------------------------------------------------
69 70 CONSTANT Coef_SZ : INTEGER := 9;
70 71 CONSTANT CoefCntPerCel : INTEGER := 6;
71 72 CONSTANT CoefPerCel : INTEGER := 5;
72 73 CONSTANT Cels_count : INTEGER := 5;
73 74
74 75 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 76 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 77 --
77 78 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
78 79 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 80 --
80 81 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
81 82 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 83 -----------------------------------------------------------------------------
83 84 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 85 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 86 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 87 --
87 88 SIGNAL sample_f0_val : STD_LOGIC;
88 89 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 90 -----------------------------------------------------------------------------
90 91 SIGNAL sample_f1_val : STD_LOGIC;
91 92 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 93 --
93 94 SIGNAL sample_f2_val : STD_LOGIC;
94 95 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 96 --
96 97 SIGNAL sample_f3_val : STD_LOGIC;
97 98 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98 99
99 100 BEGIN
100 101
101 102 -- component instantiation
102 103 -----------------------------------------------------------------------------
103 104 DIGITAL_acquisition : AD7688_drvr
104 105 GENERIC MAP (
105 106 ChanelCount => ChanelCount,
106 107 ncycle_cnv_high => ncycle_cnv_high,
107 108 ncycle_cnv => ncycle_cnv)
108 109 PORT MAP (
109 110 cnv_clk => cnv_clk, --
110 111 cnv_rstn => cnv_rstn, --
111 112 cnv_run => cnv_run, --
112 113 cnv => cnv, --
113 114 clk => clk, --
114 115 rstn => rstn, --
115 116 sck => sck, --
116 117 sdo => sdo(ChanelCount-1 DOWNTO 0), --
117 118 sample => sample,
118 119 sample_val => sample_val);
119 120
120 121 -----------------------------------------------------------------------------
121 122
122 123 PROCESS (clk, rstn)
123 124 BEGIN -- PROCESS
124 125 IF rstn = '0' THEN -- asynchronous reset (active low)
125 126 sample_val_delay <= '0';
126 127 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 128 sample_val_delay <= sample_val;
128 129 END IF;
129 130 END PROCESS;
130 131
131 132 -----------------------------------------------------------------------------
132 133 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
133 134 SampleLoop : FOR j IN 0 TO 15 GENERATE
134 135 sample_filter_in(i, j) <= sample(i)(j);
135 136 END GENERATE;
136 137
137 138 sample_filter_in(i, 16) <= sample(i)(15);
138 139 sample_filter_in(i, 17) <= sample(i)(15);
139 140 END GENERATE;
140 141
141 142 coefs_v2 <= CoefsInitValCst_v2;
142 143
143 144 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 145 GENERIC MAP (
145 146 tech => 0,
146 Mem_use => use_RAM,
147 Mem_use => Mem_use,
147 148 Sample_SZ => 18,
148 149 Coef_SZ => Coef_SZ,
149 150 Coef_Nb => 25, -- TODO
150 151 Coef_sel_SZ => 5, -- TODO
151 152 Cels_count => Cels_count,
152 153 ChanelsCount => ChanelCount)
153 154 PORT MAP (
154 155 rstn => rstn,
155 156 clk => clk,
156 157 virg_pos => 7,
157 158 coefs => coefs_v2,
158 159 sample_in_val => sample_val_delay,
159 160 sample_in => sample_filter_in,
160 161 sample_out_val => sample_filter_v2_out_val,
161 162 sample_out => sample_filter_v2_out);
162 163
163 164 -----------------------------------------------------------------------------
164 165 PROCESS (clk, rstn)
165 166 BEGIN -- PROCESS
166 167 IF rstn = '0' THEN -- asynchronous reset (active low)
167 168 sample_filter_v2_out_r_val <= '0';
168 169 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
169 170 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
170 171 sample_filter_v2_out_r(I, J) <= '0';
171 172 END LOOP rst_all_bits;
172 173 END LOOP rst_all_chanel;
173 174 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
174 175 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
175 176 IF sample_filter_v2_out_val = '1' THEN
176 177 sample_filter_v2_out_r <= sample_filter_v2_out;
177 178 END IF;
178 179 END IF;
179 180 END PROCESS;
180 181
181 182 -----------------------------------------------------------------------------
182 183 -- F0 -- @24.576 kHz
183 184 -----------------------------------------------------------------------------
184 185 Downsampling_f0 : Downsampling
185 186 GENERIC MAP (
186 187 ChanelCount => ChanelCount,
187 188 SampleSize => 18,
188 189 DivideParam => 4)
189 190 PORT MAP (
190 191 clk => clk,
191 192 rstn => rstn,
192 193 sample_in_val => sample_filter_v2_out_val ,
193 194 sample_in => sample_filter_v2_out,
194 195 sample_out_val => sample_f0_val,
195 196 sample_out => sample_f0);
196 197
197 198 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
198 199 sample_f0_wdata(I) <= sample_f0(0, I);
199 200 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
200 201 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
201 202 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
202 203 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
203 204 END GENERATE all_bit_sample_f0;
204 205
205 206 sample_f0_wen <= NOT(sample_f0_val) &
206 207 NOT(sample_f0_val) &
207 208 NOT(sample_f0_val) &
208 209 NOT(sample_f0_val) &
209 210 NOT(sample_f0_val);
210 211
211 212 -----------------------------------------------------------------------------
212 213 -- F1 -- @4096 Hz
213 214 -----------------------------------------------------------------------------
214 215 Downsampling_f1 : Downsampling
215 216 GENERIC MAP (
216 217 ChanelCount => ChanelCount,
217 218 SampleSize => 18,
218 219 DivideParam => 6)
219 220 PORT MAP (
220 221 clk => clk,
221 222 rstn => rstn,
222 223 sample_in_val => sample_f0_val ,
223 224 sample_in => sample_f0,
224 225 sample_out_val => sample_f1_val,
225 226 sample_out => sample_f1);
226 227
227 228 sample_f1_wen <= NOT(sample_f1_val) &
228 229 NOT(sample_f1_val) &
229 230 NOT(sample_f1_val) &
230 231 NOT(sample_f1_val) &
231 232 NOT(sample_f1_val);
232 233
233 234 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
234 235 sample_f1_wdata(I) <= sample_f1(0, I);
235 236 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
236 237 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
237 238 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
238 239 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
239 240 END GENERATE all_bit_sample_f1;
240 241
241 242 -----------------------------------------------------------------------------
242 243 -- F2 -- @16 Hz
243 244 -----------------------------------------------------------------------------
244 245 Downsampling_f2 : Downsampling
245 246 GENERIC MAP (
246 247 ChanelCount => ChanelCount,
247 248 SampleSize => 18,
248 249 DivideParam => 256)
249 250 PORT MAP (
250 251 clk => clk,
251 252 rstn => rstn,
252 253 sample_in_val => sample_f1_val ,
253 254 sample_in => sample_f1,
254 255 sample_out_val => sample_f2_val,
255 256 sample_out => sample_f2);
256 257
257 258 sample_f2_wen <= NOT(sample_f2_val) &
258 259 NOT(sample_f2_val) &
259 260 NOT(sample_f2_val) &
260 261 NOT(sample_f2_val) &
261 262 NOT(sample_f2_val);
262 263
263 264 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
264 265 sample_f2_wdata(I) <= sample_f2(0, I);
265 266 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
266 267 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
267 268 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
268 269 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
269 270 END GENERATE all_bit_sample_f2;
270 271
271 272 -----------------------------------------------------------------------------
272 273 -- F3 -- @256 Hz
273 274 -----------------------------------------------------------------------------
274 275 Downsampling_f3 : Downsampling
275 276 GENERIC MAP (
276 277 ChanelCount => ChanelCount,
277 278 SampleSize => 18,
278 279 DivideParam => 96)
279 280 PORT MAP (
280 281 clk => clk,
281 282 rstn => rstn,
282 283 sample_in_val => sample_f0_val ,
283 284 sample_in => sample_f0,
284 285 sample_out_val => sample_f3_val,
285 286 sample_out => sample_f3);
286 287
287 288 sample_f3_wen <= (NOT sample_f3_val) &
288 289 (NOT sample_f3_val) &
289 290 (NOT sample_f3_val) &
290 291 (NOT sample_f3_val) &
291 292 (NOT sample_f3_val);
292 293
293 294 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
294 295 sample_f3_wdata(I) <= sample_f3(0, I);
295 296 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
296 297 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
297 298 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
298 299 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
299 300 END GENERATE all_bit_sample_f3;
300 301
301 302
302 303
303 304 END tb;
Show file before | Show file after | Hide comments
@@ -1,80 +1,81
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_top_lfr_pkg IS
16 16
17 17 COMPONENT lpp_top_acq
18 18 GENERIC(
19 tech : INTEGER := 0
19 tech : INTEGER := 0;
20 Mem_use : integer := use_RAM
20 21 );
21 22 PORT (
22 23 -- ADS7886
23 24 cnv_run : IN STD_LOGIC;
24 25 cnv : OUT STD_LOGIC;
25 26 sck : OUT STD_LOGIC;
26 27 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
27 28 --
28 29 cnv_clk : IN STD_LOGIC; -- 49 MHz
29 30 cnv_rstn : IN STD_LOGIC;
30 31 --
31 32 clk : IN STD_LOGIC; -- 25 MHz
32 33 rstn : IN STD_LOGIC;
33 34 --
34 35 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 36 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 37 --
37 38 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 39 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 40 --
40 41 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 42 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 43 --
43 44 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 46 );
46 47 END COMPONENT;
47 48
48 49 COMPONENT lpp_top_apbreg
49 50 GENERIC (
50 51 pindex : INTEGER;
51 52 paddr : INTEGER;
52 53 pmask : INTEGER;
53 54 pirq : INTEGER);
54 55 PORT (
55 56 HCLK : IN STD_ULOGIC;
56 57 HRESETn : IN STD_ULOGIC;
57 58 apbi : IN apb_slv_in_type;
58 59 apbo : OUT apb_slv_out_type;
59 60 ready_matrix_f0_0 : IN STD_LOGIC;
60 61 ready_matrix_f0_1 : IN STD_LOGIC;
61 62 ready_matrix_f1 : IN STD_LOGIC;
62 63 ready_matrix_f2 : IN STD_LOGIC;
63 64 error_anticipating_empty_fifo : IN STD_LOGIC;
64 65 error_bad_component_error : IN STD_LOGIC;
65 66 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 67 status_ready_matrix_f0_0 : OUT STD_LOGIC;
67 68 status_ready_matrix_f0_1 : OUT STD_LOGIC;
68 69 status_ready_matrix_f1 : OUT STD_LOGIC;
69 70 status_ready_matrix_f2 : OUT STD_LOGIC;
70 71 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
71 72 status_error_bad_component_error : OUT STD_LOGIC;
72 73 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
73 74 config_active_interruption_onError : OUT STD_LOGIC;
74 75 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 76 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 77 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 78 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 79 END COMPONENT;
79 80
80 81 END lpp_top_lfr_pkg; No newline at end of file
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now