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Modif (dma fifo ...)
martin -
r195:2a219a64fd0a martin
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1 -- FillFifo.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FillFifo is
7 generic(
8 Data_sz : integer range 1 to 32 := 16;
9 Fifo_cnt : integer range 1 to 8 := 5
10 );
11 port(
12 clk : in std_logic;
13 raz : in std_logic;
14 write : out std_logic_vector(Fifo_cnt-1 downto 0);
15 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
16 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
17 );
18 end entity;
19
20
21 architecture ar_FillFifo of FillFifo is
22
23 signal i : integer := 0;
24
25 type etat is (eX,e0,e00);
26 signal ect : etat;
27
28 type Tbl is array(natural range <>) of std_logic_vector(Data_sz-1 downto 0);
29
30 --constant TblA : Tbl (0 to 255) := (X"FFFF",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE",X"0000",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",
31 --X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE");
32
33 constant TblA : Tbl (0 to 255) := (X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
34 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
35 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
36
37 constant TblB : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
38 X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
39 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
40
41 constant TblC : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
42 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
43 X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
44
45 constant TblD : Tbl (0 to 255) := (X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
46 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
47 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
48
49 constant TblE : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
50 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
51 X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
52
53 begin
54
55 process(clk,raz)
56 begin
57 if(raz='0')then
58 i <= 0;
59 Write <= (others => '1');
60 Reuse <= (others => '0');
61 ect <= e00;
62
63 elsif(clk'event and clk='1')then
64
65 case ect is
66
67 when e00 =>
68 Write <= (others => '0');
69 ect <= e0;
70
71 when e0 =>
72 if(i=255)then
73 Write <= (others => '1');
74 Reuse <= (others => '1');
75 ect <= eX;
76 else
77 i <= i+1;
78 ect <= e0;
79 end if;
80
81 when eX =>
82 null;
83
84 end case;
85 end if;
86 end process;
87
88 data <= TblE(i) & TblD(i) & TblC(i) & TblB(i) & TblA(i);
89
90 end architecture; No newline at end of file
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@@ -1,93 +1,100
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM_CEL is
27 port( WD : in std_logic_vector(15 downto 0); RD : out
28 std_logic_vector(15 downto 0);WEN, REN : in std_logic;
29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 ) ;
32 end RAM_CEL;
33
34
35
36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"0000");
39 signal RD_int : std_logic_vector(15 downto 0);
40
41 begin
42
43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
44
45
46 process(RWclk,reset)
47 begin
48 if reset = '0' then
49 RD <= (X"0000");
50 rst:for i in 0 to 255 loop
51 RAMarray(i) <= (others => '0');
52 end loop;
53
54 elsif RWclk'event and RWclk = '1' then
55 if REN = '0' then
56 RD <= RD_int;
57 end if;
58
59 if WEN = '0' then
60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
61 end if;
62
63 end if;
64 end process;
65 end ar_RAM_CEL;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity RAM_CEL is
27 generic(DataSz : integer range 1 to 32 := 8;
28 abits : integer range 2 to 12 := 8);
29 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
30 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
31 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
32 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
33 ) ;
34 end RAM_CEL;
35
36
37
38 architecture ar_RAM_CEL of RAM_CEL is
39
40 constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0');
41 constant MAX : integer := 2**(abits);
42
43 type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0);
44
45 signal RAMarray : RAMarrayT:=(others => VectInit);
46 signal RD_int : std_logic_vector(DataSz-1 downto 0);
47
48 begin
49
50 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
51
52
53 process(RWclk,reset)
54 begin
55 if reset = '0' then
56 RD <= VectInit;
57 rst:for i in 0 to MAX-1 loop
58 RAMarray(i) <= (others => '0');
59 end loop;
60
61 elsif RWclk'event and RWclk = '1' then
62 if REN = '0' then
63 RD <= RD_int;
64 end if;
65
66 if WEN = '0' then
67 RAMarray(to_integer(unsigned(WADDR))) <= WD;
68 end if;
69
70 end if;
71 end process;
72 end ar_RAM_CEL;
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Show file before | Show file after | Hide comments
@@ -204,17 +204,15 PACKAGE iir_filter IS
204 204 ) ;
205 205 END COMPONENT;
206 206
207 COMPONENT RAM_CEL
208 GENERIC (
209 Sample_SZ : INTEGER);
210 PORT (
211 WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
212 RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
213 WEN, REN : IN STD_LOGIC;
214 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
215 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
216 RWCLK, RESET : IN STD_LOGIC);
217 END COMPONENT;
207 COMPONENT RAM_CEL is
208 generic(DataSz : integer range 1 to 32 := 8;
209 abits : integer range 2 to 12 := 8);
210 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
211 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
212 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
213 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
214 ) ;
215 end COMPONENT;
218 216
219 217 COMPONENT RAM_CEL_N
220 218 GENERIC (
Show file before | Show file after | Hide comments
@@ -57,21 +57,29 signal Matrix_Param : std_logic_vect
57 57 signal Write_reg : std_logic;
58 58 signal Data_cpt : integer;
59 59 signal MAX : integer;
60 signal pong_reg : std_logic;
60 61
62 type etat is (idle0,idle1,pong0,pong1);
63 signal ect : etat;
61 64
62 65 begin
63 66
64 67 process (clkm,rstn)
65 68 begin
66 69 if(rstn='0')then
70 ect <= idle0;
67 71 Valid <= '0';
72 pong_reg <= '0';
73 header_val <= '0';
74 header(5 downto 0) <= (others => '0');
68 75 Write_reg <= '0';
69 76 Data_cpt <= 0;
70 MAX <= 0;
77 MAX <= 128;
71 78
72 79
73 80 elsif(clkm' event and clkm='1')then
74 81 Write_reg <= Matrix_Write;
82 pong_reg <= pong;
75 83
76 84 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
77 85 MAX <= 128;
@@ -79,33 +87,102 begin
79 87 MAX <= 256;
80 88 end if;
81 89
82 if(Write_reg = '0' and Matrix_Write = '1')then
83 if(Data_cpt = MAX)then
84 Data_cpt <= 0;
85 Valid <= '1';
86 header_val <= '1';
87 else
88 Data_cpt <= Data_cpt + 1;
89 Valid <= '0';
90 end if;
90 -- if(Write_reg = '0' and Matrix_Write = '1')then
91 -- if(Data_cpt = MAX)then
92 -- Data_cpt <= 0;
93 -- Valid <= '1';
94 -- header_val <= '1';
95 -- else
96 -- Data_cpt <= Data_cpt + 1;
97 -- Valid <= '0';
98 -- end if;
99 -- end if;
100
101 if(Write_reg = '0' and Matrix_Write = '1')then
102 Data_cpt <= Data_cpt + 1;
103 Valid <= '0';
104 elsif(Data_cpt = MAX)then
105 Data_cpt <= 0;
106 Valid <= '1';
107 header_val <= '1';
108 else
109 Valid <= '0';
91 110 end if;
92 111
93 if(header_ack = '1')then
94 header_val <= '0';
95 end if;
96
112 -- if(header_ack = '1')then
113 -- header_val <= '0';
114 -- end if;
115
116 -- if(emptyIN = "10")then
117 -- ping <= '0';
118 -- elsif(emptyIN = "01")then
119 -- ping <= '1';
120 -- else
121 -- ping <= ping;
122 -- end if;
123
124
125 case ect is
126
127 when idle0 =>
128 if(header_ack = '1')then
129 header_val <= '0';
130 --if(pong = '1')then
131 ect <= pong0;
132 --elsif(pong = '0')then
133 --ect <= pong1;
134 --end if;
135 end if;
136
137 when pong0 =>
138 header(1 downto 0) <= Matrix_Type;
139 header(5 downto 2) <= Matrix_Param;
140 if(emptyIN(0) = '1')then
141 ect <= idle1;
142 end if;
143
144 when idle1 =>
145 if(header_ack = '1')then
146 header_val <= '0';
147 ect <= pong1;
148 end if;
149
150 when pong1 =>
151 header(1 downto 0) <= Matrix_Type;
152 header(5 downto 2) <= Matrix_Param;
153 if(emptyIN(1) = '1')then
154 ect <= idle0;
155 end if;
156
157 end case;
97 158 end if;
98 159 end process;
99 160
100 161 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
101 162
102 header(1 downto 0) <= Matrix_Type;
103 header(5 downto 2) <= Matrix_Param;
163 --header(1 downto 0) <= Matrix_Type;
164 --header(5 downto 2) <= Matrix_Param;
104 165 header(31 downto 6) <= (others => '0');
105 166
106 dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
107 emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
167 with ect select
168 dataOUT <= dataIN(Data_sz-1 downto 0) when pong0,
169 dataIN(Data_sz-1 downto 0) when idle0,
170 dataIN((2*Data_sz)-1 downto Data_sz) when pong1,
171 dataIN((2*Data_sz)-1 downto Data_sz) when idle1,
172 (others => '0') when others;
108 173
109 RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
174 with ect select
175 emptyOUT <= emptyIN(0) when pong0,
176 emptyIN(0) when idle0,
177 emptyIN(1) when pong1,
178 emptyIN(1) when idle1,
179 '1' when others;
180
181 with ect select
182 RenOUT <= '1' & RenIN when pong0,
183 '1' & RenIN when idle0,
184 RenIN & '1' when pong1,
185 RenIN & '1' when idle1,
186 "11" when others;
110 187
111 188 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -103,6 +103,7 ARCHITECTURE Behavioral OF lpp_dma_ip IS
103 103 -----------------------------------------------------------------------------
104 104 -----------------------------------------------------------------------------
105 105 TYPE state_DMAWriteBurst IS (IDLE,
106 CHECK_COMPONENT_TYPE,
106 107 TRASH_FIFO,
107 108 WAIT_HEADER_ACK,
108 109 SEND_DATA,
@@ -182,8 +183,7 BEGIN
182 183 END PROCESS debug_info;
183 184
184 185
185 matrix_type <= header(1 DOWNTO 0);
186 component_type <= header(5 DOWNTO 2);
186
187 187
188 188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
@@ -191,8 +191,8 BEGIN
191 191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 192 '0';
193 193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
195 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
196 196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 197 '0';
198 198
@@ -208,6 +208,8 BEGIN
208 208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 209 BEGIN -- PROCESS DMAWriteBurst_p
210 210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 matrix_type <= (others => '0');
212 component_type <= (others => '0');
211 213 state <= IDLE;
212 214 header_ack <= '0';
213 215 ready_matrix_f0_0 <= '0';
@@ -216,7 +218,7 BEGIN
216 218 ready_matrix_f2 <= '0';
217 219 error_anticipating_empty_fifo <= '0';
218 220 error_bad_component_error <= '0';
219 component_type_pre <= "1110";
221 component_type_pre <= "0000";
220 222 fifo_ren_trash <= '1';
221 223 component_send <= '0';
222 224 address <= (OTHERS => '0');
@@ -226,7 +228,10 BEGIN
226 228 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
227 229
228 230 CASE state IS
229 WHEN IDLE =>
231 WHEN IDLE =>
232 matrix_type <= header(1 DOWNTO 0);
233 --component_type <= header(5 DOWNTO 2);
234
230 235 ready_matrix_f0_0 <= '0';
231 236 ready_matrix_f0_1 <= '0';
232 237 ready_matrix_f1 <= '0';
@@ -234,9 +239,14 BEGIN
234 239 error_bad_component_error <= '0';
235 240 header_select <= '1';
236 241 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
242 matrix_type <= header(1 DOWNTO 0);
243 component_type <= header(5 DOWNTO 2);
244 component_type_pre <= component_type;
245 state <= CHECK_COMPONENT_TYPE;
246 END IF;
247
248 WHEN CHECK_COMPONENT_TYPE =>
237 249 IF header_check_ok = '1' THEN
238 header_data <= header;
239 component_type_pre <= header(5 DOWNTO 2);
240 250 header_ack <= '1';
241 251 --
242 252 header_send <= '1';
@@ -247,14 +257,15 BEGIN
247 257 --
248 258 state <= WAIT_HEADER_ACK;
249 259 ELSE
250 error_bad_component_error <= '1';
251 component_type_pre <= "1110";
260 error_bad_component_error <= '1';
261 component_type_pre <= "0000";
252 262 header_ack <= '1';
253 263 state <= TRASH_FIFO;
254 264 END IF;
255 END IF;
265
256 266
257 267 WHEN TRASH_FIFO =>
268 header_ack <= '0';
258 269 error_bad_component_error <= '0';
259 270 error_anticipating_empty_fifo <= '0';
260 271 IF fifo_empty = '1' THEN
@@ -263,8 +274,9 BEGIN
263 274 ELSE
264 275 fifo_ren_trash <= '0';
265 276 END IF;
266
277
267 278 WHEN WAIT_HEADER_ACK =>
279 header_ack <= '0';
268 280 header_send <= '0';
269 281 IF header_send_ko = '1' THEN
270 282 state <= TRASH_FIFO;
@@ -279,7 +291,7 BEGIN
279 291 WHEN SEND_DATA =>
280 292 IF fifo_empty = '1' THEN
281 293 state <= IDLE;
282 IF component_type = "1110" THEN
294 IF component_type = "1110" THEN --"1110" -- JC
283 295 CASE matrix_type IS
284 296 WHEN "00" => ready_matrix_f0_0 <= '1';
285 297 WHEN "01" => ready_matrix_f0_1 <= '1';
@@ -287,6 +299,7 BEGIN
287 299 WHEN "11" => ready_matrix_f2 <= '1';
288 300 WHEN OTHERS => NULL;
289 301 END CASE;
302
290 303 END IF;
291 304 ELSE
292 305 component_send <= '1';
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This diff has been collapsed as it changes many lines, (525 lines changed) Show them Hide them
@@ -1,263 +1,264
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 -- APB_FIFO.vhd
23 library ieee;
24 use ieee.std_logic_1164.all;
25 use IEEE.numeric_std.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library grlib;
29 use grlib.amba.all;
30 use grlib.stdlib.all;
31 use grlib.devices.all;
32 library lpp;
33 use lpp.lpp_amba.all;
34 use lpp.apb_devices_list.all;
35 use lpp.lpp_memory.all;
36
37
38 entity APB_FIFO is
39 generic (
40 tech : integer := apa3;
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
50 R : integer := 1;
51 W : integer := 1
52 );
53 port (
54 clk : in std_logic; --! Horloge du composant
55 rst : in std_logic; --! Reset general du composant
56 rclk : in std_logic;
57 wclk : in std_logic;
58 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 );
70 end entity;
71
72 architecture ar_APB_FIFO of APB_FIFO is
73
74 constant REVISION : integer := 1;
75
76 constant pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
78 1 => apb_iobar(paddr, pmask));
79
80 type FIFO_ctrlr_Reg is record
81 FIFO_Ctrl : std_logic_vector(31 downto 0);
82 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
83 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
84 end record;
85
86 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
87 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
88 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
89
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
109
110 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
111 signal regData : fifodatabus;
112 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
113
114 type state_t is (idle,Read);
115 signal fiforeadfsmst : state_t;
116
117 begin
118
119 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
120 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
121 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
122
123
124 Writeint : if W /= 0 generate
125 FIFO_ID(4) <= '1';
126 sWen <= sWen_APB;
127 sReUse <= sReUse_APB;
128 sWclk <= clk;
129 Wrapb: for i in 0 to FifoCnt-1 generate
130 sWDATA(i) <= Rec(i).FIFO_Wdata;
131 end generate;
132 end generate;
133
134 Writeext : if W = 0 generate
135 FIFO_ID(4) <= '0';
136 sWen <= WEN;
137 sReUse <= ReUse;
138 sWclk <= Wclk;
139 Wrext: for i in 0 to FifoCnt-1 generate
140 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
141 end generate;
142 end generate;
143
144 Readint : if R /= 0 generate
145 FIFO_ID(5) <= '1';
146 sRen <= sRen_APB;
147 srclk <= clk;
148 Rdapb: for i in 0 to FifoCnt-1 generate
149 Rec(i).FIFO_Rdata <= sRDATA(i);
150 end generate;
151 end generate;
152
153 Readext : if R = 0 generate
154 FIFO_ID(5) <= '0';
155 sRen <= REN;
156 srclk <= rclk;
157 Drext: for i in 0 to FifoCnt-1 generate
158 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
159 end generate;
160 end generate;
161
162 ctrlregs: for i in 0 to FifoCnt-1 generate
163 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
164 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
165 Rec(i).FIFO_Ctrl(16) <= sFull(i);
166 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
167 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
168 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
169 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
170 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
171 end generate;
172
173 Empty <= sEmpty;
174 Full <= sFull;
175
176 fifos: for i in 0 to FifoCnt-1 generate
177 FIFO0 : lpp_fifo
178 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
179 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
180 end generate;
181
182 process(rst,clk)
183 begin
184 if(rst='0')then
185 rstloop1: for i in 0 to FifoCnt-1 loop
186 Rec(i).FIFO_Wdata <= (others => '0');
187 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
188 sWen_APB(i) <= '1';
189 end loop;
190 elsif(clk'event and clk='1')then
191
192 --APB Write OP
193 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
194 writelp: for i in 0 to FifoCnt-1 loop
195 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
196 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
197 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
198 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
199 sWen_APB(i) <= '0';
200 end if;
201 end loop;
202 else
203 sWen_APB <= (others =>'1');
204 end if;
205
206 --APB Read OP
207 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
208 if(apbi.paddr(abits-1 downto 2)="000000") then
209 PRdata <= FIFO_ID;
210 else
211 readlp: for i in 0 to FifoCnt-1 loop
212 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
213 PRdata <= Rec(i).FIFO_Ctrl;
214 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
215 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
216 end if;
217 end loop;
218 end if;
219 end if;
220 end if;
221
222 apbo.pconfig <= pconfig;
223
224 end process;
225 apbo.prdata <= PRdata when apbi.penable = '1';
226
227 process(rst,clk)
228 begin
229 if(rst='0')then
230 fiforeadfsmst <= idle;
231 rstloop: for i in 0 to FifoCnt-1 loop
232 sRen_APB(i) <= '1';
233 autoloaded(i) <= '1';
234 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
235 end loop;
236 elsif clk'event and clk = '1' then
237 sEmpty_d <= sEmpty;
238 case fiforeadfsmst is
239 when idle =>
240 idlelp: for i in 0 to FifoCnt-1 loop
241 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
242 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
243 autoloaded(i) <= '0';
244 else
245 autoloaded(i) <= '1';
246 end if;
247 sRen_APB(i) <= '0';
248 fiforeadfsmst <= read;
249 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
250 else
251 sRen_APB(i) <= '1';
252 end if;
253 end loop;
254 when read =>
255 sRen_APB <= (others => '1');
256 fiforeadfsmst <= idle;
257 when others =>
258 fiforeadfsmst <= idle;
259 end case;
260 end if;
261 end process;
262
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 -- APB_FIFO.vhd
23 library ieee;
24 use ieee.std_logic_1164.all;
25 use IEEE.numeric_std.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library grlib;
29 use grlib.amba.all;
30 use grlib.stdlib.all;
31 use grlib.devices.all;
32 library lpp;
33 use lpp.lpp_amba.all;
34 use lpp.apb_devices_list.all;
35 use lpp.lpp_memory.all;
36 use lpp.iir_filter.all;
37
38 entity APB_FIFO is
39 generic (
40 tech : integer := apa3;
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
50 Mem_use : integer := use_RAM;
51 R : integer := 1;
52 W : integer := 1
53 );
54 port (
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
71 end entity;
72
73 architecture ar_APB_FIFO of APB_FIFO is
74
75 constant REVISION : integer := 1;
76
77 constant pconfig : apb_config_type := (
78 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
79 1 => apb_iobar(paddr, pmask));
80
81 type FIFO_ctrlr_Reg is record
82 FIFO_Ctrl : std_logic_vector(31 downto 0);
83 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
84 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
85 end record;
86
87 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
88 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
89 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
90
91 signal Rec : FIFO_ctrlr_Reg_Vec;
92 signal PRdata : std_logic_vector(31 downto 0);
93 signal FIFO_ID : std_logic_vector(31 downto 0);
94 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
95 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
97 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
98 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
100 signal sRclk : std_logic;
101 signal sWclk : std_logic;
102 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
104 signal sRDATA : fifodatabus;
105 signal sWDATA : fifodatabus;
106 signal sWADDR : fifoaddressbus;
107 signal sRADDR : fifoaddressbus;
108 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
109 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
110
111 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
112 signal regData : fifodatabus;
113 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
114
115 type state_t is (idle,Read);
116 signal fiforeadfsmst : state_t;
117
118 begin
119
120 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
121 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
122 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
123
124
125 Writeint : if W /= 0 generate
126 FIFO_ID(4) <= '1';
127 sWen <= sWen_APB;
128 sReUse <= sReUse_APB;
129 sWclk <= clk;
130 Wrapb: for i in 0 to FifoCnt-1 generate
131 sWDATA(i) <= Rec(i).FIFO_Wdata;
132 end generate;
133 end generate;
134
135 Writeext : if W = 0 generate
136 FIFO_ID(4) <= '0';
137 sWen <= WEN;
138 sReUse <= ReUse;
139 sWclk <= Wclk;
140 Wrext: for i in 0 to FifoCnt-1 generate
141 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
142 end generate;
143 end generate;
144
145 Readint : if R /= 0 generate
146 FIFO_ID(5) <= '1';
147 sRen <= sRen_APB;
148 srclk <= clk;
149 Rdapb: for i in 0 to FifoCnt-1 generate
150 Rec(i).FIFO_Rdata <= sRDATA(i);
151 end generate;
152 end generate;
153
154 Readext : if R = 0 generate
155 FIFO_ID(5) <= '0';
156 sRen <= REN;
157 srclk <= rclk;
158 Drext: for i in 0 to FifoCnt-1 generate
159 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
160 end generate;
161 end generate;
162
163 ctrlregs: for i in 0 to FifoCnt-1 generate
164 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
165 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
166 Rec(i).FIFO_Ctrl(16) <= sFull(i);
167 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
168 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
169 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
170 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
171 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
172 end generate;
173
174 Empty <= sEmpty;
175 Full <= sFull;
176
177 fifos: for i in 0 to FifoCnt-1 generate
178 FIFO0 : lpp_fifo
179 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
180 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
181 end generate;
182
183 process(rst,clk)
184 begin
185 if(rst='0')then
186 rstloop1: for i in 0 to FifoCnt-1 loop
187 Rec(i).FIFO_Wdata <= (others => '0');
188 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
189 sWen_APB(i) <= '1';
190 end loop;
191 elsif(clk'event and clk='1')then
192
193 --APB Write OP
194 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
195 writelp: for i in 0 to FifoCnt-1 loop
196 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
197 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
198 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
199 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
200 sWen_APB(i) <= '0';
201 end if;
202 end loop;
203 else
204 sWen_APB <= (others =>'1');
205 end if;
206
207 --APB Read OP
208 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
209 if(apbi.paddr(abits-1 downto 2)="000000") then
210 PRdata <= FIFO_ID;
211 else
212 readlp: for i in 0 to FifoCnt-1 loop
213 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
214 PRdata <= Rec(i).FIFO_Ctrl;
215 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
216 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
217 end if;
218 end loop;
219 end if;
220 end if;
221 end if;
222
223 apbo.pconfig <= pconfig;
224
225 end process;
226 apbo.prdata <= PRdata when apbi.penable = '1';
227
228 process(rst,clk)
229 begin
230 if(rst='0')then
231 fiforeadfsmst <= idle;
232 rstloop: for i in 0 to FifoCnt-1 loop
233 sRen_APB(i) <= '1';
234 autoloaded(i) <= '1';
235 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
236 end loop;
237 elsif clk'event and clk = '1' then
238 sEmpty_d <= sEmpty;
239 case fiforeadfsmst is
240 when idle =>
241 idlelp: for i in 0 to FifoCnt-1 loop
242 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
243 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
244 autoloaded(i) <= '0';
245 else
246 autoloaded(i) <= '1';
247 end if;
248 sRen_APB(i) <= '0';
249 fiforeadfsmst <= read;
250 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
251 else
252 sRen_APB(i) <= '1';
253 end if;
254 end loop;
255 when read =>
256 sRen_APB <= (others => '1');
257 fiforeadfsmst <= idle;
258 when others =>
259 fiforeadfsmst <= idle;
260 end case;
261 end if;
262 end process;
263
263 264 end ar_APB_FIFO; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,64 +1,66
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity lppFIFOxN is
31 generic(
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
34 Addr_sz : integer range 1 to 32 := 8;
35 FifoCnt : integer := 1;
36 Enable_ReUse : std_logic := '0'
37 );
38 port(
39 rst : in std_logic;
40 wclk : in std_logic;
41 rclk : in std_logic;
42 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
43 wen : in std_logic_vector(FifoCnt-1 downto 0);
44 ren : in std_logic_vector(FifoCnt-1 downto 0);
45 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
46 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
47 full : out std_logic_vector(FifoCnt-1 downto 0);
48 empty : out std_logic_vector(FifoCnt-1 downto 0)
49 );
50 end entity;
51
52
53 architecture ar_lppFIFOxN of lppFIFOxN is
54
55 begin
56
57 fifos: for i in 0 to FifoCnt-1 generate
58 FIFO0 : lpp_fifo
59 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
60 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
61 end generate;
62
63 end architecture;
64
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
28 library techmap;
29 use techmap.gencomp.all;
30
31 entity lppFIFOxN is
32 generic(
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 1 to 32 := 8;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
39 );
40 port(
41 rst : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
51 );
52 end entity;
53
54
55 architecture ar_lppFIFOxN of lppFIFOxN is
56
57 begin
58
59 fifos: for i in 0 to FifoCnt-1 generate
60 FIFO0 : lpp_fifo
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
63 end generate;
64
65 end architecture;
66
Show file before | Show file after | Hide comments
@@ -31,6 +31,7 use techmap.gencomp.all;
31 31 entity lpp_fifo is
32 32 generic(
33 33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
34 35 Enable_ReUse : std_logic := '0';
35 36 DataSz : integer range 1 to 32 := 8;
36 37 abits : integer range 2 to 12 := 8
@@ -75,12 +76,17 begin
75 76 -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
76 77 -- A l'inverse de RAM_CEL !!!
77 78 --==================================================================================
78 SRAM : syncram_2p
79 generic map(tech,abits,DataSz)
80 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
79 memRAM : IF Mem_use = use_RAM GENERATE
80 SRAM : syncram_2p
81 generic map(tech,abits,DataSz)
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
83 END GENERATE;
81 84 --==================================================================================
82 --RAM0: entity work.RAM_CEL
83 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
85 memCEL : IF Mem_use = use_CEL GENERATE
86 CRAM : RAM_CEL
87 generic map(DataSz,abits)
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
89 END GENERATE;
84 90 --==================================================================================
85 91
86 92 --=============================
Show file before | Show file after | Hide comments
@@ -1,177 +1,163
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 library gaisler;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
32 library techmap;
33 use techmap.gencomp.all;
34
35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36
37 package lpp_memory is
38
39 component APB_FIFO is
40 generic (
41 tech : integer := apa3;
42 pindex : integer := 0;
43 paddr : integer := 0;
44 pmask : integer := 16#fff#;
45 pirq : integer := 0;
46 abits : integer := 8;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
51 R : integer := 1;
52 W : integer := 1
53 );
54 port (
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
71 end component;
72
73
74 component lpp_fifo is
75 generic(
76 tech : integer := 0;
77 Enable_ReUse : std_logic := '0';
78 DataSz : integer range 1 to 32 := 8;
79 abits : integer range 2 to 12 := 8
80 );
81 port(
82 rstn : in std_logic;
83 ReUse : in std_logic; --27/01/12
84 rclk : in std_logic;
85 ren : in std_logic;
86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 empty : out std_logic;
88 raddr : out std_logic_vector(abits-1 downto 0);
89 wclk : in std_logic;
90 wen : in std_logic;
91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 full : out std_logic;
93 waddr : out std_logic_vector(abits-1 downto 0)
94 );
95 end component;
96
97
98 component lppFIFOxN is
99 generic(
100 tech : integer := 0;
101 Data_sz : integer range 1 to 32 := 8;
102 Addr_sz : integer range 1 to 32 := 8;
103 FifoCnt : integer := 1;
104 Enable_ReUse : std_logic := '0'
105 );
106 port(
107 rst : in std_logic;
108 wclk : in std_logic;
109 rclk : in std_logic;
110 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
111 wen : in std_logic_vector(FifoCnt-1 downto 0);
112 ren : in std_logic_vector(FifoCnt-1 downto 0);
113 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
115 full : out std_logic_vector(FifoCnt-1 downto 0);
116 empty : out std_logic_vector(FifoCnt-1 downto 0)
117 );
118 end component;
119
120 component lppFIFOx5 is
121 generic(
122 tech : integer := 0;
123 Data_sz : integer range 1 to 32 := 16;
124 Addr_sz : integer range 2 to 12 := 8;
125 Enable_ReUse : std_logic := '0'
126 );
127 port(
128 rst : in std_logic;
129 wclk : in std_logic;
130 rclk : in std_logic;
131 ReUse : in std_logic_vector(4 downto 0);
132 wen : in std_logic_vector(4 downto 0);
133 ren : in std_logic_vector(4 downto 0);
134 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
135 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
136 full : out std_logic_vector(4 downto 0);
137 empty : out std_logic_vector(4 downto 0)
138 );
139 end component;
140
141 component Bridge is
142 port(
143 clk : in std_logic;
144 raz : in std_logic;
145 EmptyUp : in std_logic;
146 FullDwn : in std_logic;
147 WriteDwn : out std_logic;
148 ReadUp : out std_logic
149 );
150 end component;
151
152 component ssram_plugin is
153 generic (tech : integer := 0);
154 port
155 (
156 clk : in std_logic;
157 mem_ctrlr_o : in memory_out_type;
158 SSRAM_CLK : out std_logic;
159 nBWa : out std_logic;
160 nBWb : out std_logic;
161 nBWc : out std_logic;
162 nBWd : out std_logic;
163 nBWE : out std_logic;
164 nADSC : out std_logic;
165 nADSP : out std_logic;
166 nADV : out std_logic;
167 nGW : out std_logic;
168 nCE1 : out std_logic;
169 CE2 : out std_logic;
170 nCE3 : out std_logic;
171 nOE : out std_logic;
172 MODE : out std_logic;
173 ZZ : out std_logic
174 );
175 end component;
176
177 end;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
30 library gaisler;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
33 library techmap;
34 use techmap.gencomp.all;
35
36 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
37
38 package lpp_memory is
39
40 component APB_FIFO is
41 generic (
42 tech : integer := apa3;
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
54 W : integer := 1
55 );
56 port (
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
73 end component;
74
75
76 component lpp_fifo is
77 generic(
78 tech : integer := 0;
79 Mem_use : integer := use_RAM;
80 Enable_ReUse : std_logic := '0';
81 DataSz : integer range 1 to 32 := 8;
82 abits : integer range 2 to 12 := 8
83 );
84 port(
85 rstn : in std_logic;
86 ReUse : in std_logic; --27/01/12
87 rclk : in std_logic;
88 ren : in std_logic;
89 rdata : out std_logic_vector(DataSz-1 downto 0);
90 empty : out std_logic;
91 raddr : out std_logic_vector(abits-1 downto 0);
92 wclk : in std_logic;
93 wen : in std_logic;
94 wdata : in std_logic_vector(DataSz-1 downto 0);
95 full : out std_logic;
96 waddr : out std_logic_vector(abits-1 downto 0)
97 );
98 end component;
99
100
101 component lppFIFOxN is
102 generic(
103 tech : integer := 0;
104 Mem_use : integer := use_RAM;
105 Data_sz : integer range 1 to 32 := 8;
106 Addr_sz : integer range 1 to 32 := 8;
107 FifoCnt : integer := 1;
108 Enable_ReUse : std_logic := '0'
109 );
110 port(
111 rst : in std_logic;
112 wclk : in std_logic;
113 rclk : in std_logic;
114 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
115 wen : in std_logic_vector(FifoCnt-1 downto 0);
116 ren : in std_logic_vector(FifoCnt-1 downto 0);
117 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
118 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
119 full : out std_logic_vector(FifoCnt-1 downto 0);
120 empty : out std_logic_vector(FifoCnt-1 downto 0)
121 );
122 end component;
123
124 component FillFifo is
125 generic(
126 Data_sz : integer range 1 to 32 := 16;
127 Fifo_cnt : integer range 1 to 8 := 5
128 );
129 port(
130 clk : in std_logic;
131 raz : in std_logic;
132 write : out std_logic_vector(Fifo_cnt-1 downto 0);
133 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
134 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
135 );
136 end component;
137
138 component ssram_plugin is
139 generic (tech : integer := 0);
140 port
141 (
142 clk : in std_logic;
143 mem_ctrlr_o : in memory_out_type;
144 SSRAM_CLK : out std_logic;
145 nBWa : out std_logic;
146 nBWb : out std_logic;
147 nBWc : out std_logic;
148 nBWd : out std_logic;
149 nBWE : out std_logic;
150 nADSC : out std_logic;
151 nADSP : out std_logic;
152 nADV : out std_logic;
153 nGW : out std_logic;
154 nCE1 : out std_logic;
155 CE2 : out std_logic;
156 nCE3 : out std_logic;
157 nOE : out std_logic;
158 MODE : out std_logic;
159 ZZ : out std_logic
160 );
161 end component;
162
163 end;
Show file before | Show file after | Hide comments
@@ -11,7 +11,8 USE techmap.gencomp.ALL;
11 11
12 12 ENTITY lpp_top_acq IS
13 13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0;
15 Mem_use : integer := use_RAM
15 16 );
16 17 PORT (
17 18 -- ADS7886
@@ -143,7 +144,7 BEGIN
143 144 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 145 GENERIC MAP (
145 146 tech => 0,
146 Mem_use => use_RAM,
147 Mem_use => Mem_use,
147 148 Sample_SZ => 18,
148 149 Coef_SZ => Coef_SZ,
149 150 Coef_Nb => 25, -- TODO
Show file before | Show file after | Hide comments
@@ -16,7 +16,8 PACKAGE lpp_top_lfr_pkg IS
16 16
17 17 COMPONENT lpp_top_acq
18 18 GENERIC(
19 tech : INTEGER := 0
19 tech : INTEGER := 0;
20 Mem_use : integer := use_RAM
20 21 );
21 22 PORT (
22 23 -- ADS7886
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