HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r467:10ba15a05d8c

LFR-em 1.1.35

pellion -

r467:10ba15a05d8c (LFR-EM) WFP_MS-1-1-35 JC

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r467:10ba15a05d8c

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designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;      -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1 : IN  STD_ULOGIC;            -- DSU rx data
                 TAG3 : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2 : IN  STD_ULOGIC;            -- UART1 rx data
                 TAG4 : OUT STD_ULOGIC;            -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0 : OUT   STD_LOGIC;
                 nSRAM_BE1 : OUT   STD_LOGIC;
                 nSRAM_BE2 : OUT   STD_LOGIC;
                 nSRAM_BE3 : OUT   STD_LOGIC;
                 nSRAM_WE  : OUT   STD_LOGIC;
                 nSRAM_CE  : OUT   STD_LOGIC;
                 nSRAM_OE  : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din  : IN  STD_LOGIC;
                 spw1_sin  : IN  STD_LOGIC;
                 spw1_dout : OUT STD_LOGIC;
                 spw1_sout : OUT STD_LOGIC;
                 spw2_din  : IN  STD_LOGIC;
                 spw2_sin  : IN  STD_LOGIC;
                 spw2_dout : OUT STD_LOGIC;
                 spw2_sout : OUT STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT STD_LOGIC;
                 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT STD_LOGIC;
                 ADC_data       : IN  STD_LOGIC_VECTOR(13 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8 : OUT STD_LOGIC;
                 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
               SIGNAL LFR_soft_rstn  : STD_LOGIC;
               SIGNAL LFR_rstn       : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                 -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn,
                   errorn    => OPEN,
                   ahbrxd    => TAG1,
                   ahbtxd    => TAG3,
                   urxd1     => TAG2,
                   utxd1     => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE,
                   nSRAM_OE  => nSRAM_OE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_time_management_1 : apb_lfr_time_management
                 GENERIC MAP (
                   pindex => 6,
                   paddr  => 6,
                   pmask  => 16#fff#,
                   FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz     => clk_25,
                   clk24_576MHz => clk_24,           -- 49.152MHz/2
                   resetn       => rstn,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                   coarse_time  => coarse_time,
                   fine_time    => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,      -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010122")  -- aa.bb.cc version
+                  top_lfr_version        => X"010123")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw);--,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample: FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 8,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH,
                   sample     => sample,
                   sample_val => sample_val);
               --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
               --  GENERIC MAP (
               --    ChanelCount     => 8,
               --    ncycle_cnv_high => 40,            -- TODO : 79
               --    ncycle_cnv      => 250)           -- TODO : 500
               --  PORT MAP (
               --    cnv_clk    => clk_24,             -- TODO : 49.152
               --    cnv_rstn   => rstn,               -- ok
               --    cnv        => ADC_smpclk_s,         -- ok
               --    clk        => clk_25,             -- ok
               --    rstn       => rstn,               -- ok
               --    ADC_data   => ADC_data,           -- ok
               --    ADC_nOE    => ADC_OEB_bar_CH,     -- ok
               --    sample     => sample,             -- ok
               --    sample_val => sample_val);        -- ok
               ADC_smpclk <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
             END beh;

designs/MINI-LFR_WFP_MS/testbench.vhd +12 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             use IEEE.std_logic_textio.all;
             LIBRARY STD;
             use std.textio.all;
             LIBRARY grlib;
             USE grlib.stdlib.ALL;
             LIBRARY gaisler;
             USE gaisler.libdcom.ALL;
             USE gaisler.sim.ALL;
             USE gaisler.jtagtst.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY lpp;
             USE lpp.lpp_sim_pkg.ALL;
+            USE lpp.lpp_lfr_sim_pkg.ALL;
             USE lpp.lpp_lfr_apbreg_pkg.ALL;
             USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
             ENTITY testbench IS
             END;
             ARCHITECTURE behav OF testbench IS
               COMPONENT MINI_LFR_top
                 PORT (
                   clk_50       : IN    STD_LOGIC;
                   clk_49       : IN    STD_LOGIC;
                   reset        : IN    STD_LOGIC;
                   BP0          : IN    STD_LOGIC;
                   BP1          : IN    STD_LOGIC;
                   LED0         : OUT   STD_LOGIC;
                   LED1         : OUT   STD_LOGIC;
                   LED2         : OUT   STD_LOGIC;
                   TXD1         : IN    STD_LOGIC;
                   RXD1         : OUT   STD_LOGIC;
                   nCTS1        : OUT   STD_LOGIC;
                   nRTS1        : IN    STD_LOGIC;
                   TXD2         : IN    STD_LOGIC;
                   RXD2         : OUT   STD_LOGIC;
                   nCTS2        : OUT   STD_LOGIC;
                   nDTR2        : IN    STD_LOGIC;
                   nRTS2        : IN    STD_LOGIC;
                   nDCD2        : OUT   STD_LOGIC;
                   IO0          : INOUT STD_LOGIC;
                   IO1          : INOUT STD_LOGIC;
                   IO2          : INOUT STD_LOGIC;
                   IO3          : INOUT STD_LOGIC;
                   IO4          : INOUT STD_LOGIC;
                   IO5          : INOUT STD_LOGIC;
                   IO6          : INOUT STD_LOGIC;
                   IO7          : INOUT STD_LOGIC;
                   IO8          : INOUT STD_LOGIC;
                   IO9          : INOUT STD_LOGIC;
                   IO10         : INOUT STD_LOGIC;
                   IO11         : INOUT STD_LOGIC;
                   SPW_EN       : OUT   STD_LOGIC;
                   SPW_NOM_DIN  : IN    STD_LOGIC;
                   SPW_NOM_SIN  : IN    STD_LOGIC;
                   SPW_NOM_DOUT : OUT   STD_LOGIC;
                   SPW_NOM_SOUT : OUT   STD_LOGIC;
                   SPW_RED_DIN  : IN    STD_LOGIC;
                   SPW_RED_SIN  : IN    STD_LOGIC;
                   SPW_RED_DOUT : OUT   STD_LOGIC;
                   SPW_RED_SOUT : OUT   STD_LOGIC;
                   ADC_nCS      : OUT   STD_LOGIC;
                   ADC_CLK      : OUT   STD_LOGIC;
                   ADC_SDO      : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
                   SRAM_nWE     : OUT   STD_LOGIC;
                   SRAM_CE      : OUT   STD_LOGIC;
                   SRAM_nOE     : OUT   STD_LOGIC;
                   SRAM_nBE     : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                   SRAM_A       : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                   SRAM_DQ      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               SIGNAL clk_50 : STD_LOGIC := '0';
               SIGNAL clk_49 : STD_LOGIC := '0';
               SIGNAL reset        : STD_LOGIC;
               SIGNAL BP0          : STD_LOGIC;
               SIGNAL BP1          : STD_LOGIC;
               SIGNAL LED0         : STD_LOGIC;
               SIGNAL LED1         : STD_LOGIC;
               SIGNAL LED2         : STD_LOGIC;
               SIGNAL TXD1         : STD_LOGIC;
               SIGNAL RXD1         : STD_LOGIC;
               SIGNAL nCTS1        : STD_LOGIC;
               SIGNAL nRTS1        : STD_LOGIC;
               SIGNAL TXD2         : STD_LOGIC;
               SIGNAL RXD2         : STD_LOGIC;
               SIGNAL nCTS2        : STD_LOGIC;
               SIGNAL nDTR2        : STD_LOGIC;
               SIGNAL nRTS2        : STD_LOGIC;
               SIGNAL nDCD2        : STD_LOGIC;
               SIGNAL IO0          : STD_LOGIC;
               SIGNAL IO1          : STD_LOGIC;
               SIGNAL IO2          : STD_LOGIC;
               SIGNAL IO3          : STD_LOGIC;
               SIGNAL IO4          : STD_LOGIC;
               SIGNAL IO5          : STD_LOGIC;
               SIGNAL IO6          : STD_LOGIC;
               SIGNAL IO7          : STD_LOGIC;
               SIGNAL IO8          : STD_LOGIC;
               SIGNAL IO9          : STD_LOGIC;
               SIGNAL IO10         : STD_LOGIC;
               SIGNAL IO11         : STD_LOGIC;
               SIGNAL SPW_EN       : STD_LOGIC;
               SIGNAL SPW_NOM_DIN  : STD_LOGIC;
               SIGNAL SPW_NOM_SIN  : STD_LOGIC;
               SIGNAL SPW_NOM_DOUT : STD_LOGIC;
               SIGNAL SPW_NOM_SOUT : STD_LOGIC;
               SIGNAL SPW_RED_DIN  : STD_LOGIC;
               SIGNAL SPW_RED_SIN  : STD_LOGIC;
               SIGNAL SPW_RED_DOUT : STD_LOGIC;
               SIGNAL SPW_RED_SOUT : STD_LOGIC;
               SIGNAL ADC_nCS      : STD_LOGIC;
               SIGNAL ADC_CLK      : STD_LOGIC;
               SIGNAL ADC_SDO      : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL SRAM_nWE     : STD_LOGIC;
               SIGNAL SRAM_CE      : STD_LOGIC;
               SIGNAL SRAM_nOE     : STD_LOGIC;
               SIGNAL SRAM_nBE     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL SRAM_A       : STD_LOGIC_VECTOR(19 DOWNTO 0);
               SIGNAL SRAM_DQ      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               CONSTANT ADDR_BASE_LFR            : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
               CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
               CONSTANT ADDR_BASE_GPIO           : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
               SIGNAL message_simu : STRING(1 TO 15) := "---------------";
+              SIGNAL data_message : STRING(1 TO 15) := "---------------";
+              SIGNAL data_read    : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
             BEGIN
               -----------------------------------------------------------------------------
               -- TB
               -----------------------------------------------------------------------------
               PROCESS
                 CONSTANT txp : TIME := 320 ns;
+                VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
               BEGIN  -- PROCESS
                 TXD1  <= '1';
                 reset <= '0';
                 WAIT FOR 500 ns;
                 reset <= '1';
                 WAIT FOR 10000 ns;
                 message_simu <= "0 - UART init  ";
                 UART_INIT(TXD1,txp);
                 message_simu <= "1 - UART test  ";
                 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
                 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
                 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
+                UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
+                data_read    <= data_read_v;
+                data_message <= "GPIO_data_write";
                 -- UNSET the LFR reset
                 message_simu <= "2 - LFR UNRESET";
-                UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL   , X"00000000");
+                UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
-                UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
+                --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL   , X"00000000");
+                --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
                 --
                 message_simu <= "3 - LFR CONFIG ";
                 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
                 WAIT;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- CLOCK
               -----------------------------------------------------------------------------
               clk_50    <= NOT clk_50 AFTER 5 ns;
               clk_49    <= NOT clk_49 AFTER 10172 ps;
               -----------------------------------------------------------------------------
               -- DON'T CARE
               -----------------------------------------------------------------------------
               BP0   <= '0';
               BP1   <= '0';
               nRTS1 <= '0' ;
               TXD2  <= '1';
               nRTS2 <= '1';
               nDTR2 <= '1';
               SPW_NOM_DIN  <= '1';
               SPW_NOM_SIN  <= '1';
               SPW_RED_DIN  <= '1';
               SPW_RED_SIN  <= '1';
               ADC_SDO      <= x"AA";
               SRAM_DQ      <= (OTHERS => 'Z');
               --IO0          <= 'Z';
               --IO1          <= 'Z';
               --IO2          <= 'Z';
               --IO3          <= 'Z';
               --IO4          <= 'Z';
               --IO5          <= 'Z';
               --IO6          <= 'Z';
               --IO7          <= 'Z';
               --IO8          <= 'Z';
               --IO9          <= 'Z';
               --IO10         <= 'Z';
               --IO11         <= 'Z';
               -----------------------------------------------------------------------------
               -- DUT
               -----------------------------------------------------------------------------
               MINI_LFR_top_1: MINI_LFR_top
                 PORT MAP (
                   clk_50       => clk_50,
                   clk_49       => clk_49,
                   reset        => reset,
                   BP0          => BP0,
                   BP1          => BP1,
                   LED0         => LED0,
                   LED1         => LED1,
                   LED2         => LED2,
                   TXD1         => TXD1,
                   RXD1         => RXD1,
                   nCTS1        => nCTS1,
                   nRTS1        => nRTS1,
                   TXD2         => TXD2,
                   RXD2         => RXD2,
                   nCTS2        => nCTS2,
                   nDTR2        => nDTR2,
                   nRTS2        => nRTS2,
                   nDCD2        => nDCD2,
                   IO0          => IO0,
                   IO1          => IO1,
                   IO2          => IO2,
                   IO3          => IO3,
                   IO4          => IO4,
                   IO5          => IO5,
                   IO6          => IO6,
                   IO7          => IO7,
                   IO8          => IO8,
                   IO9          => IO9,
                   IO10         => IO10,
                   IO11         => IO11,
                   SPW_EN       => SPW_EN,
                   SPW_NOM_DIN  => SPW_NOM_DIN,
                   SPW_NOM_SIN  => SPW_NOM_SIN,
                   SPW_NOM_DOUT => SPW_NOM_DOUT,
                   SPW_NOM_SOUT => SPW_NOM_SOUT,
                   SPW_RED_DIN  => SPW_RED_DIN,
                   SPW_RED_SIN  => SPW_RED_SIN,
                   SPW_RED_DOUT => SPW_RED_DOUT,
                   SPW_RED_SOUT => SPW_RED_SOUT,
                   ADC_nCS      => ADC_nCS,
                   ADC_CLK      => ADC_CLK,
                   ADC_SDO      => ADC_SDO,
                   SRAM_nWE     => SRAM_nWE,
                   SRAM_CE      => SRAM_CE,
                   SRAM_nOE     => SRAM_nOE,
                   SRAM_nBE     => SRAM_nBE,
                   SRAM_A       => SRAM_A,
                   SRAM_DQ      => SRAM_DQ);
             END;

lib/lpp/lpp_dma/DMA_SubSystem.vhd +3 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
-            USE lpp.lpp_waveform_pkg.ALL;
+            --USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
-            USE lpp.lpp_top_lfr_pkg.ALL;
+            --USE lpp.lpp_top_lfr_pkg.ALL;
-            USE lpp.lpp_lfr_pkg.ALL;
+            --USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY DMA_SubSystem IS
               GENERIC (
                 hindex : INTEGER := 2);
               PORT (
                 clk                            : IN  STD_LOGIC;
                 rstn                           : IN  STD_LOGIC;
                 run                            : IN  STD_LOGIC;
                 -- AHB
                 ahbi                           : IN  AHB_Mst_In_Type;
                 ahbo                           : OUT AHB_Mst_Out_Type;
                 ---------------------------------------------------------------------------
                 fifo_burst_valid               : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 fifo_data                      : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                 fifo_ren                       : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 buffer_new                     : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 buffer_addr                    : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                 buffer_length                  : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
                 buffer_full                    : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 buffer_full_err                : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 grant_error : OUT STD_LOGIC                               --
                 );
             END DMA_SubSystem;
             ARCHITECTURE beh OF DMA_SubSystem IS
               COMPONENT DMA_SubSystem_GestionBuffer
                 GENERIC (
                   BUFFER_ADDR_SIZE   : INTEGER;
                   BUFFER_LENGTH_SIZE : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   buffer_new      : IN  STD_LOGIC;
                   buffer_addr     : IN  STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
                   buffer_length   : IN  STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
                   buffer_full     : OUT STD_LOGIC;
                   buffer_full_err : OUT STD_LOGIC;
                   burst_send      : IN  STD_LOGIC;
                   burst_addr      : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_Arbiter
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   data_burst_valid       : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
               END COMPONENT;
               COMPONENT DMA_SubSystem_MUX
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   run             : IN  STD_LOGIC;
                   fifo_grant      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_data       : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_address    : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
                   fifo_ren        : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   dma_send        : OUT STD_LOGIC;
                   dma_valid_burst : OUT STD_LOGIC;
                   dma_address     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_ren         : IN  STD_LOGIC;
                   dma_done        : IN  STD_LOGIC;
                   grant_error     : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               SIGNAL dma_send        : STD_LOGIC;
               SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_done        : STD_LOGIC;
               SIGNAL dma_ren         : STD_LOGIC;
               SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL burst_send      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_grant      :  STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_address    :   STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);  --
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
                 GENERIC MAP (
                   tech   => inferred,
                   hindex => hindex)
                 PORT MAP (
                   HCLK           => clk,
                   HRESETn        => rstn,
                   run            => run,
                   AHB_Master_In  => ahbi,
                   AHB_Master_Out => ahbo,
                   send        => dma_send,
                   valid_burst => dma_valid_burst,
                   done        => dma_done,
                   ren         => dma_ren,
                   address     => dma_address,
                   data        => dma_data);
               -----------------------------------------------------------------------------
               -- RoundRobin Selection Channel For DMA
               -----------------------------------------------------------------------------
               DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   data_burst_valid       => fifo_burst_valid,
                   data_burst_valid_grant => fifo_grant);
               -----------------------------------------------------------------------------
               -- Mux between the channel from Waveform Picker and Spectral Matrix
               -----------------------------------------------------------------------------
               DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
                 PORT MAP (
                   clk             => clk,
                   rstn            => rstn,
                   run             => run,
                   fifo_grant      => fifo_grant,
                   fifo_data       => fifo_data,
                   fifo_address    => fifo_address,
                   fifo_ren        => fifo_ren,
                   fifo_burst_done => burst_send,
                   dma_send        => dma_send,
                   dma_valid_burst => dma_valid_burst,
                   dma_address     => dma_address,
                   dma_data        => dma_data,
                   dma_ren         => dma_ren,
                   dma_done        => dma_done,
                   grant_error     => grant_error);
               -----------------------------------------------------------------------------
               -- GEN ADDR
               -----------------------------------------------------------------------------
               all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
                 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
                   GENERIC MAP (
                     BUFFER_ADDR_SIZE   => 32,
                     BUFFER_LENGTH_SIZE => 26)
                   PORT MAP (
                     clk  => clk,
                     rstn => rstn,
                     run  => run,
                     buffer_new      => buffer_new(I),
                     buffer_addr     => buffer_addr(32*(I+1)-1 DOWNTO I*32),
                     buffer_length   => buffer_length(26*(I+1)-1 DOWNTO I*26),
                     buffer_full     => buffer_full(I),
                     buffer_full_err => buffer_full_err(I),
                     burst_send => burst_send(I),
                     burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
                     );
               END GENERATE all_buffer;
             END beh;

lib/lpp/lpp_dma/DMA_SubSystem_Arbiter.vhd +3 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
-            USE lpp.lpp_waveform_pkg.ALL;
+            --USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
-            USE lpp.lpp_top_lfr_pkg.ALL;
+            --USE lpp.lpp_top_lfr_pkg.ALL;
-            USE lpp.lpp_lfr_pkg.ALL;
+            --USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY DMA_SubSystem_Arbiter IS
               PORT (
                 clk                            : IN  STD_LOGIC;
                 rstn                           : IN  STD_LOGIC;
                 run                            : IN  STD_LOGIC;
                 --
                 data_burst_valid         : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 data_burst_valid_grant   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
                 );
             END DMA_SubSystem_Arbiter;
             ARCHITECTURE beh OF DMA_SubSystem_Arbiter IS
               SIGNAL data_burst_valid_r : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- REG the burst valid signal
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_burst_valid_r <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF run = '1' THEN
                     data_burst_valid_r <= data_burst_valid;
                   ELSE
                     data_burst_valid_r <= (OTHERS => '0');
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- ARBITER Between all the "WAVEFORM_PICKER" channel
               -----------------------------------------------------------------------------
               RR_Arbiter_4_1 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => data_burst_valid_r(3 DOWNTO 0),
                   out_grant => dma_rr_grant_s);
               dma_rr_valid_ms(0) <= data_burst_valid_r(4);--data_ms_valid OR data_ms_valid_burst;
               dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
               dma_rr_valid_ms(2) <= '0';
               dma_rr_valid_ms(3) <= '0';
               -----------------------------------------------------------------------------
               -- ARBITER Between all the "WAVEFORM_PICKER" and "SPECTRAL MATRIX"
               -----------------------------------------------------------------------------
               RR_Arbiter_4_2 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid_ms,
                   out_grant => dma_rr_grant_ms);
               data_burst_valid_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
             END beh;

lib/lpp/lpp_dma/DMA_SubSystem_MUX.vhd +3 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
-            USE lpp.lpp_waveform_pkg.ALL;
+            --USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
-            USE lpp.lpp_top_lfr_pkg.ALL;
+            --USE lpp.lpp_top_lfr_pkg.ALL;
-            USE lpp.lpp_lfr_pkg.ALL;
+            --USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY DMA_SubSystem_MUX IS
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 run             : IN  STD_LOGIC;
                 --
                 fifo_grant      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 fifo_data       : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);  --
                 fifo_address    : IN  STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);  --
                 fifo_ren        : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);       --
                 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --
                 dma_send        : OUT STD_LOGIC;
                 dma_valid_burst : OUT STD_LOGIC;                          --
                 dma_address     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);      --
                 dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);      --
                 dma_ren         : IN  STD_LOGIC;                          --
                 dma_done        : IN  STD_LOGIC;                          --
                 --
                 grant_error : OUT STD_LOGIC                               --
                 );
             END DMA_SubSystem_MUX;
             ARCHITECTURE beh OF DMA_SubSystem_MUX IS
               SIGNAL channel_ongoing     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL one_grant           : STD_LOGIC;
               SIGNAL more_than_one_grant : STD_LOGIC;
             BEGIN
               one_grant           <= '0' WHEN fifo_grant = "00000" ELSE '1';
               more_than_one_grant <= '0' WHEN fifo_grant = "00000" OR
                                               fifo_grant = "00001" OR
                                               fifo_grant = "00010" OR
                                               fifo_grant = "00100" OR
                                               fifo_grant = "01000" OR
                                               fifo_grant = "10000" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   channel_ongoing <= (OTHERS => '0');
                   fifo_burst_done <= (OTHERS => '0');
                   dma_send        <= '0';
                   dma_valid_burst <= '0';
                   grant_error     <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   grant_error     <= '0';
                   IF run = '1' THEN
                     IF dma_done = '1' THEN
                       fifo_burst_done  <= channel_ongoing;
                     ELSE
                       fifo_burst_done  <= (OTHERS => '0');
                     END IF;
                     IF channel_ongoing = "00000" OR dma_done = '1' THEN
                       channel_ongoing <= fifo_grant;
                       grant_error     <= more_than_one_grant;
                       dma_valid_burst <= one_grant;
                       dma_send        <= one_grant;
                     ELSE
                       dma_send <= '0';
                     END IF;
                   ELSE
                     channel_ongoing <= (OTHERS => '0');
                     fifo_burst_done <= (OTHERS => '0');
                     dma_send        <= '0';
                     dma_valid_burst <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               -------------------------------------------------------------------------
               all_channel : FOR I IN 4 DOWNTO 0 GENERATE
                 fifo_ren(I) <= dma_ren WHEN channel_ongoing(I) = '1' ELSE '1';
               END GENERATE all_channel;
               dma_data <= fifo_data(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
                           fifo_data(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
                           fifo_data(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
                           fifo_data(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
                           fifo_data(32*5-1 DOWNTO 32*4);  --WHEN channel_ongoing(4) = '1' ELSE
               dma_address <= fifo_address(32*1-1 DOWNTO 32*0) WHEN channel_ongoing(0) = '1' ELSE
                              fifo_address(32*2-1 DOWNTO 32*1) WHEN channel_ongoing(1) = '1' ELSE
                              fifo_address(32*3-1 DOWNTO 32*2) WHEN channel_ongoing(2) = '1' ELSE
                              fifo_address(32*4-1 DOWNTO 32*3) WHEN channel_ongoing(3) = '1' ELSE
                              fifo_address(32*5-1 DOWNTO 32*4);  --WHEN channel_ongoing(4) = '1' ELSE
             END beh;

lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             -- 1.0 - initial version
             -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY lpp;
             USE lpp.lpp_amba.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_dma_pkg.ALL;
-            USE lpp.lpp_waveform_pkg.ALL;
+            --USE lpp.lpp_waveform_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_dma_singleOrBurst IS
               GENERIC (
                 tech                    : INTEGER := inferred;
                 hindex                  : INTEGER := 2
                 );
               PORT (
                 -- AMBA AHB system signals
                 HCLK               : IN  STD_ULOGIC;
                 HRESETn            : IN  STD_ULOGIC;
                 --
                 run : IN STD_LOGIC;
                 -- AMBA AHB Master Interface
                 AHB_Master_In      : IN  AHB_Mst_In_Type;
                 AHB_Master_Out     : OUT AHB_Mst_Out_Type;
                 --
                 send               : IN  STD_LOGIC;
                 valid_burst        : IN  STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
                 done               : OUT STD_LOGIC;
                 ren                : OUT STD_LOGIC;
                 address            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 data               : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --
                 debug_dmaout_okay : OUT STD_LOGIC
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
               -----------------------------------------------------------------------------
               SIGNAL DMAIn  : DMA_In_Type;
               SIGNAL DMAOut : DMA_OUt_Type;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- CONTROL
               SIGNAL single_send : STD_LOGIC;
               SIGNAL burst_send  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SEND SINGLE MODULE
               SIGNAL single_dmai            : DMA_In_Type;
               SIGNAL single_send_ok         : STD_LOGIC;
               SIGNAL single_send_ko         : STD_LOGIC;
               SIGNAL single_ren             : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SEND SINGLE MODULE
               SIGNAL burst_dmai            : DMA_In_Type;
               SIGNAL burst_send_ok         : STD_LOGIC;
               SIGNAL burst_send_ko         : STD_LOGIC;
               SIGNAL burst_ren             : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL data_2_halfword      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- \/ -- 20/02/2014 -- JC Pellion
               SIGNAL send_reg : STD_LOGIC;
               SIGNAL send_s   : STD_LOGIC;
               -- /\ --
             BEGIN
               debug_dmaout_okay <= DMAOut.OKAY;
               -----------------------------------------------------------------------------
               -- DMA to AHB interface
               DMA2AHB_1 : DMA2AHB
                 GENERIC MAP (
                   hindex   => hindex,
                   vendorid => VENDOR_LPP,
                   deviceid => 10,
                   version  => 0,
                   syncrst  => 1,
                   boundary => 1)                    -- FIX 11/01/2013
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => DMAIn,
                   DMAOut  => DMAOut,
                   AHBIn   => AHB_Master_In,
                   AHBOut  => AHB_Master_Out);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- \/ -- 20/02/2014 -- JC Pellion
               PROCESS (HCLK, HRESETn)
               BEGIN
                 IF HRESETn = '0' THEN
                   send_reg <= '0';
                 ELSIF HCLK'event AND HCLK = '1' THEN
                   send_reg <= send;
                 END IF;
               END PROCESS;
               send_s <= send_reg;
               single_send   <= send_s  WHEN valid_burst = '0' ELSE '0';
               burst_send    <= send_s  WHEN valid_burst = '1' ELSE '0';
               -- /\ --
               DMAIn         <= single_dmai      WHEN valid_burst = '0' ELSE burst_dmai;
               -- TODO : verifier
               done  <= single_send_ok OR single_send_ko OR burst_send_ok  OR burst_send_ko;
               --done  <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
               --         burst_send_ok  OR burst_send_ko;
               --ren   <= burst_ren     WHEN valid_burst = '1' ELSE
               --         NOT single_send_ok;
               --ren   <= burst_ren AND single_ren;
               -- \/ JC - 20/01/2014 \/
               ren   <= burst_ren    WHEN valid_burst = '1' ELSE
                        single_ren;
               --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
               --       '1';
               -- /\ JC - 20/01/2014 /\
               -----------------------------------------------------------------------------
               -- SEND 1 word by DMA
               -----------------------------------------------------------------------------
               lpp_dma_send_1word_1 : lpp_dma_send_1word
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => single_dmai,
                   DMAOut  => DMAOut,
                   send    => single_send,
                   address => address,
                   data    => data_2_halfword,
                   ren     => single_ren,
                   send_ok => single_send_ok,        -- TODO
                   send_ko => single_send_ko         -- TODO
                   );
               -----------------------------------------------------------------------------
               -- SEND 16 word by DMA (in burst mode)
               -----------------------------------------------------------------------------
               --data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
               data_2_halfword(31 DOWNTO 0) <= data(31 DOWNTO 0);
               lpp_dma_send_16word_1 : lpp_dma_send_16word
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => burst_dmai,
                   DMAOut  => DMAOut,
                   send    => burst_send,
                   address => address,
                   data    => data_2_halfword,
                   ren     => burst_ren,
                   send_ok => burst_send_ok,
                   send_ko => burst_send_ko);
             END Behavioral;

lib/lpp/lpp_sim/lpp_sim_pkg.vhd +36 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.stdlib.ALL;
             LIBRARY gaisler;
             USE gaisler.libdcom.ALL;
             USE gaisler.sim.ALL;
             USE gaisler.jtagtst.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_sim_pkg IS
               PROCEDURE UART_INIT (
                 SIGNAL   TX        : OUT STD_LOGIC;
                 CONSTANT tx_period : IN  TIME
                 );
               PROCEDURE UART_WRITE_ADDR32 (
                 SIGNAL   TX        : OUT STD_LOGIC;
                 CONSTANT tx_period : IN  TIME;
                 CONSTANT ADDR      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 CONSTANT DATA      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
               PROCEDURE UART_WRITE (
                 SIGNAL   TX        : OUT STD_LOGIC;
                 CONSTANT tx_period : IN  TIME;
                 CONSTANT ADDR      : IN  STD_LOGIC_VECTOR(31 DOWNTO 2);
                 CONSTANT DATA      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
+              PROCEDURE UART_READ (
+                SIGNAL   TX        : OUT STD_LOGIC;
+                SIGNAL   RX        : IN  STD_LOGIC;
+                CONSTANT tx_period : IN  TIME;
+                CONSTANT ADDR      : IN  STD_LOGIC_VECTOR(31 DOWNTO 2);
+                DATA      : OUT  STD_LOGIC_VECTOR
+                );
             END lpp_sim_pkg;
             PACKAGE BODY lpp_sim_pkg IS
               PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
               BEGIN
                 txc(TX, 16#55#, tx_period);
               END;
               PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
               CONSTANT ADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
               CONSTANT DATA                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
               BEGIN
                 txc(TX, 16#c0#, tx_period);
                 txa(TX,
                     to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
                     to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
                     to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
                     to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
                     tx_period);
                 txa(TX,
                     to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
                     to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
                     to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
                     to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
                     tx_period);
               END;
               PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
               CONSTANT ADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 2);
               CONSTANT DATA                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
                 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
               BEGIN
                 txc(TX, 16#c0#, tx_period);
                 txa(TX,
                     to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
                     to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
                     to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
                     to_integer(UNSIGNED(ADDR_last)),
                     tx_period);
                 txa(TX,
                     to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
                     to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
                     to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
                     to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
                     tx_period);
               END;
+              PROCEDURE UART_READ (
+                SIGNAL   TX        : OUT STD_LOGIC;
+                SIGNAL   RX        : IN  STD_LOGIC;
+                CONSTANT tx_period : IN  TIME;
+                CONSTANT ADDR      : IN  STD_LOGIC_VECTOR(31 DOWNTO 2);
+                DATA      : OUT  STD_LOGIC_VECTOR )
+              IS
+                VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
+                CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
+              BEGIN
+                txc(TX, 16#80#, tx_period);
+                txa(TX,
+                    to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
+                    to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
+                    to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
+                    to_integer(UNSIGNED(ADDR_last)),
+                    tx_period);
+                rxc(RX,V_DATA,tx_period);
+                DATA(31 DOWNTO 24) := V_DATA;
+                rxc(RX,V_DATA,tx_period);
+                DATA(23 DOWNTO 16) := V_DATA;
+                rxc(RX,V_DATA,tx_period);
+                DATA(15 DOWNTO 8) := V_DATA;
+                rxc(RX,V_DATA,tx_period);
+                DATA(7 DOWNTO 0) := V_DATA;
+              END;
             END lpp_sim_pkg;

lib/lpp/lpp_sim/vhdlsim.txt +1 0

@@ -1,2 +1,3
1	lpp_sim_pkg.vhd	1	lpp_sim_pkg.vhd
		2	lpp_lfr_sim_pkg.vhd
2		3

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