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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 GRLIB=../..
2 TOP=leon3mp
3 BOARD=em-LeonLPP-A3PE3kL-v3-core1
4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8 EFFORT=high
9 XSTOPT=
10 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
11 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
12 VHDLSYNFILES=config.vhd leon3mp.vhd
13 #VHDLSIMFILES=testbench.vhd
14 #SIMTOP=testbench
15 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
16 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
17 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
18 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
19 CLEAN=soft-clean
20
21 TECHLIBS = proasic3e
22
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc
25
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./amba_lcd_16x2_ctrlr \
29 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_delay \
32 ./lpp_bootloader \
33 ./lpp_cna \
34 ./lpp_uart \
35 ./lpp_usb \
36
37 FILESKIP = i2cmst.vhd \
38 APB_MULTI_DIODE.vhd \
39 APB_MULTI_DIODE.vhd \
40 Top_MatrixSpec.vhd \
41 APB_FFT.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 use lpp.iir_filter.all;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
45 ENTITY leon3mp IS
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
54 );
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
60 errorn : OUT STD_ULOGIC;
61
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
91
92 -- ADC --------------------------------------------------------------------
93 bias_fail_sw : OUT STD_LOGIC;
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 ADC_smpclk : OUT STD_LOGIC;
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97
98 ---------------------------------------------------------------------------
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
100 );
101 END;
102
103 ARCHITECTURE Behavioral OF leon3mp IS
104
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 -- CFG_GRETH+CFG_AHB_JTAG;
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CFG_AHB_UART+
109 CFG_GRETH+
110 CFG_AHB_JTAG
111 +3; -- 1 is for the SpaceWire module grspw, which is a master
112 -- 1 is for the LFR SM
113 -- 1 is for the LFR WFP
114
115 CONSTANT maxahbm : INTEGER := maxahbmsp;
116
117 --Clk & Rst gοΏ½nοΏ½
118 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 SIGNAL resetnl : STD_ULOGIC;
121 SIGNAL clk2x : STD_ULOGIC;
122 SIGNAL lclk2x : STD_ULOGIC;
123 SIGNAL lclk25MHz : STD_ULOGIC;
124 SIGNAL lclk50MHz : STD_ULOGIC;
125 SIGNAL lclk100MHz : STD_ULOGIC;
126 SIGNAL clkm : STD_ULOGIC;
127 SIGNAL rstn : STD_ULOGIC;
128 SIGNAL rstraw : STD_ULOGIC;
129 SIGNAL pciclk : STD_ULOGIC;
130 SIGNAL sdclkl : STD_ULOGIC;
131 SIGNAL cgi : clkgen_in_type;
132 SIGNAL cgo : clkgen_out_type;
133 --- AHB / APB
134 SIGNAL apbi : apb_slv_in_type;
135 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
136 SIGNAL ahbsi : ahb_slv_in_type;
137 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
138 SIGNAL ahbmi : ahb_mst_in_type;
139 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
140 --UART
141 SIGNAL ahbuarti : uart_in_type;
142 SIGNAL ahbuarto : uart_out_type;
143 SIGNAL apbuarti : uart_in_type;
144 SIGNAL apbuarto : uart_out_type;
145 --MEM CTRLR
146 SIGNAL memi : memory_in_type;
147 SIGNAL memo : memory_out_type;
148 SIGNAL wpo : wprot_out_type;
149 SIGNAL sdo : sdram_out_type;
150 SIGNAL ramcs : STD_ULOGIC;
151 --IRQ
152 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
153 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
154 --Timer
155 SIGNAL gpti : gptimer_in_type;
156 SIGNAL gpto : gptimer_out_type;
157 --GPIO
158 SIGNAL gpioi : gpio_in_type;
159 SIGNAL gpioo : gpio_out_type;
160 --DSU
161 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
162 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
163 SIGNAL dsui : dsu_in_type;
164 SIGNAL dsuo : dsu_out_type;
165
166 ---------------------------------------------------------------------
167 --- AJOUT TEST ------------------------Signaux----------------------
168 ---------------------------------------------------------------------
169
170 ---------------------------------------------------------------------
171 CONSTANT IOAEN : INTEGER := CFG_CAN;
172 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
173
174 -- time management signal
175 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
177
178 -- Spacewire signals
179 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
180 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
181 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
182 signal spw_rxtxclk : std_ulogic;
183 signal spw_rxclkn : std_ulogic;
184 SIGNAL spw_clk : std_logic;
185 SIGNAL swni : grspw_in_type; -- PLE
186 SIGNAL swno : grspw_out_type; -- PLE
187 SIGNAL clkmn : STD_ULOGIC; -- PLE
188 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
189
190 -- AD Converter RHF1401
191 SIGNAL sample : Samples14v(7 DOWNTO 0);
192 SIGNAL sample_val : STD_LOGIC;
193 -----------------------------------------------------------------------------
194 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
195
196 BEGIN
197
198
199 ----------------------------------------------------------------------
200 --- Reset and Clock generation -------------------------------------
201 ----------------------------------------------------------------------
202
203 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
204 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
205
206 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
207
208
209 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
210
211 clkgen0 : clkgen -- clock generator
212 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
213 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
214 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
215
216 PROCESS(lclk100MHz)
217 BEGIN
218 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
219 lclk50MHz <= NOT lclk50MHz;
220 END IF;
221 END PROCESS;
222
223 PROCESS(lclk50MHz)
224 BEGIN
225 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
226 lclk25MHz <= NOT lclk25MHz;
227 END IF;
228 END PROCESS;
229
230 lclk2x <= lclk50MHz;
231 spw_clk <= lclk50MHz;
232
233 ----------------------------------------------------------------------
234 --- LEON3 processor / DSU / IRQ ------------------------------------
235 ----------------------------------------------------------------------
236
237 l3 : IF CFG_LEON3 = 1 GENERATE
238 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
239 u0 : leon3s -- LEON3 processor
240 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
241 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
242 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
243 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
244 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
245 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
246 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
247 irqi(i), irqo(i), dbgi(i), dbgo(i));
248 END GENERATE;
249 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
250
251 dsugen : IF CFG_DSU = 1 GENERATE
252 dsu0 : dsu3 -- LEON3 Debug Support Unit
253 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
254 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
255 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
256 dsui.enable <= '1';
257 dsui.break <= '0';
258 led(2) <= dsuo.active;
259 END GENERATE;
260 END GENERATE;
261
262 nodsu : IF CFG_DSU = 0 GENERATE
263 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
264 END GENERATE;
265
266 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
267 irqctrl0 : irqmp -- interrupt controller
268 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
269 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
270 END GENERATE;
271 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
272 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
273 irqi(i).irl <= "0000";
274 END GENERATE;
275 apbo(2) <= apb_none;
276 END GENERATE;
277
278 ----------------------------------------------------------------------
279 --- Memory controllers ---------------------------------------------
280 ----------------------------------------------------------------------
281 memctrlr : mctrl GENERIC MAP (
282 hindex => 0,
283 pindex => 0,
284 paddr => 0,
285 srbanks => 1
286 )
287 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
288
289 memi.brdyn <= '1';
290 memi.bexcn <= '1';
291 memi.writen <= '1';
292 memi.wrn <= "1111";
293 memi.bwidth <= "10";
294
295 bdr : FOR i IN 0 TO 3 GENERATE
296 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
297 PORT MAP (
298 data(31-i*8 DOWNTO 24-i*8),
299 memo.data(31-i*8 DOWNTO 24-i*8),
300 memo.bdrive(i),
301 memi.data(31-i*8 DOWNTO 24-i*8));
302 END GENERATE;
303
304 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
305 PORT MAP (address, memo.address(21 DOWNTO 2));
306
307 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
308 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
309 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
310 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
311 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
312 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
313 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
314
315 ----------------------------------------------------------------------
316 --- AHB CONTROLLER -------------------------------------------------
317 ----------------------------------------------------------------------
318 ahb0 : ahbctrl -- AHB arbiter/multiplexer
319 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
320 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
321 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
322 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
323
324 ----------------------------------------------------------------------
325 --- AHB UART -------------------------------------------------------
326 ----------------------------------------------------------------------
327 dcomgen : IF CFG_AHB_UART = 1 GENERATE
328 dcom0 : ahbuart
329 GENERIC MAP ( hindex => 4, pindex => 4, paddr => 4)
330 PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(4));
331 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
332 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
333 led(0) <= NOT ahbuarti.rxd;
334 led(1) <= NOT ahbuarto.txd;
335 END GENERATE;
336 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
337
338 ----------------------------------------------------------------------
339 --- APB Bridge -----------------------------------------------------
340 ----------------------------------------------------------------------
341 apb0 : apbctrl -- AHB/APB bridge
342 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
343 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
344
345 ----------------------------------------------------------------------
346 --- GPT Timer ------------------------------------------------------
347 ----------------------------------------------------------------------
348 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
349 timer0 : gptimer -- timer unit
350 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
351 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
352 nbits => CFG_GPT_TW)
353 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
354 gpti.dhalt <= dsuo.tstop;
355 gpti.extclk <= '0';
356 END GENERATE;
357 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
358
359
360 ----------------------------------------------------------------------
361 --- APB UART -------------------------------------------------------
362 ----------------------------------------------------------------------
363 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
364 uart1 : apbuart -- UART 1
365 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
366 fifosize => CFG_UART1_FIFO)
367 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
368 apbuarti.rxd <= urxd1;
369 apbuarti.extclk <= '0';
370 utxd1 <= apbuarto.txd;
371 apbuarti.ctsn <= '0';
372 END GENERATE;
373 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
374
375 -------------------------------------------------------------------------------
376 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
377 -------------------------------------------------------------------------------
378 lfrtimemanagement0 : apb_lfr_time_management
379 GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#,
380 masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536,
381 pirq => 12)
382 PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6),
383 coarse_time, fine_time);
384
385 -----------------------------------------------------------------------
386 --- SpaceWire --------------------------------------------------------
387 -----------------------------------------------------------------------
388
389 spw_rxtxclk <= spw_clk;
390 spw_rxclkn <= not spw_rxtxclk;
391
392 -- PADS for SPW1
393 spw1_rxd_pad : inpad generic map (tech => padtech)
394 port map (spw1_din, dtmp(0));
395 spw1_rxs_pad : inpad generic map (tech => padtech)
396 port map (spw1_sin, stmp(0));
397 spw1_txd_pad : outpad generic map (tech => padtech)
398 port map (spw1_dout, swno.d(0));
399 spw1_txs_pad : outpad generic map (tech => padtech)
400 port map (spw1_sout, swno.s(0));
401 -- PADS FOR SPW2
402 spw2_rxd_pad : inpad generic map (tech => padtech)
403 port map (spw2_din, dtmp(1));
404 spw2_rxs_pad : inpad generic map (tech => padtech)
405 port map (spw2_sin, stmp(1));
406 spw2_txd_pad : outpad generic map (tech => padtech)
407 port map (spw2_dout, swno.d(1));
408 spw2_txs_pad : outpad generic map (tech => padtech)
409 port map (spw2_sout, swno.s(1));
410
411 -- GRSPW PHY
412 --spw1_input: if CFG_SPW_GRSPW = 1 generate
413 spw_inputloop: for j in 0 to 1 generate
414 spw_phy0 : grspw_phy
415 generic map(
416 tech => fabtech,
417 rxclkbuftype => 1,
418 scantest => 0)
419 port map(
420 rxrst => swno.rxrst,
421 di => dtmp(j),
422 si => stmp(j),
423 rxclko => spw_rxclk(j),
424 do => swni.d(j),
425 ndo => swni.nd(j*5+4 downto j*5),
426 dconnect => swni.dconnect(j*2+1 downto j*2));
427 end generate spw_inputloop;
428
429 -- SPW core
430 sw0 : grspwm generic map(
431 tech => apa3e,
432 hindex => 1,
433 pindex => 5,
434 paddr => 5,
435 pirq => 11,
436 sysfreq => 25000, -- CPU_FREQ
437 rmap => 1,
438 rmapcrc => 1,
439 fifosize1 => 16,
440 fifosize2 => 16,
441 rxclkbuftype => 1,
442 rxunaligned => 0,
443 rmapbufs => 4,
444 ft => 0,
445 netlist => 0,
446 ports => 2,
447 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
448 memtech => apa3e,
449 destkey => 2,
450 spwcore => 1
451 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
452 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
453 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
454 )
455 port map(rstn, clkm, spw_rxclk(0),
456 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
457 ahbmi, ahbmo(1), apbi, apbo(5),
458 swni, swno);
459
460 swni.tickin <= '0';
461 swni.rmapen <= '1';
462 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
463 swni.tickinraw <= '0';
464 swni.timein <= (others => '0');
465 swni.dcrstval <= (others => '0');
466 swni.timerrstval <= (others => '0');
467
468 -------------------------------------------------------------------------------
469 -- LFR
470 -------------------------------------------------------------------------------
471 lpp_lfr_1: lpp_lfr
472 GENERIC MAP (
473 Mem_use => use_RAM,
474 nb_burst_available_size => 12,
475 nb_snapshot_param_size => 12,
476 delta_snapshot_size => 16,
477 delta_f2_f0_size => 20,
478 delta_f2_f1_size => 16,
479 pindex => 15,
480 paddr => 15,
481 pmask => 16#fff#,
482 pirq_ms => 6,
483 pirq_wfp => 14,
484 hindex_wfp => 2,
485 hindex_ms => 3)
486 PORT MAP (
487 clk => clkm,
488 rstn => rstn,
489 sample_B => sample(2 DOWNTO 0),
490 sample_E => sample(7 DOWNTO 3),
491 sample_val => sample_val,
492 apbi => apbi,
493 apbo => apbo(15),
494 ahbi_wfp => ahbmi,
495 ahbo_wfp => ahbmo(2),
496 ahbi_ms => ahbmi,
497 ahbo_ms => ahbmo(3),
498 coarse_time_0 => coarse_time(0),
499 data_shaping_BW => bias_fail_sw);
500
501 top_ad_conv_RHF1401_1: top_ad_conv_RHF1401
502 GENERIC MAP (
503 ChanelCount => 8,
504 ncycle_cnv_high => 79,
505 ncycle_cnv => 500)
506 PORT MAP (
507 cnv_clk => clk49_152MHz,
508 cnv_rstn => rstn,
509
510 cnv => ADC_smpclk,
511
512 clk => clkm,
513 rstn => rstn,
514 ADC_data => ADC_data,
515
516 ADC_nOE => ADC_OEB_bar_CH,
517 sample => sample,
518 sample_val => sample_val);
519
520 END Behavioral;
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