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add comments for clk_50 frequency in the code (ALTRAN request)
add comments for clk_50 frequency in the code (ALTRAN request)
pellion - - Load All Authors

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r580:f4e8c3120b82 simu_with_Leon3
r610:f9824a3b6ae2 simu_with_Leon3
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bootrom.S
214 lines | 2.7 KiB | text/S-plus | SLexer
/ lib / lpp / lpp_bootloader / bootrom.S
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pellion
BootLoader v1.0.0
 r110
/* Template boot-code for LEON3 test benches */
#include "bootrom.h"
#ifndef STACKSIZE
#define STACKSIZE 0x00020000
#endif
.seg "text"
.proc 0
.align 4
.global start
start:
flush
set 0x10e0, %g1 ! init IU
mov %g1, %psr
mov %g0, %wim
mov %g0, %tbr
mov %g0, %y
mov %g0, %asr16
nop
set 0x81000f, %g1
sta %g1, [%g0] 2
mov %g0, %g2
nop
nop
nop
nop
nop
or %g2, %g2, %g0
nop
nop
nop
nop
nop
#ifdef DSUADDR
set DSUADDR, %g2
st %g0, [%g2]
st %g0, [%g2+0x08]
st %g0, [%g2+0x20]
st %g0, [%g2+0x24]
st %g0, [%g2+0x40]
st %g0, [%g2+0x44]
st %g0, [%g2+0x50]
st %g0, [%g2+0x54]
st %g0, [%g2+0x58]
st %g0, [%g2+0x5C]
st %g0, [%g2+0x54]
#endif
2:
mov %asr17, %g3
and %g3, 0x1f, %g3
mov %g0, %g4
mov %g0, %g5
mov %g0, %g6
mov %g0, %g7
1:
mov %g0, %l0
mov %g0, %l1
mov %g0, %l2
mov %g0, %l3
mov %g0, %l4
mov %g0, %l5
mov %g0, %l6
mov %g0, %l7
mov %g0, %o0
mov %g0, %o1
mov %g0, %o2
mov %g0, %o3
mov %g0, %o4
mov %g0, %o5
mov %g0, %o6
mov %g0, %o7
subcc %g3, 1, %g3
bge 1b
save
mov 2, %g1
mov %g1, %wim
set 0x10e0, %g1 ! enable traps
mov %g1, %psr
nop; nop; nop;
mov %psr, %g1
srl %g1, 12, %g1
andcc %g1, 1, %g0
be 1f
nop
set _fsrxx, %g3
ld [%g3], %fsr
ldd [%g3], %f0
ldd [%g3], %f2
ldd [%g3], %f4
ldd [%g3], %f6
ldd [%g3], %f8
ldd [%g3], %f10
ldd [%g3], %f12
ldd [%g3], %f14
ldd [%g3], %f16
ldd [%g3], %f18
ldd [%g3], %f20
ldd [%g3], %f22
ldd [%g3], %f24
ldd [%g3], %f26
ldd [%g3], %f28
ldd [%g3], %f30
nop
nop
nop
nop
nop
faddd %f0, %f2, %f4
nop
nop
nop
nop
ba 1f
nop
.align 8
_fsrxx:
.word 0
.word 0
1:
mov %asr17, %g3
srl %g3, 28, %g3
andcc %g3, 0x0f, %g3
bne 1f
pellion
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
 r580 /* set L2MCTRLIO, %g1
pellion
BootLoader v1.0.0
 r110 set MCFG1, %g2
st %g2, [%g1]
set MCFG2, %g2
st %g2, [%g1+4]
set MCFG3, %g2
st %g2, [%g1+8]
pellion
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
 r580 */
pellion
BootLoader v1.0.0
 r110 ! set IRQCTRL, %g1
! set 0x0ffff, %g2
! st %g2, [%g1+0x10]
#ifdef DDR2CTRLIO
set DDR2CTRLIO, %g1
set DDR2CFG4, %g2
st %g2, [%g1+12]
#endif
#ifdef ASDCFG
#ifndef SDCTRLPNP
#define SDCTRLPNP 0xFFFFF860
#endif
set SDCTRLPNP, %g1
ld [%g1], %g2
srl %g2, 12, %g2
set 0x01009, %g1
subcc %g1, %g2, %g0
bne 1f
set ASDCFG, %g1
set DSDCFG, %g2
st %g2, [%g1]
#endif
! %g3 = cpu index
1: set STACKSIZE, %g2
mov %g0, %g1
2: subcc %g3, 0, %g0
be 3f
nop
add %g1, %g2, %g1
ba 2b
sub %g3, 1, %g3
pellion
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
 r580 3: set RAMSTART_RAMSIZE-32, %fp
sub %fp, %g1, %fp
sub %fp, 96, %sp
pellion
BootLoader v1.0.0
 r110
pellion
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
 r580 set RAMSTART, %g1
jmp %g1
nop
/*
pellion
BootLoader v1.0.0
 r110 3:
set REG_BOOTLOADER, %10
ld [%10], %11
tst %11
be RunProg
inf_wait_on_boot:
nop
ld [%10+4], %11
tst %11
be inf_wait_on_boot
RunProg:
nop
ld [%10+8], %11
set RAMSTART_RAMSIZE-32, %10
add %11, %10, %fp
sub %fp, %g1, %fp
sub %fp, 96, %sp
mov %11, %g1
jmp %g1
nop
pellion
custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
 r580 */
pellion
BootLoader v1.0.0
 r110 .align 32