HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · boards/MINI-LFR/Makefile.inc

add RTAX post layout constraint

pellion - - Load All Authors

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simu_with_Leon3

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             Makefile.inc
        
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                MakefileLexer
            
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        Alexis Jeandet
    
MINI-LFR board added

              r245
            
      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

        pellion
    
TOP with Leon3 SoC only (no LPP module)

              r260
            
      TECHNOLOGY=ProASIC3E

      LIBERO_DIE=IT14X14M4

      PART=A3PE3000

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

        Alexis Jeandet
    
MINI-LFR board added

              r245
            
      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

        pellion
    
TOP with Leon3 SoC only (no LPP module)

              r260
            
      MGCTECHNOLOGY=Proasic3

        Alexis Jeandet
    
MINI-LFR board added

              r245
            
      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

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Alexis Jeandet MINI-LFR board added	r245	PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

pellion TOP with Leon3 SoC only (no LPP module)	r260	TECHNOLOGY=ProASIC3E
		LIBERO_DIE=IT14X14M4
		PART=A3PE3000

		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM
Alexis Jeandet MINI-LFR board added	r245	DESIGNER_PACKAGE=FBGA
		DESIGNER_PINS=324

		MANUFACTURER=Actel
pellion TOP with Leon3 SoC only (no LPP module)	r260	MGCTECHNOLOGY=Proasic3
Alexis Jeandet MINI-LFR board added	r245	MGCPART=$(PART)
		MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		LIBERO_PACKAGE=fg$(DESIGNER_PINS)