HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · boards/UT8ER1M32-test-board/Makefile.inc

update test design Validation_CIC_LFR (and lib\lpp\chirp simulation IP)

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r482:792dac4c614c JC


                r634:b5a2eca6bf42

simu_with_Leon3

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             Makefile.inc
        
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        Alexis Jeandet
    
Patch1

              r433
            
      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

      TECHNOLOGY=ProASIC3E

      LIBERO_DIE=IT14X14M4

      PART=A3PE3000

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

      DESIGNER_PACKAGE=FBGA

      DESIGNER_PINS=324

      MANUFACTURER=Actel

      MGCTECHNOLOGY=Proasic3

      MGCPART=$(PART)

      MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}

      LIBERO_PACKAGE=fg$(DESIGNER_PINS)

        pellion
    
Preliminary working IAP Memctrlr integration....

              r482

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Alexis Jeandet Patch1	r433	PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

		TECHNOLOGY=ProASIC3E
		LIBERO_DIE=IT14X14M4
		PART=A3PE3000

		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM
		DESIGNER_PACKAGE=FBGA
		DESIGNER_PINS=324

		MANUFACTURER=Actel
		MGCTECHNOLOGY=Proasic3
		MGCPART=$(PART)
		MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
		LIBERO_PACKAGE=fg$(DESIGNER_PINS)

pellion Preliminary working IAP Memctrlr integration....	r482