HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · boards/GSE_ICI/Makefile.inc

update test design Validation_CIC_LFR (and lib\lpp\chirp simulation IP)

Alexis Jeandet - - Load All Authors

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r219:df1aff8cd31b alexis


                r634:b5a2eca6bf42

simu_with_Leon3

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             Makefile.inc
        
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        Alexis Jeandet
    
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

              r217
            
      TECHNOLOGY=PROASIC3

      PACKAGE=\"\"

      SPEED=Std

      SYNFREQ=50

      PART=A3PE1500

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
      DESIGNER_PACKAGE=PQFF

        Alexis Jeandet
    
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

              r217
            
      DESIGNER_PINS=208

      DESIGNER_VOLTAGE=COM

      DESIGNER_TEMP=COM

      MANUFACTURER=Actel

      MGCPART=$(PART)

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
      MGCTECHNOLOGY=ProASIC3E

      MGCPACKAGE= {$(DESIGNER_PINS)$(DESIGNER_PACKAGE)}

      LIBERO_DIE=IT10X10M3

      LIBERO_PACKAGE=pq$(DESIGNER_PINS)

        Alexis Jeandet
    
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

              r217

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Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217	TECHNOLOGY=PROASIC3
		PACKAGE=\"\"
		SPEED=Std
		SYNFREQ=50

		PART=A3PE1500
Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219	DESIGNER_PACKAGE=PQFF
Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217	DESIGNER_PINS=208
		DESIGNER_VOLTAGE=COM
		DESIGNER_TEMP=COM

		MANUFACTURER=Actel
		MGCPART=$(PART)
Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219	MGCTECHNOLOGY=ProASIC3E
		MGCPACKAGE= {$(DESIGNER_PINS)$(DESIGNER_PACKAGE)}
		LIBERO_DIE=IT10X10M3
		LIBERO_PACKAGE=pq$(DESIGNER_PINS)
Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217