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             UART.vhd
        
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        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

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      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      -------------------------------------------------------------------------------

        Alexis
    
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              r38
            
      --                    Author : Alexis Jeandet

      --                     Mail : alexis.jeandet@lpp.polytechnique.fr

      ----------------------------------------------------------------------------

        Alexis
    
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      library IEEE;

      use IEEE.numeric_std.all;

      use IEEE.std_logic_1164.all;

      library lpp;

      use lpp.lpp_uart.all;

        alexis
    
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      --! \brief A general purpose UART with automatic baudrate 

      --! 

      --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr

        Alexis
    
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      entity UART is 

        alexis
    
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              r67
            
      generic(Data_sz     :   integer :=  8);            --! Data width

        Alexis
    
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      port(

        alexis
    
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          clk         :   in  std_logic;                              --! System clock

          reset       :   in  std_logic;                              --! System reset

          TXD         :   out std_logic;                              --! UART Transmission pin

          RXD         :   in  std_logic;                              --! UART Reception pin

          Capture     :   in  std_logic;                              --! Automatic baudrate module reset

          NwDat       :   out std_logic;                              --! New data flag, means that a new data have been received by the UART

          ACK         :   in  std_logic;                              --! Acknowledge flag to clear NwDat flag

          Send        :   in  std_logic;                              --! To send a data you have to set this flag

          Sended      :   out std_logic;                              --! When this flag is set you can sed a new data

          BTrigger    :   out std_logic_vector(11 downto 0);          --! Baudrate generator current value, could be usefull if you whant to know the current value of the baudrate or of the oscillator (it suppose that you know baudrate)

          RDATA       :   out std_logic_vector(Data_sz-1 downto 0);   --! Current read word

          WDATA       :   in  std_logic_vector(Data_sz-1 downto 0)    --! Put here the word you whant to send

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      );

      end entity;

        alexis
    
Improved doxygen html output, improved documentation on some VHDL and C files.

              r67
            
        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      architecture ar_UART of UART is

      signal  Bclk    :   std_logic;

        martin
    
Update and debug UART

              r99
            
      signal  RDATA_int   :   std_logic_vector(Data_sz+1 downto 0);

      signal  WDATA_int   :   std_logic_vector(Data_sz+1 downto 0);

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        martin
    
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              r99
            
      signal  Take        :   std_logic;

      signal  Taken       :   std_logic;

      signal  Taken_reg   :   std_logic;

      constant Dummy      :   std_logic_vector(Data_sz+1 downto 0) := (others => '1');

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      begin

        martin
    
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              r99
            
      NwDat    <= '0' when (ack = '1') else '1' when (Taken_reg='0' and Taken='1');

      WDATA_int     <= '1' & WDATA & '0';

        Alexis
    
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              r36
            
        martin
    
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              r99
            
      BaudGenerator : BaudGen

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
          port map(clk,reset,Capture,Bclk,RXD,BTrigger);

        martin
    
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              r99
            
      RX_REG  : Shift_Reg

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
          generic map(Data_sz+2)

        martin
    
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              r99
            
          port map(Bclk,RXD,open,Take,Taken,Dummy,RDATA_int);

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
        martin
    
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              r99
            
      TX_REG  : Shift_Reg

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
          generic map(Data_sz+2)

        martin
    
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              r99
            
          port map(Bclk,Dummy(0),TXD,Send,Sended,WDATA_int,open);

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
      process(clk,reset)

      begin

        martin
    
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              r99
            
          if(reset ='0')then

              Take   <=  '0';

          elsif(clk'event and clk ='1')then

              Taken_reg <= Taken;

              if(RXD ='0' and Taken ='1')then

                  Take <=  '1';

              elsif(Taken ='0')then

                  Take <=  '0';

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
              end if;

        martin
    
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              r99
            
              if (Taken_reg ='0' and Taken ='1') then

      			RDATA   <=  RDATA_int(8 downto 1);

        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
              end if;

        martin
    
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              r99
            
        Alexis
    
Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\

              r19
            
          end if;

      end process;

        martin
    
Update and debug UART

              r99
            
      end architecture;

        Alexis
    
Added an automated Devices ID and Vendor ID handler

              r36

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Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		-------------------------------------------------------------------------------
Alexis Minor changes	r38	-- Author : Alexis Jeandet
		-- Mail : alexis.jeandet@lpp.polytechnique.fr
		----------------------------------------------------------------------------
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	library IEEE;
		use IEEE.numeric_std.all;
		use IEEE.std_logic_1164.all;
		library lpp;
		use lpp.lpp_uart.all;

alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67	--! \brief A general purpose UART with automatic baudrate
		--!
		--! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		entity UART is
alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67	generic(Data_sz : integer := 8); --! Data width
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	port(
alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67	clk : in std_logic; --! System clock
		reset : in std_logic; --! System reset
		TXD : out std_logic; --! UART Transmission pin
		RXD : in std_logic; --! UART Reception pin
		Capture : in std_logic; --! Automatic baudrate module reset
		NwDat : out std_logic; --! New data flag, means that a new data have been received by the UART
		ACK : in std_logic; --! Acknowledge flag to clear NwDat flag
		Send : in std_logic; --! To send a data you have to set this flag
		Sended : out std_logic; --! When this flag is set you can sed a new data
		BTrigger : out std_logic_vector(11 downto 0); --! Baudrate generator current value, could be usefull if you whant to know the current value of the baudrate or of the oscillator (it suppose that you know baudrate)
		RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word
		WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Put here the word you whant to send
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	);
		end entity;

alexis Improved doxygen html output, improved documentation on some VHDL and C files.	r67
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	architecture ar_UART of UART is
		signal Bclk : std_logic;

martin Update and debug UART	r99	signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
		signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
martin Update and debug UART	r99	signal Take : std_logic;
		signal Taken : std_logic;
		signal Taken_reg : std_logic;

		constant Dummy : std_logic_vector(Data_sz+1 downto 0) := (others => '1');
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		begin

martin Update and debug UART	r99	NwDat <= '0' when (ack = '1') else '1' when (Taken_reg='0' and Taken='1');
		WDATA_int <= '1' & WDATA & '0';
Alexis Added an automated Devices ID and Vendor ID handler	r36
martin Update and debug UART	r99	BaudGenerator : BaudGen
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	port map(clk,reset,Capture,Bclk,RXD,BTrigger);

martin Update and debug UART	r99	RX_REG : Shift_Reg
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	generic map(Data_sz+2)
martin Update and debug UART	r99	port map(Bclk,RXD,open,Take,Taken,Dummy,RDATA_int);
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
martin Update and debug UART	r99	TX_REG : Shift_Reg
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	generic map(Data_sz+2)
martin Update and debug UART	r99	port map(Bclk,Dummy(0),TXD,Send,Sended,WDATA_int,open);
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19
		process(clk,reset)
		begin
martin Update and debug UART	r99	if(reset ='0')then
		Take <= '0';

		elsif(clk'event and clk ='1')then
		Taken_reg <= Taken;

		if(RXD ='0' and Taken ='1')then
		Take <= '1';
		elsif(Taken ='0')then
		Take <= '0';
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	end if;
martin Update and debug UART	r99
		if (Taken_reg ='0' and Taken ='1') then
		RDATA <= RDATA_int(8 downto 1);
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	end if;
martin Update and debug UART	r99
Alexis Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\	r19	end if;
		end process;

martin Update and debug UART	r99	end architecture;
Alexis Added an automated Devices ID and Vendor ID handler	r36