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Fusion avec alexis
Fusion avec alexis
Alexis Jeandet - - Load All Authors

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r245:0fbfdf431a95 alexis
r250:708a8ff959a7 merge JC
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Makefile
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/ designs / EGSE_ICI / Makefile
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Alexis Jeandet
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
 r220 #GRLIB=../..
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 VHDLIB=../..
Alexis Jeandet
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
 r220 SCRIPTSDIR=$(VHDLIB)/scripts/
GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
Alexis Jeandet
Cleaned EGSE_ICI design.
 r218 TOP=TOP_EGSE2
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 BOARD=GSE_ICI
Alexis Jeandet
MINI-LFR board added
 r245 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
Alexis Jeandet
MINI-LFR board added
 r245 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 EFFORT=high
XSTOPT=
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
Alexis Jeandet
ICI4 EGSE now working, need some more cleaning.
 r219 VHDLSYNFILES=config.vhd EGSE_ICI.vhd DC_GATE_GEN.vhd LF_GATE_GEN.vhd MajF_Gen.vhd MinF_Gen.vhd Serial_driver.vhd ICI_EGSE_PROTOCOL.vhd
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
Alexis Jeandet
MINI-LFR board added
 r245 SDCFILE=$(VHDLIB)/boards/$(BOARD)/synplify.sdc
SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
PDC=$(VHDLIB)/boards/$(BOARD)/GSE_ICI.pdc
BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 CLEAN=soft-clean
TECHLIBS = proasic3
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
Alexis Jeandet
Cleaned EGSE_ICI design.
 r218 tmtc openchip hynix ihp gleichmann micron usbhc spw fmf gsi eth spansion esa
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
Alexis Jeandet
ICI4 EGSE now working, need some more cleaning.
 r219 pci grusbhc haps slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft can greth net gr1553b ./amba_lcd_16x2_ctrlr ./lpp_waveform \
./lpp_dma
Alexis Jeandet
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.
 r217
FILESKIP = i2cmst.vhd
include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile
################## project specific targets ##########################