defconfig
209 lines
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jeandet@PC-DE-JEANDET.lpp.polytechnique.fr
|
r81 | # | ||
| # Automatically generated make config: don't edit | ||||
| # | ||||
| # | ||||
| # Synthesis | ||||
| # | ||||
| CONFIG_SYN_INFERRED=y | ||||
| # CONFIG_SYN_ATC18 is not set | ||||
| # CONFIG_SYN_RHUMC is not set | ||||
| # CONFIG_SYN_IHP25 is not set | ||||
| # CONFIG_SYN_PROASIC is not set | ||||
| # CONFIG_SYN_PROASICPLUS is not set | ||||
| # CONFIG_SYN_PROASIC3 is not set | ||||
| # CONFIG_SYN_AXCEL is not set | ||||
| # CONFIG_SYN_SPARTAN2 is not set | ||||
| # CONFIG_SYN_SPARTAN3 is not set | ||||
| # CONFIG_SYN_VIRTEX is not set | ||||
| # CONFIG_SYN_VIRTEXE is not set | ||||
| # CONFIG_SYN_VIRTEX2 is not set | ||||
| CONFIG_MEM_INFERRED=y | ||||
| # CONFIG_MEM_RHUMC is not set | ||||
| # CONFIG_MEM_IHP25 is not set | ||||
| # CONFIG_MEM_VIRAGE is not set | ||||
| # | ||||
| # Clock generation | ||||
| # | ||||
| CONFIG_CLK_INFERRED=y | ||||
| # CONFIG_CLK_HCLKBUF is not set | ||||
| # CONFIG_CLK_ALTDLL is not set | ||||
| # CONFIG_CLK_CLKDLL is not set | ||||
| # CONFIG_CLK_DCM is not set | ||||
| # CONFIG_PCI_SYSCLK is not set | ||||
| CONFIG_PROC_NUM=1 | ||||
| # | ||||
| # Processor | ||||
| # | ||||
| # | ||||
| # Integer unit | ||||
| # | ||||
| CONFIG_IU_NWINDOWS=8 | ||||
| # CONFIG_IU_V8MULDIV is not set | ||||
| # CONFIG_IU_SVT is not set | ||||
| CONFIG_IU_LDELAY=1 | ||||
| CONFIG_IU_WATCHPOINTS=2 | ||||
| CONFIG_PWD=y | ||||
| CONFIG_IU_RSTADDR=00000 | ||||
| # CONFIG_IU_NOHALT is not set | ||||
| # | ||||
| # Floating-point unit | ||||
| # | ||||
| # CONFIG_FPU_ENABLE is not set | ||||
| # | ||||
| # Cache system | ||||
| # | ||||
| CONFIG_ICACHE_ENABLE=y | ||||
| # CONFIG_ICACHE_ASSO1 is not set | ||||
| CONFIG_ICACHE_ASSO2=y | ||||
| # CONFIG_ICACHE_ASSO3 is not set | ||||
| # CONFIG_ICACHE_ASSO4 is not set | ||||
| # CONFIG_ICACHE_SZ1 is not set | ||||
| CONFIG_ICACHE_SZ2=y | ||||
| # CONFIG_ICACHE_SZ4 is not set | ||||
| # CONFIG_ICACHE_SZ8 is not set | ||||
| # CONFIG_ICACHE_SZ16 is not set | ||||
| # CONFIG_ICACHE_SZ32 is not set | ||||
| # CONFIG_ICACHE_SZ64 is not set | ||||
| # CONFIG_ICACHE_SZ128 is not set | ||||
| # CONFIG_ICACHE_SZ256 is not set | ||||
| # CONFIG_ICACHE_LZ16 is not set | ||||
| CONFIG_ICACHE_LZ32=y | ||||
| # CONFIG_ICACHE_ALGORND is not set | ||||
| CONFIG_ICACHE_ALGOLRR=y | ||||
| # CONFIG_ICACHE_ALGOLRU is not set | ||||
| # CONFIG_ICACHE_LOCK is not set | ||||
| # CONFIG_ICACHE_LRAM is not set | ||||
| CONFIG_DCACHE_ENABLE=y | ||||
| # CONFIG_DCACHE_ASSO1 is not set | ||||
| CONFIG_DCACHE_ASSO2=y | ||||
| # CONFIG_DCACHE_ASSO3 is not set | ||||
| # CONFIG_DCACHE_ASSO4 is not set | ||||
| # CONFIG_DCACHE_SZ1 is not set | ||||
| CONFIG_DCACHE_SZ2=y | ||||
| # CONFIG_DCACHE_SZ4 is not set | ||||
| # CONFIG_DCACHE_SZ8 is not set | ||||
| # CONFIG_DCACHE_SZ16 is not set | ||||
| # CONFIG_DCACHE_SZ32 is not set | ||||
| # CONFIG_DCACHE_SZ64 is not set | ||||
| # CONFIG_DCACHE_SZ128 is not set | ||||
| # CONFIG_DCACHE_SZ256 is not set | ||||
| # CONFIG_DCACHE_LZ16 is not set | ||||
| CONFIG_DCACHE_LZ32=y | ||||
| # CONFIG_DCACHE_ALGORND is not set | ||||
| CONFIG_DCACHE_ALGOLRR=y | ||||
| # CONFIG_DCACHE_ALGOLRU is not set | ||||
| # CONFIG_DCACHE_LOCK is not set | ||||
| # CONFIG_DCACHE_LRAM is not set | ||||
| # | ||||
| # MMU | ||||
| # | ||||
| # CONFIG_MMU_ENABLE is not set | ||||
| # | ||||
| # Debug Support Unit | ||||
| # | ||||
| CONFIG_DSU_ENABLE=y | ||||
| CONFIG_DSU_ITRACE=y | ||||
| CONFIG_DSU_ITRACESZ1=y | ||||
| # CONFIG_DSU_ITRACESZ2 is not set | ||||
| # CONFIG_DSU_ITRACESZ4 is not set | ||||
| # CONFIG_DSU_ITRACESZ8 is not set | ||||
| # CONFIG_DSU_ITRACESZ16 is not set | ||||
| CONFIG_DSU_ATRACE=y | ||||
| CONFIG_DSU_ATRACESZ1=y | ||||
| # CONFIG_DSU_ATRACESZ2 is not set | ||||
| # CONFIG_DSU_ATRACESZ4 is not set | ||||
| # CONFIG_DSU_ATRACESZ8 is not set | ||||
| # CONFIG_DSU_ATRACESZ16 is not set | ||||
| # | ||||
| # AMBA configuration | ||||
| # | ||||
| CONFIG_AHB_DEFMST=0 | ||||
| CONFIG_AHB_RROBIN=y | ||||
| # CONFIG_AHB_SPLIT is not set | ||||
| CONFIG_AHB_IOADDR=FFF | ||||
| CONFIG_APB_HADDR=800 | ||||
| # | ||||
| # Debug Link | ||||
| # | ||||
| CONFIG_DSU_UART=y | ||||
| # CONFIG_DSU_ETH is not set | ||||
| # | ||||
| # Peripherals | ||||
| # | ||||
| # | ||||
| # Memory controllers | ||||
| # | ||||
| CONFIG_MCTRL_SMALL=y | ||||
| # CONFIG_MCTRL_SMALL_8BIT is not set | ||||
| CONFIG_MCTRL_PROMWS=3 | ||||
| CONFIG_MCTRL_RAMWS=0 | ||||
| CONFIG_MCTRL_RMW=y | ||||
| # CONFIG_MCTRL_SDRAM is not set | ||||
| # | ||||
| # On-chip RAM/ROM | ||||
| # | ||||
| # CONFIG_AHBROM_ENABLE is not set | ||||
| # CONFIG_AHBRAM_ENABLE is not set | ||||
| # | ||||
| # Ethernet | ||||
| # | ||||
| # CONFIG_ETH_ENABLE is not set | ||||
| # | ||||
| # CAN | ||||
| # | ||||
| # CONFIG_CAN_ENABLE is not set | ||||
| # | ||||
| # PCI | ||||
| # | ||||
| # CONFIG_PCI_SIMPLE_TARGET is not set | ||||
| # CONFIG_PCI_MASTER_TARGET is not set | ||||
| # CONFIG_PCI_ARBITER_APB is not set | ||||
| # CONFIG_PCI_TRACE is not set | ||||
| # | ||||
| # UARTs, timers and irq control | ||||
| # | ||||
| CONFIG_UART1_ENABLE=y | ||||
| # CONFIG_UA1_FIFO1 is not set | ||||
| # CONFIG_UA1_FIFO2 is not set | ||||
| CONFIG_UA1_FIFO4=y | ||||
| # CONFIG_UA1_FIFO8 is not set | ||||
| # CONFIG_UA1_FIFO16 is not set | ||||
| # CONFIG_UA1_FIFO32 is not set | ||||
| CONFIG_UART2_ENABLE=y | ||||
| # CONFIG_UA2_FIFO1 is not set | ||||
| # CONFIG_UA2_FIFO2 is not set | ||||
| CONFIG_UA2_FIFO4=y | ||||
| # CONFIG_UA2_FIFO8 is not set | ||||
| # CONFIG_UA2_FIFO16 is not set | ||||
| # CONFIG_UA2_FIFO32 is not set | ||||
| CONFIG_IRQ3_ENABLE=y | ||||
| CONFIG_GPT_ENABLE=y | ||||
| CONFIG_GPT_NTIM=2 | ||||
| CONFIG_GPT_SW=8 | ||||
| CONFIG_GPT_TW=32 | ||||
| CONFIG_GPT_IRQ=8 | ||||
| CONFIG_GPT_SEPIRQ=y | ||||
| # | ||||
| # VHDL Debugging | ||||
| # | ||||
| # CONFIG_IU_DISAS is not set | ||||
| # CONFIG_DEBUG_UART is not set | ||||
| # CONFIG_DEBUG_PC32 is not set | ||||