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compile.dc
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Alexis
Improved IIR filter configuration
 r35 sh mkdir synopsys
sh mkdir synopsys/grlib
define_design_lib grlib -path synopsys/grlib
analyze -f VHDL -library grlib ../../lib/grlib/stdlib/version.vhd
analyze -f VHDL -library grlib ../../lib/grlib/stdlib/config.vhd
analyze -f VHDL -library grlib ../../lib/grlib/stdlib/stdlib.vhd
analyze -f VHDL -library grlib ../../lib/grlib/sparc/sparc.vhd
analyze -f VHDL -library grlib ../../lib/grlib/modgen/multlib.vhd
analyze -f VHDL -library grlib ../../lib/grlib/modgen/leaves.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/amba.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/devices.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/defmst.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/apbctrl.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/ahbctrl.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
analyze -f VHDL -library grlib ../../lib/grlib/amba/dma2ahb.vhd
sh mkdir synopsys/unisim
define_design_lib unisim -path synopsys/unisim
sh mkdir synopsys/synplify
define_design_lib synplify -path synopsys/synplify
sh mkdir synopsys/techmap
define_design_lib techmap -path synopsys/techmap
analyze -f VHDL -library techmap ../../lib/techmap/gencomp/gencomp.vhd
analyze -f VHDL -library techmap ../../lib/techmap/gencomp/netcomp.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/memory_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/ddr_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/mul_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
analyze -f VHDL -library techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allclkgen.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allddr.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allmem.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/allpads.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/alltap.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkgen.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkmux.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkand.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ddr_ireg.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ddr_oreg.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ddrphy.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram64.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram_2p.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram_dp.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncfifo.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/regfile_3p.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/tap.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/techbuf.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/nandtree.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/clkpad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iodpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/lvds_combo.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/odpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad_ds.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/toutpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/skew_outpad.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grspwc_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grspwc2_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grlfpw_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grfpw_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/mul_61x61.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/cpu_disas_net.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/ringosc.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/system_monitor.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/grgates.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad_ddr.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad_ddr.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad_ddr.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram128bw.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram128.vhd
analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram156bw.vhd
sh mkdir synopsys/eth
define_design_lib eth -path synopsys/eth
analyze -f VHDL -library eth ../../lib/eth/comp/ethcomp.vhd
analyze -f VHDL -library eth ../../lib/eth/core/greth_pkg.vhd
analyze -f VHDL -library eth ../../lib/eth/core/eth_rstgen.vhd
analyze -f VHDL -library eth ../../lib/eth/core/eth_ahb_mst.vhd
analyze -f VHDL -library eth ../../lib/eth/core/greth_tx.vhd
analyze -f VHDL -library eth ../../lib/eth/core/greth_rx.vhd
analyze -f VHDL -library eth ../../lib/eth/core/grethc.vhd
analyze -f VHDL -library eth ../../lib/eth/wrapper/greth_gen.vhd
analyze -f VHDL -library eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
sh mkdir synopsys/gaisler
define_design_lib gaisler -path synopsys/gaisler
analyze -f VHDL -library gaisler ../../lib/gaisler/arith/arith.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/arith/mul32.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/arith/div32.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/memctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/srctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmuiface.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libmmu.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libiu.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libcache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libproc3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cachemem.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmulrue.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmulru.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutlb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutw.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/iu3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mfpwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/tbufmem.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dsu3x.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dsu3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/proc3.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3s.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3cg.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/irqmp.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3sh.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/misc.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/rstgen.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/gptimer.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbram.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbdpram.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbtrace.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbmst.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grgpio.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbstat.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/logan.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/apbps2.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/charrom_package.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/charrom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/apbvga.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/svgactrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/spictrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/i2cslv.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/wild.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/wild2ahb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grsysmon.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/gracectrl.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grgpreg.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbmst2.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/net/net.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/uart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/libdcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/apbuart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/dcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/dcom_uart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/uart/ahbuart.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/jtag.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/jtagcom.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/greth.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/greth_gbit.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/greth/grethm.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrspa.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
sh mkdir synopsys/esa
define_design_lib esa -path synopsys/esa
analyze -f VHDL -library esa ../../lib/esa/memoryctrl/memoryctrl.vhd
analyze -f VHDL -library esa ../../lib/esa/memoryctrl/mctrl.vhd
sh mkdir synopsys/fmf
define_design_lib fmf -path synopsys/fmf
sh mkdir synopsys/spansion
define_design_lib spansion -path synopsys/spansion
sh mkdir synopsys/gsi
define_design_lib gsi -path synopsys/gsi
sh mkdir synopsys/lpp
define_design_lib lpp -path synopsys/lpp
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Adder.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/ALU.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MUX2.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/REG.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Shifter.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/UART.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
sh mkdir synopsys/cypress
define_design_lib cypress -path synopsys/cypress
sh mkdir synopsys/hynix
define_design_lib hynix -path synopsys/hynix
sh mkdir synopsys/micron
define_design_lib micron -path synopsys/micron
sh mkdir synopsys/work
define_design_lib work -path synopsys/work