HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/EGSE_ICI/MajF_Gen.vhd

Update Sample transformation from ADC to IIR_FILTER

Alexis Jeandet - - Load All Authors

File last commit:

r222:b37e19fe4c0b alexis


                r347:326fa6e96475

Download file

             MajF_Gen.vhd
        
                    48 lines
            
             | 1.1 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / designs / EGSE_ICI / MajF_Gen.vhd
          
                    History
                
                 |
                  Source
                 | Raw
                 |Copy content
                 |Copy permalink

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
      -- MajF_Gen.vhd

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      entity MajF_Gen is 

      generic(WordCnt : integer :=144;MinFCount   :   integer := 64);

      port(

          clk         :   in  std_logic;

          reset       :   in  std_logic;

          WordCnt_in  :   in  integer range 0 to WordCnt-1;

          MinfCnt_in  :   in  integer range 0 to MinFCount-1;

          WordClk     :   in  std_logic;

          MajF_Clk    :   out std_logic

      );

      end entity;

      architecture arMajF_Gen of MajF_Gen is

        Alexis Jeandet
    
Fixed bug, now minor and major frame pulses have the good width....

              r222
            
      signal monostable : std_logic := '0';

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
      begin

      process(clk)

      begin

          if reset = '0' then

              MajF_Clk    <=  '0';

        Alexis Jeandet
    
Fixed bug, now minor and major frame pulses have the good width....

              r222
            
              monostable  <=  '1';

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
          elsif clk'event and clk = '0' then

        Alexis Jeandet
    
Fixed bug, now minor and major frame pulses have the good width....

              r222
            
              if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
                  MajF_Clk    <=  '1';

              else

                  MajF_Clk    <=  '0';

              end if;

        Alexis Jeandet
    
Fixed bug, now minor and major frame pulses have the good width....

              r222
            
              if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then

                  monostable  <=  '0';

              elsif WordCnt_in /= 0  and monostable = '0' then

                  monostable  <=  '1';

              end if;

        Alexis Jeandet
    
ICI4 EGSE now working, need some more cleaning.

              r219
            
          end if;

      end process;

      end architecture;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219	-- MajF_Gen.vhd
		library IEEE;
		use IEEE.std_logic_1164.all;
		use IEEE.numeric_std.all;



		entity MajF_Gen is
		generic(WordCnt : integer :=144;MinFCount : integer := 64);
		port(
		clk : in std_logic;
		reset : in std_logic;
		WordCnt_in : in integer range 0 to WordCnt-1;
		MinfCnt_in : in integer range 0 to MinFCount-1;
		WordClk : in std_logic;
		MajF_Clk : out std_logic
		);
		end entity;






		architecture arMajF_Gen of MajF_Gen is
Alexis Jeandet Fixed bug, now minor and major frame pulses have the good width....	r222	signal monostable : std_logic := '0';
Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219
		begin

		process(clk)
		begin
		if reset = '0' then
		MajF_Clk <= '0';
Alexis Jeandet Fixed bug, now minor and major frame pulses have the good width....	r222	monostable <= '1';
Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219	elsif clk'event and clk = '0' then
Alexis Jeandet Fixed bug, now minor and major frame pulses have the good width....	r222	if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219	MajF_Clk <= '1';
		else
		MajF_Clk <= '0';
		end if;
Alexis Jeandet Fixed bug, now minor and major frame pulses have the good width....	r222	if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
		monostable <= '0';
		elsif WordCnt_in /= 0 and monostable = '0' then
		monostable <= '1';
		end if;
Alexis Jeandet ICI4 EGSE now working, need some more cleaning.	r219	end if;
		end process;

		end architecture;