HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · tests/LFR_time_managment/Makefile

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

Alexis Jeandet - - Load All Authors

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        Alexis Jeandet
    
Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

              r655
            
      VHDLIB=../..

      SCRIPTSDIR=$(VHDLIB)/scripts/

      GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)

      TOP=testbench

      BOARD=LFR-EQM

      include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc

      DEVICE=$(PART)-$(PACKAGE)$(SPEED)

      UCF=

      QSF=

      EFFORT=high

      XSTOPT=

      SYNPOPT=

      VHDLSYNFILES=

      VHDLSIMFILES= tb.vhd

      SIMTOP=TB

      CLEAN=soft-clean

      TECHLIBS = axcelerator

      LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \

      	tmtc openchip hynix ihp gleichmann micron usbhc  opencores fmf ftlib gsi

      DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \

      	pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \

      	grlfpc \

      	./dsp/lpp_fft_rtax \

      	./amba_lcd_16x2_ctrlr \

      	./general_purpose/lpp_AMR \

      	./general_purpose/lpp_balise \

      	./general_purpose/lpp_delay \

      	./lpp_bootloader \

      	./lpp_sim/CY7C1061DV33 \

      	./lpp_uart \

      	./lpp_usb \

      	./dsp/lpp_fft \

      	./lpp_leon3_soc \

      	./lpp_debug_lfr

      FILESKIP = i2cmst.vhd \

      	APB_MULTI_DIODE.vhd \

      	APB_MULTI_DIODE.vhd \

      	Top_MatrixSpec.vhd \

      	APB_FFT.vhd \

      	lpp_lfr_ms_FFT.vhd \

      	lpp_lfr_apbreg.vhd \

      	CoreFFT.vhd \

      	lpp_lfr_ms.vhd \

      	lpp_lfr_sim_pkg.vhd \

      	mtie_maps.vhd \

      	ftsrctrlc.vhd \

      	ftsdctrl.vhd \

      	ftsrctrl8.vhd \

      	ftmctrl.vhd \

      	ftsdctrl64.vhd \

      	ftahbram.vhd \

      	ftahbram2.vhd \

      	sramft.vhd \

      	nandfctrlx.vhd

      include $(GRLIB)/bin/Makefile

      include $(GRLIB)/software/leon3/Makefile

      ##################  project specific targets ##########################

      distclean:myclean

      vsim:cp_for_vsim

      myclean:

      	rm -f input.txt output_fx.txt *.log

      	rm -rf ./2016*

      generate :

      #	python ./generate.py

      cp_for_vsim: generate

      #	cp ./input.txt simulation/

      archivate:

      	xonsh ./archivate.xsh

      test: | generate ghdl ghdl-run archivate

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Alexis Jeandet Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...	r655	VHDLIB=../..
		SCRIPTSDIR=$(VHDLIB)/scripts/
		GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
		TOP=testbench
		BOARD=LFR-EQM
		include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
		DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		UCF=
		QSF=
		EFFORT=high
		XSTOPT=
		SYNPOPT=
		VHDLSYNFILES=
		VHDLSIMFILES= tb.vhd
		SIMTOP=TB
		CLEAN=soft-clean

		TECHLIBS = axcelerator

		LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi

		DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
		pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
		grlfpc \
		./dsp/lpp_fft_rtax \
		./amba_lcd_16x2_ctrlr \
		./general_purpose/lpp_AMR \
		./general_purpose/lpp_balise \
		./general_purpose/lpp_delay \
		./lpp_bootloader \
		./lpp_sim/CY7C1061DV33 \
		./lpp_uart \
		./lpp_usb \
		./dsp/lpp_fft \
		./lpp_leon3_soc \
		./lpp_debug_lfr

		FILESKIP = i2cmst.vhd \
		APB_MULTI_DIODE.vhd \
		APB_MULTI_DIODE.vhd \
		Top_MatrixSpec.vhd \
		APB_FFT.vhd \
		lpp_lfr_ms_FFT.vhd \
		lpp_lfr_apbreg.vhd \
		CoreFFT.vhd \
		lpp_lfr_ms.vhd \
		lpp_lfr_sim_pkg.vhd \
		mtie_maps.vhd \
		ftsrctrlc.vhd \
		ftsdctrl.vhd \
		ftsrctrl8.vhd \
		ftmctrl.vhd \
		ftsdctrl64.vhd \
		ftahbram.vhd \
		ftahbram2.vhd \
		sramft.vhd \
		nandfctrlx.vhd

		include $(GRLIB)/bin/Makefile
		include $(GRLIB)/software/leon3/Makefile

		################## project specific targets ##########################
		distclean:myclean
		vsim:cp_for_vsim

		myclean:
		rm -f input.txt output_fx.txt *.log
		rm -rf ./2016*

		generate :
		# python ./generate.py

		cp_for_vsim: generate
		# cp ./input.txt simulation/

		archivate:
		xonsh ./archivate.xsh

		test: \| generate ghdl ghdl-run archivate