HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/EGSE_ICI/config.vhd

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory...

Moved Validation_LFR_TIME_MANAGEMENT from designs to tests directory Changed test directory Validation_LFR_TIME_MANAGEMENT in LFR_time_management. Added LFR_MANAGMENT_TIME_FINE_DELTA register into apb_lfr_management module at address 0x30 : * LFR_MANAGMENT_TIME_FINE_DELTA ( 8 downto 0) : ft_counter_lsb value * LFR_MANAGMENT_TIME_FINE_DELTA (24 downto 9) : ft value * LFR_MANAGMENT_TIME_FINE_DELTA (26 downto 25) : + ft_counter_lsb_MAX_VALUE = 379 when "00" + ft_counter_lsb_MAX_VALUE = 380 when "01" + ft_counter_lsb_MAX_VALUE = 381 when "10" Updated LFR_time_managment testbench.

Alexis Jeandet - - Load All Authors

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        Alexis Jeandet
    
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

              r217
            
      -----------------------------------------------------------------------------

      -- LEON3 Demonstration design test bench configuration

      -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research

      --

      -- This program is free software; you can redistribute it and/or modify

      -- it under the terms of the GNU General Public License as published by

      -- the Free Software Foundation; either version 2 of the License, or

      -- (at your option) any later version.

      --

      -- This program is distributed in the hope that it will be useful,

      -- but WITHOUT ANY WARRANTY; without even the implied warranty of

      -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

      -- GNU General Public License for more details.

      ------------------------------------------------------------------------------

      library techmap;

      use techmap.gencomp.all;

      package config is

      -- Technology and synthesis options

        constant CFG_FABTECH : integer := apa3;

        constant CFG_MEMTECH : integer := apa3;

        constant CFG_PADTECH : integer := inferred;

        constant CFG_NOASYNC : integer := 0;

        constant CFG_SCAN : integer := 0;

      -- Clock generator

        Alexis Jeandet
    
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....

              r220
            
        constant CFG_CLKTECH : integer := apa3;

        constant CFG_CLKMUL : integer := (25);

        constant CFG_CLKDIV : integer := (9);

        constant CFG_OCLKDIV : integer := (4);

        Alexis Jeandet
    
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

              r217
            
        constant CFG_PCIDLL : integer := 0;

        constant CFG_PCISYSCLK: integer := 0;

        constant CFG_CLK_NOFB : integer := 0;

        Alexis Jeandet
    
ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....

              r220
            
        constant BOARDFREQ : integer := 48000;

        Alexis Jeandet
    
Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.

              r217
            
      end;

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Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217	-----------------------------------------------------------------------------
		-- LEON3 Demonstration design test bench configuration
		-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 2 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		------------------------------------------------------------------------------


		library techmap;
		use techmap.gencomp.all;

		package config is


		-- Technology and synthesis options
		constant CFG_FABTECH : integer := apa3;
		constant CFG_MEMTECH : integer := apa3;
		constant CFG_PADTECH : integer := inferred;
		constant CFG_NOASYNC : integer := 0;
		constant CFG_SCAN : integer := 0;

		-- Clock generator
Alexis Jeandet ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....	r220	constant CFG_CLKTECH : integer := apa3;
		constant CFG_CLKMUL : integer := (25);
		constant CFG_CLKDIV : integer := (9);
		constant CFG_OCLKDIV : integer := (4);
Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217	constant CFG_PCIDLL : integer := 0;
		constant CFG_PCISYSCLK: integer := 0;
		constant CFG_CLK_NOFB : integer := 0;
Alexis Jeandet ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....	r220	constant BOARDFREQ : integer := 48000;
Alexis Jeandet Added simple FX2LP driver to write in endpoint 6 in 8 bit mode.	r217

		end;