debug.vhd
53 lines
| 1.8 KiB
| text/x-vhdl
|
VhdlLexer
martin
|
r100 | ------------------------------------------------------------------------------ | ||
| -- This file is a part of the GRLIB VHDL IP LIBRARY | ||||
| -- Copyright (C) 2003 - 2008, Gaisler Research | ||||
| -- Copyright (C) 2008 - 2010, Aeroflex Gaisler | ||||
| -- | ||||
| -- This program is free software; you can redistribute it and/or modify | ||||
| -- it under the terms of the GNU General Public License as published by | ||||
| -- the Free Software Foundation; either version 2 of the License, or | ||||
| -- (at your option) any later version. | ||||
| -- | ||||
| -- This program is distributed in the hope that it will be useful, | ||||
| -- but WITHOUT ANY WARRANTY; without even the implied warranty of | ||||
| -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||||
| -- GNU General Public License for more details. | ||||
| -- | ||||
| -- You should have received a copy of the GNU General Public License | ||||
| -- along with this program; if not, write to the Free Software | ||||
| -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||||
| ----------------------------------------------------------------------------- | ||||
| -- Entity: debug | ||||
| -- File: debug.vhd | ||||
| -- Author: Jiri Gaisler, Gaisler Research | ||||
| -- Description: Various debug utilities | ||||
| ------------------------------------------------------------------------------ | ||||
| library ieee; | ||||
| use ieee.std_logic_1164.all; | ||||
| library grlib; | ||||
| use grlib.amba.all; | ||||
| package debug is | ||||
| component grtestmod | ||||
| generic ( | ||||
| halt : integer := 0; | ||||
| width : integer := 32); | ||||
| port ( | ||||
| resetn : in std_ulogic; | ||||
| clk : in std_ulogic; | ||||
| errorn : in std_ulogic; | ||||
| address : in std_logic_vector(21 downto 2); | ||||
| data : inout std_logic_vector(width-1 downto 0); | ||||
| iosn : in std_ulogic; | ||||
| oen : in std_ulogic; | ||||
| writen : in std_ulogic; | ||||
| brdyn : out std_ulogic; | ||||
| bexcn : out std_ulogic | ||||
| ); | ||||
| end component; | ||||
| end; | ||||