HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · designs/ProjetBlanc-LeonLPP-A3PE3kL/top_synplify_win32.npl

temp

Alexis Jeandet - - Load All Authors

File last commit:

r181:2a5b3fda6e52 alexis


                r249:279a122aaba5

Download file

             top_synplify_win32.npl
        
                    18 lines
            
             | 708 B
            
                | text/plain
            
             |
                TextLexer

/ designs / ProjetBlanc-LeonLPP-A3PE3kL / top_synplify_win32.npl

History | Source | Raw |Copy content |Copy permalink

martin Mise a jour Projets blanc	r100	JDF G
		PROJECT top
		DESIGN top
		DEVFAM PROASIC3
		DEVICE A3PE3000L
		DEVSPEED Std
		DEVPKG ""
		DEVTOPLEVELMODULETYPE EDIF
		DEVSIMULATOR Modelsim
		DEVGENERATEDSIMULATIONMODEL VHDL
		SOURCE synplify\top.edf
Alexis Jeandet Sync	r181	DEPASSOC top C:\opt\grlib-gpl-1.1.0-b4108\boards\LeonLPP-A3PE3kL\top.ucf
martin Mise a jour Projets blanc	r100	[Normal]
		xilxMapAllowLogicOpt=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
		xilxMapCoverMode=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Speed
		xilxNgdbld_AUL=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, True
		xilxPAReffortLevel=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1102861051, Medium
Alexis Jeandet Sync	r181	xilxNgdbldMacro=edif, PROASIC3, EDIF.t_placeAndRouteDes, 1105378344, C:\opt\grlib-gpl-1.1.0-b4108\netlists\xilinx\PROASIC3

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages