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r181:2a5b3fda6e52 alexis
r249:279a122aaba5 JC
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top_synplify.prj
31 lines | 781 B | text/plain | TextLexer
martin
Mise a jour Projets blanc
r100 source compile.synp
add_file -vhdl -lib work config.vhd
add_file -vhdl -lib work ahbrom.vhd
add_file -vhdl -lib work leon3mp.vhd
Alexis Jeandet
Sync
r181 add_file -constraint C:/opt/grlib-gpl-1.1.0-b4108/boards/LeonLPP-A3PE3kL/synplify.sdc
martin
Mise a jour Projets blanc
r100
#implementation: "synplify"
impl -add synplify
#device options
set_option -technology PROASIC3
set_option -part A3PE3000L
set_option -speed_grade Std
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -write_vhdl 1
#set_option -disable_io_insertion 0
#map options
set_option -frequency 50
set_option -top_module top
#set result format/file last
project -result_file "synplify/top.edf"
#implementation attributes
set_option -package ""
set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0
impl -active "synplify"