HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Files · lib/lpp/lpp_matrix/Dispatch.vhd

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             Dispatch.vhd
        
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        martin
    
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      ------------------------------------------------------------------------------

      --  This file is a part of the LPP VHDL IP LIBRARY

      --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS

      --

      --  This program is free software; you can redistribute it and/or modify

      --  it under the terms of the GNU General Public License as published by

      --  the Free Software Foundation; either version 3 of the License, or

      --  (at your option) any later version.

      --

      --  This program is distributed in the hope that it will be useful,

      --  but WITHOUT ANY WARRANTY; without even the implied warranty of

      --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

      --  GNU General Public License for more details.

      --

      --  You should have received a copy of the GNU General Public License

      --  along with this program; if not, write to the Free Software

      --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

      -------------------------------------------------------------------------------

      --                    Author : Martin Morlot

      --                   Mail : martin.morlot@lpp.polytechnique.fr

      -------------------------------------------------------------------------------

      library IEEE;

      use IEEE.numeric_std.all;

      use IEEE.std_logic_1164.all;

      entity Dispatch is

      generic(

          Data_SZ  : integer := 32);

      port(

          clk         : in std_logic;

          reset       : in std_logic;

          Acq         : in std_logic;

          Data        : in std_logic_vector(Data_SZ-1 downto 0);

          Write       : in std_logic;

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          Valid       : in std_logic;

      --    Full        : in std_logic_vector(1 downto 0);

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          FifoData    : out std_logic_vector(2*Data_SZ-1 downto 0);

          FifoWrite   : out std_logic_vector(1 downto 0);

          Pong        : out std_logic;

          Error       : out std_logic

      );

      end entity;

      architecture ar_Dispatch of Dispatch is

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      type etat is (eX,e0,e1,e2);

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      signal ect : etat;

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      signal Pong_int : std_logic;

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      --signal FifoCpt : integer range 0 to 1 := 0;

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      begin

       process (clk,reset)

          begin

              if(reset='0')then

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                  Pong_int    <= '0';

                  Error   <= '0';

                  ect <= e0;   

        martin
    
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              elsif(clk' event and clk='1')then

                  case ect is

                      when e0 =>

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      --                    if(Full(FifoCpt) = '1')then

                          if(Valid = '1')then

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                              Pong_int <= not Pong_int;

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                              ect <= e1;

                          end if;

                      when e1 =>

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                          if(Acq = '0')then

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                              Error <= '1';

                              ect <= e1;

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                          else

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                              Error <= '0';

                              ect <= e0;

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                          end if;                  

                      when others =>

                          null;  

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                  end case;

              end if;

          end process;

      FifoData <= Data & Data;

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      Pong <= Pong_int;

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      --FifoCpt <= 0 when Pong_int='0' else 1;

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      FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';

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      end architecture;

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martin Débug de la FIFO...	r103	------------------------------------------------------------------------------
		-- This file is a part of the LPP VHDL IP LIBRARY
		-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		--
		-- This program is free software; you can redistribute it and/or modify
		-- it under the terms of the GNU General Public License as published by
		-- the Free Software Foundation; either version 3 of the License, or
		-- (at your option) any later version.
		--
		-- This program is distributed in the hope that it will be useful,
		-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		-- GNU General Public License for more details.
		--
		-- You should have received a copy of the GNU General Public License
		-- along with this program; if not, write to the Free Software
		-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		-------------------------------------------------------------------------------
		-- Author : Martin Morlot
		-- Mail : martin.morlot@lpp.polytechnique.fr
		-------------------------------------------------------------------------------
		library IEEE;
		use IEEE.numeric_std.all;
		use IEEE.std_logic_1164.all;

		entity Dispatch is
		generic(
		Data_SZ : integer := 32);
		port(
		clk : in std_logic;
		reset : in std_logic;
		Acq : in std_logic;
		Data : in std_logic_vector(Data_SZ-1 downto 0);
		Write : in std_logic;
martin UP	r175	Valid : in std_logic;
		-- Full : in std_logic_vector(1 downto 0);
martin Débug de la FIFO...	r103	FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
		FifoWrite : out std_logic_vector(1 downto 0);
		Pong : out std_logic;
		Error : out std_logic
		);
		end entity;


		architecture ar_Dispatch of Dispatch is

martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	type etat is (eX,e0,e1,e2);
martin Débug de la FIFO...	r103	signal ect : etat;

martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	signal Pong_int : std_logic;
martin UP	r175	--signal FifoCpt : integer range 0 to 1 := 0;
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109
martin Débug de la FIFO...	r103	begin

		process (clk,reset)
		begin
		if(reset='0')then
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	Pong_int <= '0';
		Error <= '0';
		ect <= e0;
martin Débug de la FIFO...	r103
		elsif(clk' event and clk='1')then

		case ect is

		when e0 =>
martin UP	r175	-- if(Full(FifoCpt) = '1')then
		if(Valid = '1')then
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	Pong_int <= not Pong_int;
martin Débug de la FIFO...	r103	ect <= e1;
		end if;

		when e1 =>
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	if(Acq = '0')then
martin Débug de la FIFO...	r103	Error <= '1';
		ect <= e1;
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	else
martin Débug de la FIFO...	r103	Error <= '0';
		ect <= e0;
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	end if;

		when others =>
		null;
martin Débug de la FIFO...	r103
		end case;

		end if;
		end process;

		FifoData <= Data & Data;
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109	Pong <= Pong_int;
martin Débug de la FIFO...	r103
martin UP	r175	--FifoCpt <= 0 when Pong_int='0' else 1;
martin Chaine de traitement sur 5 voies (FFT + MATRIX) OKAI	r109
		FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
martin Débug de la FIFO...	r103
		end architecture;