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1 | #------------------------------------------------- | |||
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2 | # | |||
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3 | # Project created by QtCreator 2014-08-23T00:04:05 | |||
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4 | # | |||
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5 | #------------------------------------------------- | |||
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6 | ||||
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7 | QT += core gui | |||
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8 | greaterThan(QT_MAJOR_VERSION, 4): QT += widgets | |||
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9 | ||||
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10 | TARGET = VHDL_TreeWidget | |||
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11 | ||||
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12 | DESTDIR = ../../bin | |||
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13 | ||||
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14 | TEMPLATE = app | |||
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15 | ||||
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16 | INCLUDEPATH += \ | |||
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17 | $$DESTDIR/../vhdlparser \ | |||
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18 | ../../vhdlparser | |||
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19 | ||||
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20 | ||||
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21 | LIBS += -lfl -L${DESTDIR} -lvhdlparser | |||
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22 | ||||
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23 | SOURCES += main.cpp\ | |||
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24 | mainwindow.cpp | |||
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25 | ||||
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26 | HEADERS += mainwindow.h | |||
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27 | ||||
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28 | FORMS += mainwindow.ui |
@@ -0,0 +1,11 | |||||
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1 | #include "mainwindow.h" | |||
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2 | #include <QApplication> | |||
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3 | ||||
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4 | int main(int argc, char *argv[]) | |||
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5 | { | |||
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6 | QApplication a(argc, argv); | |||
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7 | MainWindow w; | |||
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8 | w.show(); | |||
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9 | ||||
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10 | return a.exec(); | |||
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11 | } |
@@ -0,0 +1,111 | |||||
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1 | #include "mainwindow.h" | |||
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2 | #include "ui_mainwindow.h" | |||
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3 | #include <QFileDialog> | |||
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4 | #include <QTreeWidget> | |||
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5 | #include <QTreeWidgetItem> | |||
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6 | ||||
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7 | MainWindow::MainWindow(QWidget *parent) : | |||
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8 | QMainWindow(parent), | |||
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9 | ui(new Ui::MainWindow) | |||
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10 | { | |||
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11 | ui->setupUi(this); | |||
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12 | connect(this->ui->actionOpen,SIGNAL(triggered()),this,SLOT(openFile())); | |||
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13 | connect(this->ui->actionScan_Folder,SIGNAL(triggered()),this,SLOT(openFolder())); | |||
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14 | this->file = new VHDL_Tools::VHDL_File; | |||
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15 | this->rootNode = NULL; | |||
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16 | } | |||
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17 | ||||
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18 | MainWindow::~MainWindow() | |||
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19 | { | |||
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20 | delete ui; | |||
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21 | } | |||
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22 | ||||
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23 | void MainWindow::openFile() | |||
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24 | { | |||
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25 | QString fileName = QFileDialog::getOpenFileName(this, | |||
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26 | tr("Open VHDL file"), NULL, tr("VHDL Files (*.vhd)")); | |||
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27 | if(fileName!="") | |||
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28 | { | |||
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29 | parseFile(fileName,true); | |||
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30 | this->rootNode=file->getParseTree(); | |||
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31 | updateTree(rootNode); | |||
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32 | } | |||
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33 | } | |||
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34 | ||||
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35 | void MainWindow::openFolder() | |||
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36 | { | |||
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37 | QString dir = QFileDialog::getExistingDirectory(this, tr("Open Directory"), | |||
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38 | NULL, | |||
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39 | QFileDialog::ShowDirsOnly | |||
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40 | | QFileDialog::DontResolveSymlinks); | |||
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41 | if(dir!="") | |||
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42 | { | |||
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43 | this->rootNode=new VHDL_Tools::VHDL_AST_Node(dir,VHDL_Tools::virtualGroup); | |||
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44 | parseDirectory(dir); | |||
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45 | updateTree(this->rootNode); | |||
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46 | } | |||
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47 | } | |||
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48 | ||||
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49 | ||||
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50 | void MainWindow::updateTree(VHDL_Tools::VHDL_AST_Node *rootNode) | |||
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51 | { | |||
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52 | this->ui->VHDLtreeWidget->clear(); | |||
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53 | if(rootNode) | |||
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54 | { | |||
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55 | QTreeWidgetItem* item = new QTreeWidgetItem(QStringList()<<rootNode->a_value); | |||
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56 | for(int i=0;i<rootNode->childs.count();i++) | |||
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57 | { | |||
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58 | printNode(rootNode->childs.at(i),item); | |||
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59 | } | |||
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60 | this->ui->VHDLtreeWidget->addTopLevelItem(item); | |||
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61 | } | |||
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62 | } | |||
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63 | ||||
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64 | void MainWindow::printNode(VHDL_Tools::VHDL_AST_Node *rootNode, QTreeWidgetItem *parent) | |||
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65 | { | |||
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66 | if(rootNode) | |||
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67 | { | |||
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68 | QTreeWidgetItem* item = new QTreeWidgetItem(parent,QStringList()<<rootNode->a_value); | |||
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69 | for(int i=0;i<rootNode->childs.count();i++) | |||
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70 | { | |||
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71 | printNode(rootNode->childs.at(i),item); | |||
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72 | } | |||
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73 | } | |||
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74 | } | |||
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75 | ||||
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76 | void MainWindow::parseFile(const QString &fileName, bool trashPreviousTree) | |||
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77 | { | |||
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78 | if(fileName!="") | |||
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79 | this->file->parseFile(fileName,trashPreviousTree); | |||
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80 | } | |||
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81 | ||||
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82 | void MainWindow::parseDirectory(const QString &dirName) | |||
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83 | { | |||
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84 | QDir dir(dirName); | |||
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85 | dir.setFilter(QDir::Files | QDir::Hidden | QDir::NoSymLinks); | |||
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86 | QFileInfoList list = dir.entryInfoList(); | |||
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87 | for (int i = 0; i < list.size(); ++i) | |||
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88 | { | |||
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89 | if(list.at(i).isDir()) | |||
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90 | { | |||
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91 | parseDirectory(list.at(i).fileName()); | |||
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92 | } | |||
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93 | else | |||
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94 | { | |||
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95 | if(list.at(i).isFile() && (!list.at(i).completeSuffix().compare("vhd"))) | |||
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96 | { | |||
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97 | parseFile(list.at(i).absoluteFilePath(),false); | |||
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98 | VHDL_Tools::VHDL_AST_Node* parseTree = file->getParseTree(); | |||
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99 | this->rootNode->childs.append(parseTree); | |||
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100 | parseTree->parent = this->rootNode; | |||
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101 | } | |||
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102 | } | |||
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103 | } | |||
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104 | } | |||
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105 | ||||
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106 | ||||
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107 | ||||
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108 | ||||
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109 | ||||
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110 | ||||
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111 |
@@ -0,0 +1,33 | |||||
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1 | #ifndef MAINWINDOW_H | |||
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2 | #define MAINWINDOW_H | |||
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3 | ||||
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4 | #include <QMainWindow> | |||
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5 | #include <vhdl_file.h> | |||
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6 | #include <QTreeWidgetItem> | |||
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7 | ||||
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8 | namespace Ui { | |||
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9 | class MainWindow; | |||
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10 | } | |||
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11 | ||||
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12 | class MainWindow : public QMainWindow | |||
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13 | { | |||
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14 | Q_OBJECT | |||
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15 | ||||
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16 | public: | |||
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17 | explicit MainWindow(QWidget *parent = 0); | |||
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18 | ~MainWindow(); | |||
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19 | ||||
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20 | private slots: | |||
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21 | void openFile(); | |||
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22 | void openFolder(); | |||
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23 | private: | |||
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24 | void updateTree(VHDL_Tools::VHDL_AST_Node* rootNode); | |||
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25 | void printNode(VHDL_Tools::VHDL_AST_Node* rootNode,QTreeWidgetItem* parent); | |||
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26 | void parseFile(const QString& fileName, bool trashPreviousTree=false); | |||
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27 | void parseDirectory(const QString& dirName); | |||
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28 | VHDL_Tools::VHDL_AST_Node* rootNode; | |||
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29 | Ui::MainWindow *ui; | |||
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30 | VHDL_Tools::VHDL_File* file; | |||
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31 | }; | |||
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32 | ||||
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33 | #endif // MAINWINDOW_H |
@@ -0,0 +1,70 | |||||
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1 | <?xml version="1.0" encoding="UTF-8"?> | |||
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2 | <ui version="4.0"> | |||
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3 | <class>MainWindow</class> | |||
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4 | <widget class="QMainWindow" name="MainWindow"> | |||
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5 | <property name="geometry"> | |||
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6 | <rect> | |||
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7 | <x>0</x> | |||
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8 | <y>0</y> | |||
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9 | <width>400</width> | |||
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10 | <height>300</height> | |||
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11 | </rect> | |||
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12 | </property> | |||
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13 | <property name="windowTitle"> | |||
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14 | <string>MainWindow</string> | |||
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15 | </property> | |||
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16 | <widget class="QWidget" name="centralWidget"> | |||
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17 | <layout class="QVBoxLayout" name="verticalLayout"> | |||
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18 | <item> | |||
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19 | <widget class="QTreeWidget" name="VHDLtreeWidget"> | |||
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20 | <column> | |||
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21 | <property name="text"> | |||
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22 | <string notr="true">1</string> | |||
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23 | </property> | |||
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24 | </column> | |||
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25 | </widget> | |||
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26 | </item> | |||
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27 | </layout> | |||
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28 | </widget> | |||
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29 | <widget class="QMenuBar" name="menuBar"> | |||
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30 | <property name="geometry"> | |||
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31 | <rect> | |||
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32 | <x>0</x> | |||
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33 | <y>0</y> | |||
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34 | <width>400</width> | |||
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35 | <height>27</height> | |||
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36 | </rect> | |||
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37 | </property> | |||
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38 | <widget class="QMenu" name="menuFile"> | |||
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39 | <property name="title"> | |||
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40 | <string>File</string> | |||
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41 | </property> | |||
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42 | <addaction name="actionOpen"/> | |||
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43 | <addaction name="actionScan_Folder"/> | |||
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44 | </widget> | |||
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45 | <addaction name="menuFile"/> | |||
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46 | </widget> | |||
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47 | <widget class="QToolBar" name="mainToolBar"> | |||
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48 | <attribute name="toolBarArea"> | |||
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49 | <enum>TopToolBarArea</enum> | |||
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50 | </attribute> | |||
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51 | <attribute name="toolBarBreak"> | |||
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52 | <bool>false</bool> | |||
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53 | </attribute> | |||
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54 | </widget> | |||
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55 | <widget class="QStatusBar" name="statusBar"/> | |||
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56 | <action name="actionOpen"> | |||
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57 | <property name="text"> | |||
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58 | <string>Open</string> | |||
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59 | </property> | |||
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60 | </action> | |||
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61 | <action name="actionScan_Folder"> | |||
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62 | <property name="text"> | |||
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63 | <string>Scan Folder</string> | |||
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64 | </property> | |||
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65 | </action> | |||
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66 | </widget> | |||
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67 | <layoutdefault spacing="6" margin="11"/> | |||
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68 | <resources/> | |||
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69 | <connections/> | |||
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70 | </ui> |
@@ -0,0 +1,261 | |||||
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1 | LIBRARY IEEE; | |||
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2 | USE IEEE.numeric_std.ALL; | |||
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3 | USE IEEE.std_logic_1164.ALL; | |||
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4 | LIBRARY grlib; | |||
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5 | USE grlib.amba.ALL; | |||
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6 | USE grlib.stdlib.ALL; | |||
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7 | LIBRARY techmap; | |||
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8 | USE techmap.gencomp.ALL; | |||
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9 | LIBRARY gaisler; | |||
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10 | USE gaisler.memctrl.ALL; | |||
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11 | USE gaisler.leon3.ALL; | |||
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12 | USE gaisler.uart.ALL; | |||
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13 | USE gaisler.misc.ALL; | |||
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14 | USE gaisler.spacewire.ALL; -- PLE | |||
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15 | LIBRARY esa; | |||
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16 | USE esa.memoryctrl.ALL; | |||
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17 | ||||
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18 | LIBRARY staging; | |||
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19 | USE staging.SOC_LPP_JCP.ALL; | |||
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20 | ||||
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21 | ENTITY MINI_LFR_top IS | |||
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22 | ||||
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23 | PORT ( | |||
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24 | clk_50 : IN STD_LOGIC; | |||
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25 | clk_49 : IN STD_LOGIC; | |||
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26 | reset : IN STD_LOGIC; | |||
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27 | --BPs | |||
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28 | BP0 : IN STD_LOGIC; | |||
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29 | BP1 : IN STD_LOGIC; | |||
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30 | --LEDs | |||
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31 | LED0 : OUT STD_LOGIC; | |||
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32 | LED1 : OUT STD_LOGIC; | |||
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33 | LED2 : OUT STD_LOGIC; | |||
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34 | --UARTs | |||
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35 | TXD1 : IN STD_LOGIC; | |||
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36 | RXD1 : OUT STD_LOGIC; | |||
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37 | nCTS1 : OUT STD_LOGIC; | |||
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38 | nRTS1 : IN STD_LOGIC; | |||
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39 | ||||
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40 | TXD2 : IN STD_LOGIC; | |||
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41 | RXD2 : OUT STD_LOGIC; | |||
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42 | nCTS2 : OUT STD_LOGIC; | |||
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43 | nDTR2 : IN STD_LOGIC; | |||
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44 | nRTS2 : IN STD_LOGIC; | |||
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45 | nDCD2 : OUT STD_LOGIC; | |||
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46 | ||||
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47 | --EXT CONNECTOR | |||
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48 | IO0 : INOUT STD_LOGIC; | |||
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49 | IO1 : INOUT STD_LOGIC; | |||
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50 | IO2 : INOUT STD_LOGIC; | |||
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51 | IO3 : INOUT STD_LOGIC; | |||
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52 | IO4 : INOUT STD_LOGIC; | |||
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53 | IO5 : INOUT STD_LOGIC; | |||
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54 | IO6 : INOUT STD_LOGIC; | |||
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55 | IO7 : INOUT STD_LOGIC; | |||
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56 | IO8 : INOUT STD_LOGIC; | |||
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57 | IO9 : INOUT STD_LOGIC; | |||
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58 | IO10 : INOUT STD_LOGIC; | |||
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59 | IO11 : INOUT STD_LOGIC; | |||
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60 | ||||
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61 | --SPACE WIRE | |||
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62 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |||
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63 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |||
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64 | SPW_NOM_SIN : IN STD_LOGIC; | |||
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65 | SPW_NOM_DOUT : OUT STD_LOGIC; | |||
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66 | SPW_NOM_SOUT : OUT STD_LOGIC; | |||
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67 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |||
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68 | SPW_RED_SIN : IN STD_LOGIC; | |||
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69 | SPW_RED_DOUT : OUT STD_LOGIC; | |||
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70 | SPW_RED_SOUT : OUT STD_LOGIC; | |||
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71 | -- MINI LFR ADC INPUTS | |||
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72 | ADC_nCS : OUT STD_LOGIC; | |||
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73 | ADC_CLK : OUT STD_LOGIC; | |||
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74 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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75 | ||||
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76 | -- SRAM | |||
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77 | SRAM_nWE : OUT STD_LOGIC; | |||
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78 | SRAM_CE : OUT STD_LOGIC; | |||
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79 | SRAM_nOE : OUT STD_LOGIC; | |||
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80 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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81 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |||
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82 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
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83 | ); | |||
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84 | ||||
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85 | END MINI_LFR_top; | |||
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86 | ||||
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87 | ||||
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88 | ARCHITECTURE beh OF MINI_LFR_top IS | |||
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89 | ||||
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90 | type DURATION is range -1E18 to 1E18 | |||
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91 | units | |||
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92 | fs; | |||
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93 | ps = 1000 fs; | |||
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94 | ns = 1000 ps; | |||
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95 | us = 1000 ns; | |||
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96 | ms = 1000 us; | |||
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97 | sec = 1000 ms; | |||
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98 | min = 60 sec; | |||
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99 | end units; | |||
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100 | ||||
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101 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |||
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102 | SIGNAL clk_25 : STD_LOGIC := '0'; | |||
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103 | ----------------------------------------------------------------------------- | |||
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104 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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105 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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106 | -- | |||
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107 | SIGNAL errorn : STD_LOGIC; | |||
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108 | -- UART AHB --------------------------------------------------------------- | |||
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109 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |||
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110 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |||
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111 | ||||
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112 | -- UART APB --------------------------------------------------------------- | |||
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113 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |||
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114 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |||
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115 | -- | |||
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116 | SIGNAL I00_s : STD_LOGIC; | |||
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117 | -- | |||
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118 | CONSTANT NB_APB_SLAVE : INTEGER := 1; | |||
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119 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |||
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120 | CONSTANT NB_AHB_MASTER : INTEGER := 1; | |||
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121 | ||||
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122 | SIGNAL apbi_ext : apb_slv_in_type; | |||
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123 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); | |||
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124 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |||
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125 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); | |||
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126 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |||
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127 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); | |||
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128 | ||||
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129 | BEGIN -- beh | |||
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130 | ||||
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131 | ----------------------------------------------------------------------------- | |||
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132 | -- CLK | |||
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133 | ----------------------------------------------------------------------------- | |||
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134 | ||||
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135 | PROCESS(clk_50) | |||
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136 | BEGIN | |||
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137 | IF clk_50'EVENT AND clk_50 = '1' THEN | |||
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138 | clk_50_s <= NOT clk_50_s; | |||
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139 | END IF; | |||
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140 | END PROCESS; | |||
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141 | ||||
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142 | PROCESS(clk_50_s) | |||
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143 | BEGIN | |||
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144 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |||
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145 | clk_25 <= NOT clk_25; | |||
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146 | END IF; | |||
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147 | END PROCESS; | |||
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148 | ||||
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149 | ----------------------------------------------------------------------------- | |||
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150 | ||||
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151 | PROCESS (clk_25, reset) | |||
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152 | BEGIN -- PROCESS | |||
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153 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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154 | LED0 <= '0'; | |||
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155 | LED1 <= '0'; | |||
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156 | LED2 <= '0'; | |||
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157 | IO1 <= '0'; | |||
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158 | IO2 <= '1'; | |||
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159 | IO3 <= '0'; | |||
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160 | IO4 <= '0'; | |||
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161 | IO5 <= '0'; | |||
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162 | IO6 <= '0'; | |||
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163 | IO7 <= '0'; | |||
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164 | IO8 <= '0'; | |||
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165 | IO9 <= '0'; | |||
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166 | IO10 <= '0'; | |||
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167 | IO11 <= '0'; | |||
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168 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |||
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169 | LED0 <= '0'; | |||
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170 | LED1 <= '1'; | |||
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171 | LED2 <= BP0; | |||
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172 | IO1 <= '1'; | |||
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173 | IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |||
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174 | IO3 <= ADC_SDO(0); | |||
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175 | IO4 <= ADC_SDO(1); | |||
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176 | IO5 <= ADC_SDO(2); | |||
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177 | IO6 <= ADC_SDO(3); | |||
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178 | IO7 <= ADC_SDO(4); | |||
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179 | IO8 <= ADC_SDO(5); | |||
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180 | IO9 <= ADC_SDO(6); | |||
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181 | IO10 <= ADC_SDO(7); | |||
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182 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |||
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183 | END IF; | |||
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184 | END PROCESS; | |||
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185 | ||||
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186 | PROCESS (clk_49, reset) | |||
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187 | BEGIN -- PROCESS | |||
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188 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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189 | I00_s <= '0'; | |||
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190 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge | |||
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191 | I00_s <= NOT I00_s; | |||
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192 | END IF; | |||
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193 | END PROCESS; | |||
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194 | IO0 <= I00_s; | |||
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195 | ||||
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196 | --UARTs | |||
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197 | nCTS1 <= '1'; | |||
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198 | nCTS2 <= '1'; | |||
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199 | nDCD2 <= '1'; | |||
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200 | ||||
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201 | --EXT CONNECTOR | |||
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202 | ||||
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203 | --SPACE WIRE | |||
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204 | SPW_EN <= '0'; -- 0 => off | |||
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205 | ||||
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206 | SPW_NOM_DOUT <= '0'; | |||
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207 | SPW_NOM_SOUT <= '0'; | |||
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208 | SPW_RED_DOUT <= '0'; | |||
|
209 | SPW_RED_SOUT <= '0'; | |||
|
210 | ||||
|
211 | ADC_nCS <= '0'; | |||
|
212 | ADC_CLK <= '0'; | |||
|
213 | ||||
|
214 | ||||
|
215 | leon3_soc_1: leon3_soc_LPP_JCP | |||
|
216 | GENERIC MAP ( | |||
|
217 | fabtech => apa3e, | |||
|
218 | memtech => apa3e, | |||
|
219 | padtech => inferred, | |||
|
220 | clktech => inferred, | |||
|
221 | disas => 0, | |||
|
222 | dbguart => 0, | |||
|
223 | pclow => 2, | |||
|
224 | clk_freq => 25000, | |||
|
225 | NB_CPU => 1, | |||
|
226 | ENABLE_FPU => 0, | |||
|
227 | FPU_NETLIST => 0, | |||
|
228 | ENABLE_DSU => 1, | |||
|
229 | ENABLE_AHB_UART => 1, | |||
|
230 | ENABLE_APB_UART => 1, | |||
|
231 | ENABLE_IRQMP => 1, | |||
|
232 | ENABLE_GPT => 1, | |||
|
233 | NB_AHB_MASTER => NB_AHB_MASTER, | |||
|
234 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |||
|
235 | NB_APB_SLAVE => NB_APB_SLAVE) | |||
|
236 | PORT MAP ( | |||
|
237 | clk => clk_25, | |||
|
238 | rstn => reset, | |||
|
239 | errorn => errorn, | |||
|
240 | ahbrxd => TXD1, | |||
|
241 | ahbtxd => RXD1, | |||
|
242 | urxd1 => TXD2, | |||
|
243 | utxd1 => RXD2, | |||
|
244 | address => SRAM_A, | |||
|
245 | data => SRAM_DQ, | |||
|
246 | nSRAM_BE0 => SRAM_nBE(0), | |||
|
247 | nSRAM_BE1 => SRAM_nBE(1), | |||
|
248 | nSRAM_BE2 => SRAM_nBE(2), | |||
|
249 | nSRAM_BE3 => SRAM_nBE(3), | |||
|
250 | nSRAM_WE => SRAM_nWE, | |||
|
251 | nSRAM_CE => SRAM_CE, | |||
|
252 | nSRAM_OE => SRAM_nOE, | |||
|
253 | ||||
|
254 | apbi_ext => apbi_ext, | |||
|
255 | apbo_ext => apbo_ext, | |||
|
256 | ahbi_s_ext => ahbi_s_ext, | |||
|
257 | ahbo_s_ext => ahbo_s_ext, | |||
|
258 | ahbi_m_ext => ahbi_m_ext, | |||
|
259 | ahbo_m_ext => ahbo_m_ext); | |||
|
260 | ||||
|
261 | END beh; |
@@ -0,0 +1,40 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the VHDL Tools Software | |||
|
3 | -- Copyright (C) 2014, Plasma Physics Laboratory - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@member.fsf.org | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
|
22 | #include "vhdl_ast_node.h" | |||
|
23 | ||||
|
24 | ||||
|
25 | ||||
|
26 | VHDL_Tools::VHDL_AST_Node::VHDL_AST_Node(const QString &value, VHDL_Tools::VHDL_AST_Node_type type, int line, int column) | |||
|
27 | :a_value(value),type(type),line(line),column(column) | |||
|
28 | { | |||
|
29 | ||||
|
30 | } | |||
|
31 | ||||
|
32 | void VHDL_Tools::VHDL_AST_Node::move(VHDL_Tools::VHDL_AST_Node *parentNode) | |||
|
33 | { | |||
|
34 | if(parentNode!=NULL) | |||
|
35 | { | |||
|
36 | this->parent->childs.removeOne(this); | |||
|
37 | parentNode->childs.append(this); | |||
|
38 | this->parent=parentNode; | |||
|
39 | } | |||
|
40 | } |
@@ -0,0 +1,78 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the VHDL Tools Software | |||
|
3 | -- Copyright (C) 2014, Plasma Physics Laboratory - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@member.fsf.org | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
|
22 | #ifndef VHDL_AST_NODE_H | |||
|
23 | #define VHDL_AST_NODE_H | |||
|
24 | #include <QString> | |||
|
25 | #include <QList> | |||
|
26 | ||||
|
27 | namespace VHDL_Tools{ | |||
|
28 | ||||
|
29 | #define closedByEnd 0x100 | |||
|
30 | #define closedBySemicolon 0x200 | |||
|
31 | #define closedByRightParen 0x300 | |||
|
32 | ||||
|
33 | #define IS_CLOSED_BY_END(type) (((type)&0xF00)==closedByEnd) | |||
|
34 | #define IS_CLOSED_BY_SEMICOLON(type) (((type)&0xF00)==closedBySemicolon) | |||
|
35 | #define IS_CLOSED_BY_RIGHTPAREN(type) (((type)&0xF00)==closedByRightParen) | |||
|
36 | ||||
|
37 | #define IS_CLOSED_BY(openType,type) ((type)==ExpectedCloseTypeLookUp[((openType)&0xF00)>>8]) | |||
|
38 | ||||
|
39 | enum VHDL_AST_Node_type { | |||
|
40 | none=0, | |||
|
41 | separator=1, | |||
|
42 | keyword=2, | |||
|
43 | leftParen=3|closedByRightParen, | |||
|
44 | rightParen=4, | |||
|
45 | block=5|closedByEnd, | |||
|
46 | units=6|closedByEnd, | |||
|
47 | entity=7|closedByEnd, | |||
|
48 | clause=8|closedBySemicolon, | |||
|
49 | semicolon=9, | |||
|
50 | colon=10, | |||
|
51 | generic=11, | |||
|
52 | port=12, | |||
|
53 | map=13, | |||
|
54 | endKw=14, | |||
|
55 | virtualGroup=15, | |||
|
56 | identifier=16, | |||
|
57 | literal=17, | |||
|
58 | rootNode=18, | |||
|
59 | comment=19 | |||
|
60 | }; | |||
|
61 | ||||
|
62 | const VHDL_AST_Node_type ExpectedCloseTypeLookUp[]={none,endKw,semicolon,rightParen,none,none,none,none,none,none,none,none,none,none,none,none}; | |||
|
63 | ||||
|
64 | class VHDL_AST_Node | |||
|
65 | { | |||
|
66 | public: | |||
|
67 | VHDL_AST_Node(const QString& value,VHDL_Tools::VHDL_AST_Node_type type,int line=0, int column=0); | |||
|
68 | QString a_value; | |||
|
69 | VHDL_Tools::VHDL_AST_Node_type type; | |||
|
70 | int line; | |||
|
71 | int column; | |||
|
72 | VHDL_Tools::VHDL_AST_Node* parent; | |||
|
73 | QList<VHDL_Tools::VHDL_AST_Node*> childs; | |||
|
74 | void move(VHDL_Tools::VHDL_AST_Node* parentNode); | |||
|
75 | }; | |||
|
76 | } | |||
|
77 | ||||
|
78 | #endif // VHDL_AST_NODE_H |
@@ -0,0 +1,26 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the VHDL Tools Software | |||
|
3 | -- Copyright (C) 2014, Plasma Physics Laboratory - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@member.fsf.org | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
|
22 | #include "vhdl_fragment.h" | |||
|
23 | ||||
|
24 | VHDL_Tools::VHDL_Fragment::VHDL_Fragment() | |||
|
25 | { | |||
|
26 | } |
@@ -0,0 +1,131 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the VHDL Tools Software | |||
|
3 | -- Copyright (C) 2014, Plasma Physics Laboratory - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | -------------------------------------------------------------------------------*/ | |||
|
19 | /*-- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@member.fsf.org | |||
|
21 | ----------------------------------------------------------------------------*/ | |||
|
22 | #ifndef VHDL_FRAGMENT_H | |||
|
23 | #define VHDL_FRAGMENT_H | |||
|
24 | #include "vhdl_ast_node.h" | |||
|
25 | namespace VHDL_Tools { | |||
|
26 | class VHDL_Fragment | |||
|
27 | { | |||
|
28 | public: | |||
|
29 | VHDL_Fragment(); | |||
|
30 | virtual void pushNode(VHDL_Tools::VHDL_AST_Node* node)=0; | |||
|
31 | VHDL_Tools::VHDL_AST_Node* node; | |||
|
32 | }; | |||
|
33 | ||||
|
34 | class VHDL_packaget: public VHDL_Tools::VHDL_Fragment | |||
|
35 | { | |||
|
36 | public: | |||
|
37 | VHDL_packaget() {} | |||
|
38 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
39 | QString name; | |||
|
40 | }; | |||
|
41 | ||||
|
42 | class VHDL_entity: public VHDL_Tools::VHDL_Fragment | |||
|
43 | { | |||
|
44 | public: | |||
|
45 | VHDL_entity() {} | |||
|
46 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
47 | QString name; | |||
|
48 | }; | |||
|
49 | ||||
|
50 | class VHDL_architecture: public VHDL_Tools::VHDL_Fragment | |||
|
51 | { | |||
|
52 | public: | |||
|
53 | VHDL_architecture() {} | |||
|
54 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
55 | QString name; | |||
|
56 | }; | |||
|
57 | ||||
|
58 | class VHDL_component: public VHDL_Tools::VHDL_Fragment | |||
|
59 | { | |||
|
60 | public: | |||
|
61 | VHDL_component() {} | |||
|
62 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
63 | QString name; | |||
|
64 | }; | |||
|
65 | ||||
|
66 | class VHDL_Library: public VHDL_Tools::VHDL_Fragment | |||
|
67 | { | |||
|
68 | public: | |||
|
69 | VHDL_Library() {} | |||
|
70 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
71 | QString name; | |||
|
72 | }; | |||
|
73 | ||||
|
74 | class VHDL_useClose: public VHDL_Tools::VHDL_Fragment | |||
|
75 | { | |||
|
76 | public: | |||
|
77 | VHDL_useClose() {} | |||
|
78 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
79 | QString name; | |||
|
80 | }; | |||
|
81 | ||||
|
82 | class VHDL_generic: public VHDL_Tools::VHDL_Fragment | |||
|
83 | { | |||
|
84 | public: | |||
|
85 | VHDL_generic() {} | |||
|
86 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
87 | QString name; | |||
|
88 | }; | |||
|
89 | ||||
|
90 | class VHDL_port: public VHDL_Tools::VHDL_Fragment | |||
|
91 | { | |||
|
92 | public: | |||
|
93 | VHDL_port() {} | |||
|
94 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
95 | QString name; | |||
|
96 | }; | |||
|
97 | ||||
|
98 | class VHDL_type: public VHDL_Tools::VHDL_Fragment | |||
|
99 | { | |||
|
100 | public: | |||
|
101 | VHDL_type() {} | |||
|
102 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
103 | QString name; | |||
|
104 | }; | |||
|
105 | ||||
|
106 | class VHDL_subtype: public VHDL_Tools::VHDL_Fragment | |||
|
107 | { | |||
|
108 | public: | |||
|
109 | VHDL_subtype() {} | |||
|
110 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
111 | QString name; | |||
|
112 | }; | |||
|
113 | ||||
|
114 | class VHDL_constant: public VHDL_Tools::VHDL_Fragment | |||
|
115 | { | |||
|
116 | public: | |||
|
117 | VHDL_constant() {} | |||
|
118 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
119 | QString name; | |||
|
120 | }; | |||
|
121 | ||||
|
122 | class VHDL_signal: public VHDL_Tools::VHDL_Fragment | |||
|
123 | { | |||
|
124 | public: | |||
|
125 | VHDL_signal() {} | |||
|
126 | void pushNode(VHDL_Tools::VHDL_AST_Node* node); | |||
|
127 | QString name; | |||
|
128 | }; | |||
|
129 | ||||
|
130 | } | |||
|
131 | #endif // VHDL_FRAGMENT_H |
@@ -18,10 +18,6 TEMPLATE = app | |||||
18 | INCLUDEPATH += \ |
|
18 | INCLUDEPATH += \ | |
19 | $$DESTDIR/../vhdlparser \ |
|
19 | $$DESTDIR/../vhdlparser \ | |
20 | ../../vhdlparser |
|
20 | ../../vhdlparser | |
21 | # ../../../vhdlparser \ |
|
|||
22 | # /opt/build-vhdl_tools-Qt_5_2_1_Syst_me-Debug/vhdlparser |
|
|||
23 |
|
||||
24 | message($$DESTDIR) |
|
|||
25 |
|
21 | |||
26 |
|
22 | |||
27 | LIBS += -lfl -L${DESTDIR} -lvhdlparser |
|
23 | LIBS += -lfl -L${DESTDIR} -lvhdlparser | |
@@ -29,4 +25,5 LIBS += -lfl -L${DESTDIR} -lvhdlparser | |||||
29 | SOURCES += main.cpp |
|
25 | SOURCES += main.cpp | |
30 |
|
26 | |||
31 | OTHER_FILES += \ |
|
27 | OTHER_FILES += \ | |
32 | test1.vhd |
|
28 | test1.vhd\ | |
|
29 | test2.vhd |
@@ -1,3 +1,32 | |||||
|
1 | package test is | |||
|
2 | component ramb4_s16 | |||
|
3 | port ( | |||
|
4 | do : out std_logic_vector (15 downto 0) | |||
|
5 | ); | |||
|
6 | end component; | |||
|
7 | ||||
|
8 | component ramb4_s16 | |||
|
9 | port ( | |||
|
10 | do : out std_logic_vector (15 downto 0) | |||
|
11 | ); | |||
|
12 | end component; | |||
|
13 | ||||
|
14 | end package; | |||
|
15 | ||||
|
16 | package test is | |||
|
17 | component cmp1 | |||
|
18 | port ( | |||
|
19 | do : out std_logic_vector (15 downto 0) | |||
|
20 | ); | |||
|
21 | end component; | |||
|
22 | ||||
|
23 | component cmp2 | |||
|
24 | port ( | |||
|
25 | do : out std_logic_vector (15 downto 0) | |||
|
26 | ); | |||
|
27 | end component; | |||
|
28 | ||||
|
29 | end package; | |||
1 |
|
30 | |||
2 | ------------------------------------------------------------------------------ |
|
31 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
|
32 | -- This file is a part of the GRLIB VHDL IP LIBRARY |
@@ -16,7 +16,8 CONFIG += ordered release | |||||
16 |
|
16 | |||
17 | SUBDIRS += \ |
|
17 | SUBDIRS += \ | |
18 | vhdlparser \ |
|
18 | vhdlparser \ | |
19 | tests/basic_VHDL_parser |
|
19 | tests/basic_VHDL_parser \ | |
|
20 | tests/VHDL_TreeWidget | |||
20 |
|
21 | |||
21 |
|
22 | |||
22 |
|
23 |
@@ -13,8 +13,13 | |||||
13 |
|
13 | |||
14 | /* msvc2010 requires that we exclude this header file. */ |
|
14 | /* msvc2010 requires that we exclude this header file. */ | |
15 | #define YY_NO_UNISTD_H |
|
15 | #define YY_NO_UNISTD_H | |
|
16 | ||||
|
17 | /* handle locations */ | |||
|
18 | int yycolumn = 1; | |||
|
19 | ||||
|
20 | #define YY_USER_ACTION yycolumn += yyleng; | |||
|
21 | ||||
16 | %} |
|
22 | %} | |
17 |
|
||||
18 | %option debug |
|
23 | %option debug | |
19 | %option nodefault |
|
24 | %option nodefault | |
20 | %option yyclass="vhdl_Scanner" |
|
25 | %option yyclass="vhdl_Scanner" | |
@@ -27,12 +32,14 | |||||
27 |
|
32 | |||
28 | /*-----------------------------------------------------------*/ |
|
33 | /*-----------------------------------------------------------*/ | |
29 | /*Separators*/ |
|
34 | /*Separators*/ | |
30 |
[ \t |
|
35 | [ \t]+ { } //skip new lines, blanc spaces and tabulations | |
31 | /*-----------------------------------------------------------*/ |
|
36 | /*-----------------------------------------------------------*/ | |
32 |
|
37 | \n {yycolumn=1;} | ||
33 |
|
38 | |||
34 | /*comment*/ |
|
39 | /*comment*/ | |
35 | --.* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::comment));} |
|
40 | --.* { | |
|
41 | //this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::comment,yylineno, yycolumn-yyleng)); | |||
|
42 | } | |||
36 | /*-----------------------------------------------------------*/ |
|
43 | /*-----------------------------------------------------------*/ | |
37 |
|
44 | |||
38 | /*Reserved words*/ |
|
45 | /*Reserved words*/ | |
@@ -43,45 +50,31 after | | |||||
43 | alias | |
|
50 | alias | | |
44 | all | |
|
51 | all | | |
45 | and | |
|
52 | and | | |
46 | architecture | |
|
|||
47 | array | |
|
53 | array | | |
48 | assert | |
|
54 | assert | | |
49 | attribute | |
|
55 | attribute | | |
50 | begin | |
|
56 | begin | | |
51 | block | |
|
|||
52 | body | |
|
57 | body | | |
53 | buffer | |
|
58 | buffer | | |
54 | bus | |
|
59 | bus | | |
55 | case | |
|
|||
56 | component | |
|
|||
57 | configuration | |
|
|||
58 | constant | |
|
|||
59 | disconnect | |
|
60 | disconnect | | |
60 | downto | |
|
61 | downto | | |
61 | else | |
|
62 | else | | |
62 | elsif | |
|
63 | elsif | | |
63 | end | |
|
|||
64 | entity | |
|
|||
65 | exit | |
|
64 | exit | | |
66 | file | |
|
65 | file | | |
67 | for | |
|
|||
68 | function | |
|
66 | function | | |
69 | generate | |
|
67 | generate | /* don't parse generate as block! just look for "if" or "for" */ | |
70 | generic | |
|
|||
71 | group | |
|
68 | group | | |
72 | guarded | |
|
69 | guarded | | |
73 | if | |
|
|||
74 | impure | |
|
70 | impure | | |
75 | in | |
|
71 | in | | |
76 | inertial | |
|
72 | inertial | | |
77 | inout | |
|
73 | inout | | |
78 | is | |
|
74 | is | | |
79 | label | |
|
75 | label | | |
80 | library | |
|
|||
81 | linkage | |
|
76 | linkage | | |
82 | literal | |
|
77 | literal | | |
83 | loop | |
|
|||
84 | map | |
|
|||
85 | mod | |
|
78 | mod | | |
86 | nand | |
|
79 | nand | | |
87 | new | |
|
80 | new | | |
@@ -95,14 +88,9 open | | |||||
95 | or | |
|
88 | or | | |
96 | others | |
|
89 | others | | |
97 | out | |
|
90 | out | | |
98 | package | |
|
|||
99 | port | |
|
|||
100 | postponed | |
|
91 | postponed | | |
101 | procedure | |
|
|||
102 | process | |
|
|||
103 | pure | |
|
92 | pure | | |
104 | range | |
|
93 | range | | |
105 | record | |
|
|||
106 | register | |
|
94 | register | | |
107 | reject | |
|
95 | reject | | |
108 | rem | |
|
96 | rem | | |
@@ -113,89 +101,100 ror | | |||||
113 | select | |
|
101 | select | | |
114 | severity | |
|
102 | severity | | |
115 | shared | |
|
103 | shared | | |
116 | signal | |
|
|||
117 | sla | |
|
104 | sla | | |
118 | sll | |
|
105 | sll | | |
119 | sra | |
|
106 | sra | | |
120 | srl | |
|
107 | srl | | |
121 | subtype | |
|
|||
122 | then | |
|
108 | then | | |
123 | to | |
|
109 | to | | |
124 | transport | |
|
110 | transport | | |
125 | type | |
|
|||
126 | unaffected | |
|
111 | unaffected | | |
127 | units | |
|
|||
128 | until | |
|
112 | until | | |
129 | use | |
|
|||
130 | variable | |
|
|||
131 | wait | |
|
113 | wait | | |
132 | when | |
|
114 | when | | |
133 | while | |
|
115 | while | | |
134 | with | |
|
116 | with | | |
135 | xnor | |
|
117 | xnor | | |
136 | xor | |
|
118 | xor | | |
137 | (true|false) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::keyword));} |
|
119 | (true|false) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::keyword,yylineno, yycolumn-yyleng));} | |
|
120 | ||||
|
121 | port {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::port,yylineno, yycolumn-yyleng));} | |||
|
122 | ||||
|
123 | generic {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::generic,yylineno, yycolumn-yyleng));} | |||
|
124 | ||||
|
125 | map {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::map,yylineno, yycolumn-yyleng));} | |||
|
126 | ||||
|
127 | architecture | | |||
|
128 | block | | |||
|
129 | case | | |||
|
130 | configuration | | |||
|
131 | component | | |||
|
132 | for | | |||
|
133 | if | | |||
|
134 | loop | | |||
|
135 | package | | |||
|
136 | procedure | | |||
|
137 | process | | |||
|
138 | protected | | |||
|
139 | record { | |||
|
140 | this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::block,yylineno, yycolumn-yyleng)); | |||
|
141 | } | |||
|
142 | ||||
|
143 | entity {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::entity,yylineno, yycolumn-yyleng));} | |||
138 |
|
144 | |||
139 |
|
145 | |||
140 | /* delimiter*/ |
|
146 | units { | |
141 | \. | \| | \[ | \] | |
|
147 | this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::units,yylineno, yycolumn-yyleng)); | |
142 | \:= | \>\= | |
|
148 | } | |
143 | \<\= | |
|
149 | ||
144 | \/\= | |
|
150 | constant | | |
145 | \= | |
|
151 | library | | |
146 | \> | |
|
152 | signal | | |
147 | \< | |
|
153 | subtype | | |
148 | \& | |
|
154 | type | | |
149 | \‘ | |
|
155 | use | | |
150 | \=\> | |
|
156 | variable {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::clause,yylineno, yycolumn-yyleng));} | |
151 | \: | |
|
157 | ||
152 | \<\> | |
|
158 | ||
153 | \; | |
|
159 | ||
154 | \, | |
|
160 | end {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::endKw,yylineno, yycolumn-yyleng));} | |
155 | \( | |
|
|||
156 | \) | |
|
|||
157 | \* | |
|
|||
158 | \+ | |
|
|||
159 | \- | |
|
|||
160 | \/ | |
|
|||
161 | \*\* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::separator)); } |
|
|||
162 |
|
161 | |||
163 |
|
162 | |||
164 | /*-----------------------------------------------------------*/ |
|
163 | /*-----------------------------------------------------------*/ | |
165 |
|
164 | |||
166 | /*identifier (may be a reserved word)*/ |
|
165 | /*identifier (may be a reserved word)*/ | |
167 | [a-z][a-z0-9\_]+[a-z] | |
|
166 | [a-z][a-z0-9\_\.]+[a-z0-9]+ | | |
168 | [a-z]+ | |
|
167 | [a-z]+ | | |
169 | \\.*\\ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::identifier));} |
|
168 | \\.*\\ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::identifier,yylineno, yycolumn-yyleng));} | |
170 |
|
169 | |||
171 | /*-----------------------------------------------------------*/ |
|
170 | /*-----------------------------------------------------------*/ | |
172 |
|
171 | |||
173 | /*abstract literal (integer or floating point type)*/ |
|
172 | /*abstract literal (integer or floating point type)*/ | |
174 | /*Numerical literals*/ |
|
173 | /*Numerical literals*/ | |
175 | (\+|\-)?([0-9\_]+)|(\+|\-)?([0-9\_]+E[0-9\_]+)|((2|3|4|5|6|7|8|9|10|11|12|13|14|15|16)\#[0-9\_]\#) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
174 | (\+|\-)?([0-9\_]+)|(\+|\-)?([0-9\_]+E[0-9\_]+)|((2|3|4|5|6|7|8|9|10|11|12|13|14|15|16)\#[0-9\_]\#) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
176 |
|
175 | |||
177 | (\+|\-)?[0-9\_]+\.[0-9\_]+|[0-9\_]+\.[0-9\_]+E[0-9\_]+ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
176 | (\+|\-)?[0-9\_]+\.[0-9\_]+|[0-9\_]+\.[0-9\_]+E[0-9\_]+ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
178 |
|
177 | |||
179 | \'(0|1)\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
178 | \'(0|1)\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
180 |
|
179 | |||
181 | \'.\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
180 | \'.\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
182 |
|
181 | |||
183 |
|
182 | |||
184 | (\+|\-)?([0-9\_]+)(fs|ps|ns|us|ms|sec|min|hr) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
183 | (\+|\-)?([0-9\_]+)(fs|ps|ns|us|ms|sec|min|hr) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
185 |
|
184 | |||
186 | /*Bit string literals*/ |
|
185 | /*Bit string literals*/ | |
187 | \"[0-1\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
186 | \"[0-1\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
188 |
|
187 | |||
189 | /*String literals*/ |
|
188 | /*String literals*/ | |
190 | \".*\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
189 | \".*\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
191 |
|
190 | |||
192 | x\"[0-9A-F\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
191 | x\"[0-9A-F\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
193 |
|
192 | |||
194 | o\"[0-7\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
193 | o\"[0-7\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
195 |
|
194 | |||
196 | /*The NULL literal*/ |
|
195 | /*The NULL literal*/ | |
197 |
|
196 | |||
198 | \[NULL\] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} |
|
197 | \[NULL\] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal,yylineno, yycolumn-yyleng));} | |
199 |
|
198 | |||
200 | /*-----------------------------------------------------------*/ |
|
199 | /*-----------------------------------------------------------*/ | |
201 |
|
200 | |||
@@ -208,10 +207,39 o\"[0-7\_]+\" {this->appendNode(new VHDL | |||||
208 | /* bit string literal (a sequence of extended digits * surrounded by ”, e.g.: ”011”)*/ |
|
207 | /* bit string literal (a sequence of extended digits * surrounded by ”, e.g.: ”011”)*/ | |
209 | /*-----------------------------------------------------------*/ |
|
208 | /*-----------------------------------------------------------*/ | |
210 |
|
209 | |||
|
210 | /* delimiter*/ | |||
|
211 | \. | \| | \[ | \] | | |||
|
212 | \:= | \>\= | | |||
|
213 | \<\= | | |||
|
214 | \/\= | | |||
|
215 | \= | | |||
|
216 | \> | | |||
|
217 | \< | | |||
|
218 | \& | | |||
|
219 | \‘ | | |||
|
220 | \' | | |||
|
221 | \=\> | | |||
|
222 | \<\> | | |||
|
223 | \, | | |||
|
224 | \* | | |||
|
225 | \+ | | |||
|
226 | \- | | |||
|
227 | \/ | | |||
|
228 | \*\* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::separator,yylineno, yycolumn-yyleng)); } | |||
211 |
|
229 | |||
212 |
|
230 | |||
|
231 | \: {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::colon,yylineno, yycolumn-yyleng)); } | |||
213 |
|
232 | |||
214 |
|
233 | |||
|
234 | \( {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::leftParen,yylineno, yycolumn-yyleng));} | |||
|
235 | ||||
|
236 | \) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::rightParen,yylineno, yycolumn-yyleng));} | |||
|
237 | ||||
|
238 | ||||
|
239 | \; {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::semicolon,yylineno, yycolumn-yyleng)); } | |||
|
240 | ||||
|
241 | . printf("bad input character '%s' at line %d column %d\n ", yytext, yylineno,yycolumn-yyleng); | |||
|
242 | ||||
215 | %% |
|
243 | %% | |
216 |
|
244 | |||
217 |
|
245 |
@@ -22,25 +22,50 | |||||
22 | #include "vhdl_scanner.h" |
|
22 | #include "vhdl_scanner.h" | |
23 | #include <QDebug> |
|
23 | #include <QDebug> | |
24 |
|
24 | |||
25 | VHDL_Tools::vhdl_Scanner::vhdl_Scanner(std::istream *in) |
|
25 | VHDL_Tools::vhdl_Scanner::vhdl_Scanner(std::istream *in, const QString &fileName) | |
26 | : yyFlexLexer(in) |
|
26 | : yyFlexLexer(in) | |
27 | { |
|
27 | { | |
28 |
this->rootNode = new VHDL_Tools::VHDL_AST_Node( |
|
28 | this->rootNode = new VHDL_Tools::VHDL_AST_Node(fileName,VHDL_Tools::rootNode); | |
|
29 | this->currentNode = rootNode; | |||
|
30 | this->rootNode->parent = this->rootNode; | |||
29 | } |
|
31 | } | |
30 |
|
32 | |||
|
33 | VHDL_Tools::vhdl_Scanner::~vhdl_Scanner() | |||
|
34 | { | |||
|
35 | deleteNode(rootNode); | |||
|
36 | } | |||
|
37 | ||||
|
38 | ||||
31 | int VHDL_Tools::vhdl_Scanner::scan() |
|
39 | int VHDL_Tools::vhdl_Scanner::scan() | |
32 | { |
|
40 | { | |
33 | return( yylex() ); |
|
41 | return( yylex() ); | |
34 | } |
|
42 | } | |
35 |
|
43 | |||
36 | void VHDL_Tools::vhdl_Scanner::stackData(QString data) |
|
44 | int VHDL_Tools::vhdl_Scanner::newFile(std::istream *in, const QString &fileName,bool trashPreviousTree) | |
37 | { |
|
45 | { | |
38 | qDebug()<<data; |
|
46 | switch_streams(in); | |
|
47 | if(trashPreviousTree) | |||
|
48 | deleteNode(rootNode); | |||
|
49 | this->rootNode = new VHDL_Tools::VHDL_AST_Node(fileName,VHDL_Tools::rootNode); | |||
|
50 | this->currentNode = rootNode; | |||
|
51 | this->rootNode->parent = this->rootNode; | |||
|
52 | return 1; | |||
39 | } |
|
53 | } | |
40 |
|
54 | |||
|
55 | ||||
41 | void VHDL_Tools::vhdl_Scanner::appendNode(VHDL_Tools::VHDL_AST_Node *node) |
|
56 | void VHDL_Tools::vhdl_Scanner::appendNode(VHDL_Tools::VHDL_AST_Node *node) | |
42 | { |
|
57 | { | |
43 |
this-> |
|
58 | this->currentNode->childs.append(node); | |
|
59 | node->parent = this->currentNode; | |||
|
60 | this->currentNode = node; | |||
44 | } |
|
61 | } | |
45 |
|
62 | |||
46 |
|
63 | void VHDL_Tools::vhdl_Scanner::deleteNode(VHDL_Tools::VHDL_AST_Node *node) | ||
|
64 | { | |||
|
65 | for(int i=0;i<node->childs.count();i++) | |||
|
66 | { | |||
|
67 | deleteNode(node->childs.at(i)); | |||
|
68 | } | |||
|
69 | node->parent->childs.removeAll(node); | |||
|
70 | delete node; | |||
|
71 | } |
@@ -29,35 +29,39 | |||||
29 | #include <fstream> |
|
29 | #include <fstream> | |
30 | #include <QString> |
|
30 | #include <QString> | |
31 | #include <QList> |
|
31 | #include <QList> | |
|
32 | #include <QStack> | |||
|
33 | #include "vhdl_ast_node.h" | |||
|
34 | #include "vhdl_fragment.h" | |||
32 |
|
35 | |||
33 | #undef YY_DECL |
|
36 | #undef YY_DECL | |
34 | #define YY_DECL int VHDL_Tools::vhdl_Scanner::yylex() |
|
37 | #define YY_DECL int VHDL_Tools::vhdl_Scanner::yylex() | |
35 |
|
38 | |||
36 | namespace VHDL_Tools{ |
|
39 | namespace VHDL_Tools{ | |
37 |
|
40 | |||
38 | enum VHDL_AST_Node_type {separator,keyword,identifier,literal,rootNode,comment}; |
|
41 | class vhdl_Scanner_block_stack | |
39 | class VHDL_AST_Node |
|
|||
40 | { |
|
42 | { | |
41 | public: |
|
43 | public: | |
42 | VHDL_AST_Node(const QString& value,VHDL_Tools::VHDL_AST_Node_type type):value(value),type(type) {} |
|
44 | vhdl_Scanner_block_stack(bool waitForSemicolon,bool waitForParen, int delta) | |
43 | QString value; |
|
45 | :waitForSemicolon(waitForSemicolon),waitForParen(waitForParen),stackDelta(delta){} | |
44 | VHDL_Tools::VHDL_AST_Node_type type; |
|
46 | bool waitForSemicolon; | |
45 | VHDL_Tools::VHDL_AST_Node* parent; |
|
47 | bool waitForParen; | |
46 | QList<VHDL_Tools::VHDL_AST_Node*> childs; |
|
48 | int stackDelta; | |
47 | }; |
|
49 | }; | |
48 |
|
50 | |||
49 | class vhdl_Scanner : public yyFlexLexer |
|
51 | class vhdl_Scanner : public yyFlexLexer | |
50 | { |
|
52 | { | |
51 | public: |
|
53 | public: | |
52 | vhdl_Scanner(std::istream *in); |
|
54 | vhdl_Scanner(std::istream *in,const QString& fileName); | |
|
55 | ~vhdl_Scanner(); | |||
53 | int scan(); |
|
56 | int scan(); | |
54 |
|
57 | int newFile(std::istream *in, const QString& fileName, bool trashPreviousTree=false); | ||
|
58 | VHDL_Tools::VHDL_AST_Node* getScanTree(){return rootNode;} | |||
55 | private: |
|
59 | private: | |
56 | /* hide this one from public view */ |
|
60 | /* hide this one from public view */ | |
57 | int yylex(); |
|
61 | int yylex(); | |
58 | void stackData(QString data); |
|
|||
59 | void appendNode(VHDL_Tools::VHDL_AST_Node* node); |
|
62 | void appendNode(VHDL_Tools::VHDL_AST_Node* node); | |
60 |
VHDL_Tools::VHDL_AST_Node* |
|
63 | void deleteNode(VHDL_Tools::VHDL_AST_Node* node); | |
|
64 | VHDL_Tools::VHDL_AST_Node* rootNode,*currentNode; | |||
61 | }; |
|
65 | }; | |
62 | } |
|
66 | } | |
63 |
|
67 |
@@ -1,30 +1,169 | |||||
1 | #include "vhdl_file.h" |
|
1 | #include "vhdl_file.h" | |
2 |
|
2 | #include <QDebug> | ||
3 |
|
3 | |||
4 | VHDL_Tools::VHDL_File::VHDL_File() |
|
4 | VHDL_Tools::VHDL_File::VHDL_File() | |
5 | { |
|
5 | { | |
6 | this->scanner = NULL; |
|
6 | this->scanner = NULL; | |
7 | } |
|
7 | } | |
8 |
|
8 | |||
|
9 | #define walkForward( node , code ) \ | |||
|
10 | if((node)->childs.count())\ | |||
|
11 | {\ | |||
|
12 | (node) = (node)->childs.first();\ | |||
|
13 | }\ | |||
|
14 | else\ | |||
|
15 | {\ | |||
|
16 | return (code);\ | |||
|
17 | }\ | |||
9 |
|
18 | |||
10 | bool VHDL_Tools::VHDL_File::parseFile(const QString &file) |
|
19 | ||
|
20 | #define skipTokens(node,TokenType) while ((node)->type==(TokenType)){walkForward((node),-1);} | |||
|
21 | ||||
|
22 | bool VHDL_Tools::VHDL_File::parseFile(const QString &file, bool trashPreviousTree) | |||
11 | { |
|
23 | { | |
12 | std::ifstream in_file( file.toStdString().c_str() ); |
|
24 | std::ifstream in_file( file.toStdString().c_str() ); | |
13 | if( ! in_file.good() ) return false; |
|
25 | if( ! in_file.good() ) return false; | |
14 | if(scanner) |
|
26 | // if(scanner) | |
15 | delete(scanner); |
|
27 | // delete(scanner); | |
16 | try |
|
28 | // try | |
17 | { |
|
29 | // { | |
18 | scanner = new VHDL_Tools::vhdl_Scanner( &in_file ); |
|
30 | // scanner = new VHDL_Tools::vhdl_Scanner( &in_file ,file); | |
19 | } |
|
31 | // } | |
20 | catch( std::bad_alloc &ba ) |
|
32 | // catch( std::bad_alloc &ba ) | |
|
33 | // { | |||
|
34 | // std::cerr << "Failed to allocate scanner: (" << | |||
|
35 | // ba.what() << ")\n"; | |||
|
36 | // return false; | |||
|
37 | // } | |||
|
38 | if(scanner==NULL) | |||
21 | { |
|
39 | { | |
22 | std::cerr << "Failed to allocate scanner: (" << |
|
40 | try | |
23 | ba.what() << ")\n"; |
|
41 | { | |
24 | return false; |
|
42 | scanner = new VHDL_Tools::vhdl_Scanner( &in_file ,file); | |
|
43 | } | |||
|
44 | catch( std::bad_alloc &ba ) | |||
|
45 | { | |||
|
46 | std::cerr << "Failed to allocate scanner: (" << | |||
|
47 | ba.what() << ")\n"; | |||
|
48 | return false; | |||
|
49 | } | |||
25 | } |
|
50 | } | |
|
51 | scanner->newFile(&in_file,file,trashPreviousTree); | |||
26 | while (scanner->scan()!=0); |
|
52 | while (scanner->scan()!=0); | |
27 | //parse(file.toStdString().c_str()); |
|
53 | makeParseTree(scanner->getScanTree()); | |
28 |
|
||||
29 | return false; |
|
54 | return false; | |
30 | } |
|
55 | } | |
|
56 | ||||
|
57 | VHDL_Tools::VHDL_AST_Node *VHDL_Tools::VHDL_File::getParseTree() | |||
|
58 | { | |||
|
59 | return rootNode; | |||
|
60 | } | |||
|
61 | ||||
|
62 | int VHDL_Tools::VHDL_File::makeParseTree(VHDL_AST_Node *rootNode) | |||
|
63 | { | |||
|
64 | this->rootNode = rootNode; | |||
|
65 | VHDL_AST_Node *currentNode=rootNode; | |||
|
66 | QStack<VHDL_AST_Node*> openBlocks; | |||
|
67 | openBlocks.push(rootNode); | |||
|
68 | while (currentNode) | |||
|
69 | { | |||
|
70 | switch (currentNode->type) | |||
|
71 | { | |||
|
72 | case block: | |||
|
73 | openBlocks.push(currentNode); | |||
|
74 | walkForward(currentNode,-1); | |||
|
75 | break; | |||
|
76 | case entity: | |||
|
77 | //Declaration or instanciation? | |||
|
78 | if(!((currentNode->parent->type == colon) && (currentNode->parent->parent->type==identifier))) | |||
|
79 | { | |||
|
80 | openBlocks.push(currentNode); | |||
|
81 | } | |||
|
82 | walkForward(currentNode,-1); | |||
|
83 | break; | |||
|
84 | case units: | |||
|
85 | if(openBlocks.top()->type==clause) | |||
|
86 | { | |||
|
87 | openBlocks.top()->type=units; | |||
|
88 | walkForward(currentNode,-1); | |||
|
89 | } | |||
|
90 | break; | |||
|
91 | case port: | |||
|
92 | currentNode->type = static_cast<VHDL_AST_Node_type>(currentNode->type | closedBySemicolon); | |||
|
93 | openBlocks.push(currentNode); | |||
|
94 | break; | |||
|
95 | case generic: | |||
|
96 | if(!(currentNode->childs.first()->type==map)) | |||
|
97 | { | |||
|
98 | currentNode->type = static_cast<VHDL_AST_Node_type>(currentNode->type | closedBySemicolon); | |||
|
99 | openBlocks.push(currentNode); | |||
|
100 | } | |||
|
101 | walkForward(currentNode,-1); | |||
|
102 | break; | |||
|
103 | case clause: | |||
|
104 | openBlocks.push(currentNode); | |||
|
105 | walkForward(currentNode,-1); | |||
|
106 | break; | |||
|
107 | case endKw: | |||
|
108 | closeAndMatchBlock(¤tNode,&openBlocks,QList<VHDL_AST_Node_type>()<<units<<block<<identifier,true); | |||
|
109 | break; | |||
|
110 | case leftParen: | |||
|
111 | openBlocks.push(currentNode); | |||
|
112 | walkForward(currentNode,-1); | |||
|
113 | break; | |||
|
114 | case rightParen: | |||
|
115 | if((openBlocks.top()->parent->type==port)||(openBlocks.top()->parent->type==generic)) | |||
|
116 | closeAndMatchBlock(¤tNode,&openBlocks,QList<VHDL_AST_Node_type>(),false); | |||
|
117 | else | |||
|
118 | closeAndMatchBlock(¤tNode,&openBlocks,QList<VHDL_AST_Node_type>(),false); | |||
|
119 | break; | |||
|
120 | case semicolon: | |||
|
121 | if(IS_CLOSED_BY_SEMICOLON(openBlocks.top()->type)) | |||
|
122 | { | |||
|
123 | closeAndMatchBlock(¤tNode,&openBlocks,QList<VHDL_AST_Node_type>(),false); | |||
|
124 | } | |||
|
125 | else | |||
|
126 | { | |||
|
127 | walkForward(currentNode,0); | |||
|
128 | } | |||
|
129 | break; | |||
|
130 | default: | |||
|
131 | walkForward(currentNode,0); | |||
|
132 | break; | |||
|
133 | } | |||
|
134 | } | |||
|
135 | return 0; | |||
|
136 | } | |||
|
137 | ||||
|
138 | int VHDL_Tools::VHDL_File::closeAndMatchBlock(VHDL_Tools::VHDL_AST_Node **currentNode, QStack<VHDL_Tools::VHDL_AST_Node *> *openBlocksContext, QList<VHDL_Tools::VHDL_AST_Node_type> skipTypes, bool endWithSemicolon) | |||
|
139 | { | |||
|
140 | VHDL_AST_Node* startNode = openBlocksContext->pop(); | |||
|
141 | ||||
|
142 | if( IS_CLOSED_BY(startNode->type,(*currentNode)->type)) | |||
|
143 | { | |||
|
144 | walkForward((*currentNode),-1); | |||
|
145 | for(int i=0;i<skipTypes.length();i++) | |||
|
146 | { | |||
|
147 | skipTokens((*currentNode),skipTypes.at(i)); | |||
|
148 | } | |||
|
149 | if(endWithSemicolon && ((*currentNode)->type==semicolon)) | |||
|
150 | { | |||
|
151 | walkForward((*currentNode),-1); | |||
|
152 | (*currentNode)->move(startNode->parent); | |||
|
153 | ||||
|
154 | } | |||
|
155 | else | |||
|
156 | { | |||
|
157 | (*currentNode)->move(startNode->parent); | |||
|
158 | } | |||
|
159 | } | |||
|
160 | else | |||
|
161 | { | |||
|
162 | // TODO improve message ! | |||
|
163 | qDebug() << "Got unexpected close token! @ line:" << (*currentNode)->line << " column:"<< (*currentNode)->column; | |||
|
164 | } | |||
|
165 | return 0; | |||
|
166 | } | |||
|
167 | ||||
|
168 | ||||
|
169 |
@@ -10,10 +10,13 class VHDL_File | |||||
10 |
|
10 | |||
11 | public: |
|
11 | public: | |
12 | VHDL_File(); |
|
12 | VHDL_File(); | |
13 | bool parseFile(const QString& file); |
|
13 | bool parseFile(const QString& file, bool trashPreviousTree=false); | |
14 |
|
14 | VHDL_Tools::VHDL_AST_Node* getParseTree(); | ||
15 | private: |
|
15 | private: | |
16 | VHDL_Tools::vhdl_Scanner *scanner; |
|
16 | VHDL_Tools::vhdl_Scanner *scanner; | |
|
17 | int makeParseTree(VHDL_Tools::VHDL_AST_Node* rootNode); | |||
|
18 | int closeAndMatchBlock(VHDL_Tools::VHDL_AST_Node** currentNode,QStack<VHDL_Tools::VHDL_AST_Node*>* openBlocksContext,QList<VHDL_Tools::VHDL_AST_Node_type>skipTypes,bool endWithSemicolon=false); | |||
|
19 | VHDL_Tools::VHDL_AST_Node* rootNode; | |||
17 | }; |
|
20 | }; | |
18 |
|
21 | |||
19 | } |
|
22 | } |
@@ -23,11 +23,15 INCLUDEPATH += \ | |||||
23 |
|
23 | |||
24 |
|
24 | |||
25 | SOURCES += vhdl_file.cpp \ |
|
25 | SOURCES += vhdl_file.cpp \ | |
26 | scanner/vhdl_scanner.cpp |
|
26 | scanner/vhdl_scanner.cpp \ | |
|
27 | scanner/vhdl_fragment.cpp \ | |||
|
28 | scanner/vhdl_ast_node.cpp | |||
27 |
|
29 | |||
28 | HEADERS += vhdl_file.h\ |
|
30 | HEADERS += vhdl_file.h\ | |
29 | libvhdlparser_global.h \ |
|
31 | libvhdlparser_global.h \ | |
30 | scanner/vhdl_scanner.h |
|
32 | scanner/vhdl_scanner.h \ | |
|
33 | scanner/vhdl_fragment.h \ | |||
|
34 | scanner/vhdl_ast_node.h | |||
31 |
|
35 | |||
32 | unix { |
|
36 | unix { | |
33 | target.path = /usr/lib |
|
37 | target.path = /usr/lib |
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