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1 syntax: glob
2 *~
3 *.a
4 *.so
5 *.o
6 *.pro.user
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1 GNU GENERAL PUBLIC LICENSE
2 Version 2, June 1991
3
4 Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
5 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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299 (at your option) any later version.
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303 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
304 GNU General Public License for more details.
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315 Gnomovision version 69, Copyright (C) year name of author
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317 This is free software, and you are welcome to redistribute it
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330 `Gnomovision' (which makes passes at compilers) written by James Hacker.
331
332 <signature of Ty Coon>, 1 April 1989
333 Ty Coon, President of Vice
334
335 This General Public License does not permit incorporating your program into
336 proprietary programs. If your program is a subroutine library, you may
337 consider it more useful to permit linking proprietary applications with the
338 library. If this is what you want to do, use the GNU Lesser General
339 Public License instead of this License.
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1 VHDL Tools
2 -----------
3
4 TODO:desc
5
6 Licensing
7 ---------
8
9 VHDL Tools is provided under the terms of the GNU General Public License as published by the
10 Free Software Foundation; either version 2 of the License, or (at your option) any
11 later version.
12
13 Wiki
14 ----
15
16 More details [here](https://hephaistos.lpp.polytechnique.fr/redmine/projects/VHDL_tools/wiki)
17
18 How to build
19 ------------
20
21 To build it on linux you can look here https://hephaistos.lpp.polytechnique.fr/redmine/projects/VHDL_tools/wiki/Linux_setup
22
23 If you can't access to it, first you will need a working qt5 kit with all the development packages.
24 Step 1:
25 Get and install VHDL tools
26 ```Bash
27 hg clone https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/VHDL_tools VHDL_tools
28 cd VHDL_tools
29 qmake-qt5
30 make
31 sudo make install
32 ```
33
34
35 Bug repports
36 ------------
37
38 To repport any bug you can either send a [mail](mailto:alexis.jeandet@member.fsf.org) or repport an issue [here](https://hephaistos.lpp.polytechnique.fr/redmine/projects/kicadtools/issues)
39
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1 #-------------------------------------------------
2 #
3 # Project created by QtCreator 2014-07-20T22:29:15
4 #
5 #-------------------------------------------------
6
7 QT += core
8
9 QT -= gui
10
11 TARGET = basic_VHDL_parser
12 CONFIG += console
13
14 DESTDIR = ../../bin
15
16 TEMPLATE = app
17
18 INCLUDEPATH += \
19 $$DESTDIR/../vhdlparser \
20 ../../vhdlparser
21 # ../../../vhdlparser \
22 # /opt/build-vhdl_tools-Qt_5_2_1_Syst_me-Debug/vhdlparser
23
24 message($$DESTDIR)
25
26
27 LIBS += -lfl -L${DESTDIR} -lvhdlparser
28
29 SOURCES += main.cpp
30
31 OTHER_FILES += \
32 test1.vhd
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1 #include <QCoreApplication>
2 #include <vhdl_file.h>
3
4 int main(int argc, char *argv[])
5 {
6 // extern int yydebug;
7 // yydebug = 1;
8 QCoreApplication a(argc, argv);
9 VHDL_Tools::VHDL_File test;
10 test.parseFile(argv[1]);
11 return 0;
12 }
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the GRLIB VHDL IP LIBRARY
4 -- Copyright (C) 2003 - 2008, Gaisler Research
5 -- Copyright (C) 2008 - 2014, Aeroflex Gaisler
6 --
7 -- This program is free software; you can redistribute it and/or modify
8 -- it under the terms of the GNU General Public License as published by
9 -- the Free Software Foundation; either version 2 of the License, or
10 -- (at your option) any later version.
11 --
12 -- This program is distributed in the hope that it will be useful,
13 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
14 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 -- GNU General Public License for more details.
16 --
17 -- You should have received a copy of the GNU General Public License
18 -- along with this program; if not, write to the Free Software
19 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 -----------------------------------------------------------------------------
21 -- Package: vcomponents
22 -- File: vcomponents.vhd
23 -- Author: Jiri Gaisler, Gaisler Research
24 -- Description: Component declartions of some XILINX primitives
25 -----------------------------------------------------------------------------
26
27 library ieee;
28 use ieee.std_logic_1164.all;
29
30 package vcomponents is
31
32 -- synopsys translate_off
33
34 -----------------------------------------
35 ----------- FPGA Globals --------------
36 -----------------------------------------
37 signal GSR : std_logic := '0';
38 signal GTS : std_logic := '0';
39 signal GWE : std_logic := '0';
40 signal PLL_LOCKG : std_logic := 'H';
41 signal PROGB_GLBL : std_logic := '0';
42 signal CCLKO_GLBL : std_logic := 'H';
43
44 -----------------------------------------
45 ----------- CPLD Globals --------------
46 -----------------------------------------
47 signal PRLD : std_logic := '0';
48
49 -----------------------------------------
50 ----------- JTAG Globals --------------
51 -----------------------------------------
52 signal JTAG_TDO_GLBL : std_logic;
53 signal JTAG_TDI_GLBL : std_logic := '0';
54 signal JTAG_TMS_GLBL : std_logic := '0';
55 signal JTAG_TCK_GLBL : std_logic := '0';
56 signal JTAG_TRST_GLBL : std_logic := '0';
57
58 signal JTAG_CAPTURE_GLBL : std_logic := '0';
59 signal JTAG_RESET_GLBL : std_logic := '1';
60 signal JTAG_SHIFT_GLBL : std_logic := '1';
61 signal JTAG_UPDATE_GLBL : std_logic := '0';
62 signal JTAG_RUNTEST_GLBL : std_logic := '0';
63
64 signal JTAG_SEL1_GLBL : std_logic := '0';
65 signal JTAG_SEL2_GLBL : std_logic := '0';
66 signal JTAG_SEL3_GLBL : std_logic := '0';
67 signal JTAG_SEL4_GLBL : std_logic := '0';
68
69 signal JTAG_USER_TDO1_GLBL : std_logic := 'Z';
70 signal JTAG_USER_TDO2_GLBL : std_logic := 'Z';
71 signal JTAG_USER_TDO3_GLBL : std_logic := 'Z';
72 signal JTAG_USER_TDO4_GLBL : std_logic := 'Z';
73
74 -- synopsys translate_on
75
76 component ramb4_s16 port (
77 do : out std_logic_vector (15 downto 0);
78 addr : in std_logic_vector (7 downto 0);
79 clk : in std_ulogic;
80 di : in std_logic_vector (15 downto 0);
81 en, rst, we : in std_ulogic);
82 end component;
83 component RAMB4_S8
84 port (do : out std_logic_vector (7 downto 0);
85 addr : in std_logic_vector (8 downto 0);
86 clk : in std_ulogic;
87 di : in std_logic_vector (7 downto 0);
88 en, rst, we : in std_ulogic);
89 end component;
90 component RAMB4_S4
91 port (do : out std_logic_vector (3 downto 0);
92 addr : in std_logic_vector (9 downto 0);
93 clk : in std_ulogic;
94 di : in std_logic_vector (3 downto 0);
95 en, rst, we : in std_ulogic);
96 end component;
97 component RAMB4_S2
98 port (do : out std_logic_vector (1 downto 0);
99 addr : in std_logic_vector (10 downto 0);
100 clk : in std_ulogic;
101 di : in std_logic_vector (1 downto 0);
102 en, rst, we : in std_ulogic);
103 end component;
104 component RAMB4_S1
105 port (do : out std_logic_vector (0 downto 0);
106 addr : in std_logic_vector (11 downto 0);
107 clk : in std_ulogic;
108 di : in std_logic_vector (0 downto 0);
109 en, rst, we : in std_ulogic);
110 end component;
111 component RAMB4_S1_S1
112 port (
113 doa : out std_logic_vector (0 downto 0);
114 dob : out std_logic_vector (0 downto 0);
115 addra : in std_logic_vector (11 downto 0);
116 addrb : in std_logic_vector (11 downto 0);
117 clka : in std_ulogic;
118 clkb : in std_ulogic;
119 dia : in std_logic_vector (0 downto 0);
120 dib : in std_logic_vector (0 downto 0);
121 ena : in std_ulogic;
122 enb : in std_ulogic;
123 rsta : in std_ulogic;
124 rstb : in std_ulogic;
125 wea : in std_ulogic;
126 web : in std_ulogic
127 );
128 end component;
129 component RAMB4_S2_S2
130 port (
131 doa : out std_logic_vector (1 downto 0);
132 dob : out std_logic_vector (1 downto 0);
133 addra : in std_logic_vector (10 downto 0);
134 addrb : in std_logic_vector (10 downto 0);
135 clka : in std_ulogic;
136 clkb : in std_ulogic;
137 dia : in std_logic_vector (1 downto 0);
138 dib : in std_logic_vector (1 downto 0);
139 ena : in std_ulogic;
140 enb : in std_ulogic;
141 rsta : in std_ulogic;
142 rstb : in std_ulogic;
143 wea : in std_ulogic;
144 web : in std_ulogic
145 );
146 end component;
147 component RAMB4_S4_S4
148 port (
149 doa : out std_logic_vector (3 downto 0);
150 dob : out std_logic_vector (3 downto 0);
151 addra : in std_logic_vector (9 downto 0);
152 addrb : in std_logic_vector (9 downto 0);
153 clka : in std_ulogic;
154 clkb : in std_ulogic;
155 dia : in std_logic_vector (3 downto 0);
156 dib : in std_logic_vector (3 downto 0);
157 ena : in std_ulogic;
158 enb : in std_ulogic;
159 rsta : in std_ulogic;
160 rstb : in std_ulogic;
161 wea : in std_ulogic;
162 web : in std_ulogic
163 );
164 end component;
165 component RAMB4_S8_S8
166 port (
167 doa : out std_logic_vector (7 downto 0);
168 dob : out std_logic_vector (7 downto 0);
169 addra : in std_logic_vector (8 downto 0);
170 addrb : in std_logic_vector (8 downto 0);
171 clka : in std_ulogic;
172 clkb : in std_ulogic;
173 dia : in std_logic_vector (7 downto 0);
174 dib : in std_logic_vector (7 downto 0);
175 ena : in std_ulogic;
176 enb : in std_ulogic;
177 rsta : in std_ulogic;
178 rstb : in std_ulogic;
179 wea : in std_ulogic;
180 web : in std_ulogic
181 );
182 end component;
183 component RAMB4_S16_S16
184 port (
185 doa : out std_logic_vector (15 downto 0);
186 dob : out std_logic_vector (15 downto 0);
187 addra : in std_logic_vector (7 downto 0);
188 addrb : in std_logic_vector (7 downto 0);
189 clka : in std_ulogic;
190 clkb : in std_ulogic;
191 dia : in std_logic_vector (15 downto 0);
192 dib : in std_logic_vector (15 downto 0);
193 ena : in std_ulogic;
194 enb : in std_ulogic;
195 rsta : in std_ulogic;
196 rstb : in std_ulogic;
197 wea : in std_ulogic;
198 web : in std_ulogic
199 );
200 end component;
201
202 component RAMB16_S1
203 -- pragma translate_off
204 generic
205 (
206 INIT : bit_vector := X"0";
207 SRVAL : bit_vector := X"0";
208 WRITE_MODE : string := "WRITE_FIRST";
209 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
210 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
211 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
212 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
213 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
214 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
215 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
216 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
217 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
218 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
219 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
220 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
221 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
222 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
223 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
224 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
225 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
226 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
227 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
228 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
229 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
230 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
231 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
232 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
233 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
234 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
235 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
236 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
237 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
238 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
239 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
240 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
241 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
242 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
243 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
244 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
245 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
246 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
247 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
248 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
249 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
250 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
251 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
252 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
253 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
254 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
255 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
256 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
257 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
258 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
259 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
260 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
261 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
262 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
263 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
264 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
265 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
266 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
267 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
268 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
269 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
270 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
271 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
272 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
273 );
274 -- pragma translate_on
275 port (
276 DO : out std_logic_vector (0 downto 0);
277 ADDR : in std_logic_vector (13 downto 0);
278 CLK : in std_ulogic;
279 DI : in std_logic_vector (0 downto 0);
280 EN : in std_ulogic;
281 SSR : in std_ulogic;
282 WE : in std_ulogic
283 );
284 end component;
285
286 component RAMB16_S2
287 -- pragma translate_off
288 generic
289 (
290 INIT : bit_vector := X"0";
291 SRVAL : bit_vector := X"0";
292 WRITE_MODE : string := "WRITE_FIRST";
293 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
294 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
295 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
296 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
297 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
298 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
299 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
300 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
301 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
302 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
303 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
304 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
305 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
306 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
307 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
308 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
309 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
310 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
311 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
312 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
313 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
314 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
315 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
316 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
317 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
318 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
319 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
320 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
321 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
322 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
323 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
324 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
325 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
326 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
327 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
328 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
329 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
330 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
331 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
332 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
333 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
334 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
335 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
336 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
337 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
338 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
339 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
340 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
341 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
342 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
343 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
344 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
345 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
346 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
347 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
348 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
349 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
350 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
351 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
352 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
353 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
354 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
355 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
356 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
357 );
358 -- pragma translate_on
359 port (
360 DO : out std_logic_vector (1 downto 0);
361 ADDR : in std_logic_vector (12 downto 0);
362 CLK : in std_ulogic;
363 DI : in std_logic_vector (1 downto 0);
364 EN : in std_ulogic;
365 SSR : in std_ulogic;
366 WE : in std_ulogic
367 );
368 end component;
369
370 component RAMB16_S4
371 -- pragma translate_off
372 generic
373 (
374 INIT : bit_vector := X"0";
375 SRVAL : bit_vector := X"0";
376 WRITE_MODE : string := "WRITE_FIRST";
377 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
378 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
379 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
380 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
381 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
382 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
383 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
384 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
385 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
386 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
387 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
388 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
389 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
390 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
391 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
392 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
393 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
394 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
395 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
396 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
397 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
398 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
399 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
400 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
401 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
402 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
403 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
404 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
405 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
406 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
407 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
408 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
409 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
410 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
411 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
412 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
413 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
414 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
415 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
416 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
417 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
418 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
419 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
420 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
421 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
422 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
423 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
424 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
425 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
426 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
427 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
428 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
429 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
430 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
431 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
432 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
433 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
434 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
435 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
436 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
437 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
438 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
439 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
440 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
441 );
442 -- pragma translate_on
443 port (
444 DO : out std_logic_vector (3 downto 0);
445 ADDR : in std_logic_vector (11 downto 0);
446 CLK : in std_ulogic;
447 DI : in std_logic_vector (3 downto 0);
448 EN : in std_ulogic;
449 SSR : in std_ulogic;
450 WE : in std_ulogic
451 );
452 end component;
453
454 component RAMB16_S9
455 -- pragma translate_off
456 generic
457 (
458 INIT : bit_vector := X"000";
459 SRVAL : bit_vector := X"000";
460 WRITE_MODE : string := "WRITE_FIRST";
461 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
462 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
463 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
464 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
465 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
466 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
467 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
468 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
469 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
470 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
471 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
472 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
473 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
474 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
475 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
476 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
477 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
478 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
479 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
480 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
481 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
482 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
483 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
484 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
485 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
486 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
487 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
488 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
489 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
490 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
491 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
492 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
493 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
494 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
495 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
496 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
497 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
498 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
499 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
500 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
501 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
502 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
503 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
504 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
505 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
506 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
507 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
508 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
509 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
510 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
511 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
512 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
513 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
514 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
515 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
516 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
517 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
518 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
519 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
520 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
521 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
522 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
523 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
524 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
525 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
526 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
527 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
528 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
529 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
530 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
531 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
532 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
533 );
534 -- pragma translate_on
535 port (
536 DO : out std_logic_vector (7 downto 0);
537 DOP : out std_logic_vector (0 downto 0);
538 ADDR : in std_logic_vector (10 downto 0);
539 CLK : in std_ulogic;
540 DI : in std_logic_vector (7 downto 0);
541 DIP : in std_logic_vector (0 downto 0);
542 EN : in std_ulogic;
543 SSR : in std_ulogic;
544 WE : in std_ulogic
545 );
546 end component;
547
548 component RAMB16_S18
549 -- pragma translate_off
550 generic
551 (
552 INIT : bit_vector := X"00000";
553 SRVAL : bit_vector := X"00000";
554 write_mode : string := "WRITE_FIRST";
555 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
556 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
557 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
558 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
559 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
560 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
561 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
562 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
563 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
564 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
565 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
566 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
567 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
568 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
569 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
570 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
571 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
572 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
573 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
574 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
575 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
576 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
577 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
578 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
579 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
580 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
581 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
582 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
583 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
584 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
585 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
586 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
587 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
588 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
589 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
590 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
591 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
592 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
593 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
594 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
595 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
596 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
597 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
598 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
599 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
600 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
601 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
602 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
603 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
604 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
605 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
606 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
607 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
608 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
609 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
610 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
611 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
612 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
613 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
614 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
615 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
616 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
617 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
618 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
619 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
620 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
621 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
622 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
623 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
624 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
625 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
626 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
627 );
628 -- pragma translate_on
629 port (
630 DO : out std_logic_vector (15 downto 0);
631 DOP : out std_logic_vector (1 downto 0);
632 ADDR : in std_logic_vector (9 downto 0);
633 CLK : in std_ulogic;
634 DI : in std_logic_vector (15 downto 0);
635 DIP : in std_logic_vector (1 downto 0);
636 EN : in std_ulogic;
637 SSR : in std_ulogic;
638 WE : in std_ulogic
639 );
640 end component;
641
642 component RAMB16_S36
643 -- pragma translate_off
644 generic
645 (
646 INIT : bit_vector := X"000000000";
647 SRVAL : bit_vector := X"000000000";
648 WRITE_MODE : string := "WRITE_FIRST";
649 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
650 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
651 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
652 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
653 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
654 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
655 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
656 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
657 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
658 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
659 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
660 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
661 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
662 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
663 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
664 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
665 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
666 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
667 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
668 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
669 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
670 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
671 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
672 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
673 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
674 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
675 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
676 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
677 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
678 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
679 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
680 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
681 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
682 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
683 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
684 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
685 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
686 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
687 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
688 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
689 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
690 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
691 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
692 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
693 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
694 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
695 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
696 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
697 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
698 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
699 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
700 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
701 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
702 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
703 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
704 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
705 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
706 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
707 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
708 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
709 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
710 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
711 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
712 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
713 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
714 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
715 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
716 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
717 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
718 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
719 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
720 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
721 );
722 -- pragma translate_on
723 port (
724 DO : out std_logic_vector (31 downto 0);
725 DOP : out std_logic_vector (3 downto 0);
726 ADDR : in std_logic_vector (8 downto 0);
727 CLK : in std_ulogic;
728 DI : in std_logic_vector (31 downto 0);
729 DIP : in std_logic_vector (3 downto 0);
730 EN : in std_ulogic;
731 SSR : in std_ulogic;
732 WE : in std_ulogic
733 );
734 end component;
735
736 component RAMB16_S4_S4
737 -- pragma translate_off
738 generic
739 (
740 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
741 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
742 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
743 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
744 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
745 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
746 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
747 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
748 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
749 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
750 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
751 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
752 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
753 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
754 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
755 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
756 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
757 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
758 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
759 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
760 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
761 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
762 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
763 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
764 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
765 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
766 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
767 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
768 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
769 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
770 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
771 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
772 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
773 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
774 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
775 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
776 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
777 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
778 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
779 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
780 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
781 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
782 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
783 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
784 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
785 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
786 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
787 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
788 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
789 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
790 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
791 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
792 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
793 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
794 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
795 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
796 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
797 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
798 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
799 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
800 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
801 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
802 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
803 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
804 INIT_A : bit_vector := X"0";
805 INIT_B : bit_vector := X"0";
806 SIM_COLLISION_CHECK : string := "ALL";
807 SRVAL_A : bit_vector := X"0";
808 SRVAL_B : bit_vector := X"0";
809 WRITE_MODE_A : string := "WRITE_FIRST";
810 WRITE_MODE_B : string := "WRITE_FIRST"
811 );
812 -- pragma translate_on
813 port (
814 DOA : out std_logic_vector (3 downto 0);
815 DOB : out std_logic_vector (3 downto 0);
816 ADDRA : in std_logic_vector (11 downto 0);
817 ADDRB : in std_logic_vector (11 downto 0);
818 CLKA : in std_ulogic;
819 CLKB : in std_ulogic;
820 DIA : in std_logic_vector (3 downto 0);
821 DIB : in std_logic_vector (3 downto 0);
822 ENA : in std_ulogic;
823 ENB : in std_ulogic;
824 SSRA : in std_ulogic;
825 SSRB : in std_ulogic;
826 WEA : in std_ulogic;
827 WEB : in std_ulogic
828 );
829 end component;
830
831 component RAMB16_S1_S1
832 -- pragma translate_off
833 generic
834 (
835 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
836 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
837 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
838 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
839 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
840 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
841 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
842 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
843 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
844 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
845 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
846 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
847 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
848 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
849 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
850 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
851 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
852 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
853 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
854 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
855 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
856 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
857 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
858 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
859 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
860 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
861 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
862 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
863 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
864 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
865 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
866 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
867 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
868 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
869 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
870 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
871 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
872 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
873 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
874 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
875 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
876 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
877 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
878 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
879 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
880 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
881 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
882 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
883 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
884 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
885 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
886 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
887 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
888 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
889 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
890 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
891 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
892 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
893 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
894 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
895 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
896 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
897 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
898 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
899 INIT_A : bit_vector := X"0";
900 INIT_B : bit_vector := X"0";
901 SIM_COLLISION_CHECK : string := "ALL";
902 SRVAL_A : bit_vector := X"0";
903 SRVAL_B : bit_vector := X"0";
904 WRITE_MODE_A : string := "WRITE_FIRST";
905 WRITE_MODE_B : string := "WRITE_FIRST"
906 );
907 -- pragma translate_on
908 port (
909 DOA : out std_logic_vector (0 downto 0);
910 DOB : out std_logic_vector (0 downto 0);
911 ADDRA : in std_logic_vector (13 downto 0);
912 ADDRB : in std_logic_vector (13 downto 0);
913 CLKA : in std_ulogic;
914 CLKB : in std_ulogic;
915 DIA : in std_logic_vector (0 downto 0);
916 DIB : in std_logic_vector (0 downto 0);
917 ENA : in std_ulogic;
918 ENB : in std_ulogic;
919 SSRA : in std_ulogic;
920 SSRB : in std_ulogic;
921 WEA : in std_ulogic;
922 WEB : in std_ulogic
923 );
924 end component;
925
926 component RAMB16_S2_S2
927 -- pragma translate_off
928 generic
929 (
930 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
931 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
932 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
933 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
934 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
935 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
936 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
937 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
938 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
939 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
940 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
941 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
942 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
943 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
944 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
945 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
946 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
947 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
948 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
949 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
950 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
951 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
952 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
953 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
954 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
955 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
956 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
957 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
958 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
959 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
960 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
961 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
962 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
963 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
964 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
965 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
966 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
967 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
968 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
969 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
970 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
971 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
972 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
973 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
974 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
975 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
976 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
977 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
978 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
979 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
980 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
981 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
982 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
983 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
984 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
985 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
986 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
987 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
988 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
989 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
990 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
991 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
992 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
993 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
994 INIT_A : bit_vector := X"0";
995 INIT_B : bit_vector := X"0";
996 SIM_COLLISION_CHECK : string := "ALL";
997 SRVAL_A : bit_vector := X"0";
998 SRVAL_B : bit_vector := X"0";
999 WRITE_MODE_A : string := "WRITE_FIRST";
1000 WRITE_MODE_B : string := "WRITE_FIRST"
1001 );
1002 -- pragma translate_on
1003 port (
1004 DOA : out std_logic_vector (1 downto 0);
1005 DOB : out std_logic_vector (1 downto 0);
1006 ADDRA : in std_logic_vector (12 downto 0);
1007 ADDRB : in std_logic_vector (12 downto 0);
1008 CLKA : in std_ulogic;
1009 CLKB : in std_ulogic;
1010 DIA : in std_logic_vector (1 downto 0);
1011 DIB : in std_logic_vector (1 downto 0);
1012 ENA : in std_ulogic;
1013 ENB : in std_ulogic;
1014 SSRA : in std_ulogic;
1015 SSRB : in std_ulogic;
1016 WEA : in std_ulogic;
1017 WEB : in std_ulogic
1018 );
1019 end component;
1020
1021 component RAMB16_S9_S9
1022 -- pragma translate_off
1023 generic
1024 (
1025 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1026 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1027 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1028 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1029 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1030 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1031 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1032 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1033 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1034 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1035 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1036 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1037 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1038 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1039 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1040 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1041 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1042 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1043 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1044 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1045 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1046 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1047 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1048 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1049 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1050 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1051 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1052 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1053 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1054 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1055 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1056 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1057 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1058 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1059 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1060 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1061 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1062 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1063 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1064 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1065 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1066 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1067 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1068 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1069 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1070 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1071 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1072 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1073 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1074 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1075 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1076 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1077 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1078 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1079 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1080 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1081 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1082 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1083 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1084 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1085 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1086 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1087 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1088 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1089 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1090 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1091 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1092 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1093 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1094 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1095 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1096 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1097 INIT_A : bit_vector := X"000";
1098 INIT_B : bit_vector := X"000";
1099 SIM_COLLISION_CHECK : string := "ALL";
1100 SRVAL_A : bit_vector := X"000";
1101 SRVAL_B : bit_vector := X"000";
1102 WRITE_MODE_A : string := "WRITE_FIRST";
1103 WRITE_MODE_B : string := "WRITE_FIRST"
1104 );
1105 -- pragma translate_on
1106 port (
1107 DOA : out std_logic_vector (7 downto 0);
1108 DOB : out std_logic_vector (7 downto 0);
1109 DOPA : out std_logic_vector (0 downto 0);
1110 DOPB : out std_logic_vector (0 downto 0);
1111 ADDRA : in std_logic_vector (10 downto 0);
1112 ADDRB : in std_logic_vector (10 downto 0);
1113 CLKA : in std_ulogic;
1114 CLKB : in std_ulogic;
1115 DIA : in std_logic_vector (7 downto 0);
1116 DIB : in std_logic_vector (7 downto 0);
1117 DIPA : in std_logic_vector (0 downto 0);
1118 DIPB : in std_logic_vector (0 downto 0);
1119 ENA : in std_ulogic;
1120 ENB : in std_ulogic;
1121 SSRA : in std_ulogic;
1122 SSRB : in std_ulogic;
1123 WEA : in std_ulogic;
1124 WEB : in std_ulogic
1125 );
1126 end component;
1127
1128 component RAMB16_S18_S18
1129 -- pragma translate_off
1130 generic
1131 (
1132 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1133 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1134 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1135 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1136 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1137 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1138 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1139 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1140 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1141 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1142 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1143 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1144 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1145 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1146 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1147 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1148 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1149 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1150 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1151 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1152 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1153 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1154 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1155 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1156 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1157 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1158 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1159 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1160 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1161 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1162 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1163 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1164 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1165 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1166 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1167 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1168 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1169 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1170 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1171 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1172 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1173 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1174 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1175 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1176 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1177 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1178 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1179 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1180 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1181 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1182 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1183 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1184 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1185 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1186 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1187 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1188 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1189 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1190 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1191 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1192 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1193 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1194 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1195 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1196 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1197 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1198 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1199 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1200 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1201 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1202 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1203 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1204 INIT_A : bit_vector := X"00000";
1205 INIT_B : bit_vector := X"00000";
1206 SIM_COLLISION_CHECK : string := "ALL";
1207 SRVAL_A : bit_vector := X"00000";
1208 SRVAL_B : bit_vector := X"00000";
1209 WRITE_MODE_A : string := "WRITE_FIRST";
1210 WRITE_MODE_B : string := "WRITE_FIRST"
1211 );
1212 -- pragma translate_on
1213 port (
1214 DOA : out std_logic_vector (15 downto 0);
1215 DOB : out std_logic_vector (15 downto 0);
1216 DOPA : out std_logic_vector (1 downto 0);
1217 DOPB : out std_logic_vector (1 downto 0);
1218 ADDRA : in std_logic_vector (9 downto 0);
1219 ADDRB : in std_logic_vector (9 downto 0);
1220 CLKA : in std_ulogic;
1221 CLKB : in std_ulogic;
1222 DIA : in std_logic_vector (15 downto 0);
1223 DIB : in std_logic_vector (15 downto 0);
1224 DIPA : in std_logic_vector (1 downto 0);
1225 DIPB : in std_logic_vector (1 downto 0);
1226 ENA : in std_ulogic;
1227 ENB : in std_ulogic;
1228 SSRA : in std_ulogic;
1229 SSRB : in std_ulogic;
1230 WEA : in std_ulogic;
1231 WEB : in std_ulogic);
1232 end component;
1233
1234 component RAMB16_S36_S36
1235 -- pragma translate_off
1236 generic
1237 (
1238 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1239 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1240 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1241 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1242 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1243 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1244 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1245 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1246 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1247 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1248 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1249 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1250 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1251 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1252 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1253 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1254 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1255 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1256 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1257 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1258 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1259 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1260 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1261 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1262 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1263 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1264 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1265 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1266 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1267 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1268 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1269 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1270 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1271 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1272 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1273 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1274 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1275 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1276 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1277 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1278 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1279 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1280 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1281 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1282 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1283 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1284 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1285 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1286 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1287 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1288 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1289 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1290 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1291 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1292 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1293 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1294 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1295 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1296 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1297 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1298 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1299 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1300 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1301 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1302 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1303 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1304 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1305 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1306 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1307 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1308 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1309 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
1310 INIT_A : bit_vector := X"000000000";
1311 INIT_B : bit_vector := X"000000000";
1312 SIM_COLLISION_CHECK : string := "ALL";
1313 SRVAL_A : bit_vector := X"000000000";
1314 SRVAL_B : bit_vector := X"000000000";
1315 WRITE_MODE_A : string := "WRITE_FIRST";
1316 WRITE_MODE_B : string := "WRITE_FIRST"
1317 );
1318 -- pragma translate_on
1319 port (
1320 DOA : out std_logic_vector (31 downto 0);
1321 DOB : out std_logic_vector (31 downto 0);
1322 DOPA : out std_logic_vector (3 downto 0);
1323 DOPB : out std_logic_vector (3 downto 0);
1324 ADDRA : in std_logic_vector (8 downto 0);
1325 ADDRB : in std_logic_vector (8 downto 0);
1326 CLKA : in std_ulogic;
1327 CLKB : in std_ulogic;
1328 DIA : in std_logic_vector (31 downto 0);
1329 DIB : in std_logic_vector (31 downto 0);
1330 DIPA : in std_logic_vector (3 downto 0);
1331 DIPB : in std_logic_vector (3 downto 0);
1332 ENA : in std_ulogic;
1333 ENB : in std_ulogic;
1334 SSRA : in std_ulogic;
1335 SSRB : in std_ulogic;
1336 WEA : in std_ulogic;
1337 WEB : in std_ulogic);
1338 end component;
1339
1340 component DCM
1341 generic (
1342 CLKDV_DIVIDE : real := 2.0;
1343 CLKFX_DIVIDE : integer := 1;
1344 CLKFX_MULTIPLY : integer := 4;
1345 CLKIN_DIVIDE_BY_2 : boolean := false;
1346 CLKIN_PERIOD : real := 10.0;
1347 CLKOUT_PHASE_SHIFT : string := "NONE";
1348 CLK_FEEDBACK : string := "1X";
1349 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
1350 DFS_FREQUENCY_MODE : string := "LOW";
1351 DLL_FREQUENCY_MODE : string := "LOW";
1352 DSS_MODE : string := "NONE";
1353 DUTY_CYCLE_CORRECTION : boolean := true;
1354 FACTORY_JF : bit_vector := X"C080";
1355 PHASE_SHIFT : integer := 0;
1356 STARTUP_WAIT : boolean := false
1357 );
1358 port (
1359 CLKFB : in std_logic;
1360 CLKIN : in std_logic;
1361 DSSEN : in std_logic;
1362 PSCLK : in std_logic;
1363 PSEN : in std_logic;
1364 PSINCDEC : in std_logic;
1365 RST : in std_logic;
1366 CLK0 : out std_logic;
1367 CLK90 : out std_logic;
1368 CLK180 : out std_logic;
1369 CLK270 : out std_logic;
1370 CLK2X : out std_logic;
1371 CLK2X180 : out std_logic;
1372 CLKDV : out std_logic;
1373 CLKFX : out std_logic;
1374 CLKFX180 : out std_logic;
1375 LOCKED : out std_logic;
1376 PSDONE : out std_logic;
1377 STATUS : out std_logic_vector (7 downto 0));
1378 end component;
1379
1380 component DCM_SP
1381 generic (
1382 TimingChecksOn : boolean := true;
1383 InstancePath : string := "*";
1384 Xon : boolean := true;
1385 MsgOn : boolean := false;
1386 CLKDV_DIVIDE : real := 2.0;
1387 CLKFX_DIVIDE : integer := 1;
1388 CLKFX_MULTIPLY : integer := 4;
1389 CLKIN_DIVIDE_BY_2 : boolean := false;
1390 CLKIN_PERIOD : real := 10.0; --non-simulatable
1391 CLKOUT_PHASE_SHIFT : string := "NONE";
1392 CLK_FEEDBACK : string := "1X";
1393 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
1394 DFS_FREQUENCY_MODE : string := "LOW";
1395 DLL_FREQUENCY_MODE : string := "LOW";
1396 DSS_MODE : string := "NONE"; --non-simulatable
1397 DUTY_CYCLE_CORRECTION : boolean := true;
1398 FACTORY_JF : bit_vector := X"C080"; --non-simulatable
1399 PHASE_SHIFT : integer := 0;
1400 STARTUP_WAIT : boolean := false --non-simulatable
1401 );
1402
1403 port (
1404 CLK0 : out std_ulogic := '0';
1405 CLK180 : out std_ulogic := '0';
1406 CLK270 : out std_ulogic := '0';
1407 CLK2X : out std_ulogic := '0';
1408 CLK2X180 : out std_ulogic := '0';
1409 CLK90 : out std_ulogic := '0';
1410 CLKDV : out std_ulogic := '0';
1411 CLKFX : out std_ulogic := '0';
1412 CLKFX180 : out std_ulogic := '0';
1413 LOCKED : out std_ulogic := '0';
1414 PSDONE : out std_ulogic := '0';
1415 STATUS : out std_logic_vector(7 downto 0) := "00000000";
1416
1417 CLKFB : in std_ulogic := '0';
1418 CLKIN : in std_ulogic := '0';
1419 DSSEN : in std_ulogic := '0';
1420 PSCLK : in std_ulogic := '0';
1421 PSEN : in std_ulogic := '0';
1422 PSINCDEC : in std_ulogic := '0';
1423 RST : in std_ulogic := '0'
1424 );
1425 end component;
1426
1427 ----- component PLLE2_ADV -----
1428 component PLLE2_ADV
1429 generic (
1430 BANDWIDTH : string := "OPTIMIZED";
1431 CLKFBOUT_MULT : integer := 5;
1432 CLKFBOUT_PHASE : real := 0.0;
1433 CLKIN1_PERIOD : real := 0.0;
1434 CLKIN2_PERIOD : real := 0.0;
1435 CLKOUT0_DIVIDE : integer := 1;
1436 CLKOUT0_DUTY_CYCLE : real := 0.5;
1437 CLKOUT0_PHASE : real := 0.0;
1438 CLKOUT1_DIVIDE : integer := 1;
1439 CLKOUT1_DUTY_CYCLE : real := 0.5;
1440 CLKOUT1_PHASE : real := 0.0;
1441 CLKOUT2_DIVIDE : integer := 1;
1442 CLKOUT2_DUTY_CYCLE : real := 0.5;
1443 CLKOUT2_PHASE : real := 0.0;
1444 CLKOUT3_DIVIDE : integer := 1;
1445 CLKOUT3_DUTY_CYCLE : real := 0.5;
1446 CLKOUT3_PHASE : real := 0.0;
1447 CLKOUT4_DIVIDE : integer := 1;
1448 CLKOUT4_DUTY_CYCLE : real := 0.5;
1449 CLKOUT4_PHASE : real := 0.0;
1450 CLKOUT5_DIVIDE : integer := 1;
1451 CLKOUT5_DUTY_CYCLE : real := 0.5;
1452 CLKOUT5_PHASE : real := 0.0;
1453 COMPENSATION : string := "ZHOLD";
1454 DIVCLK_DIVIDE : integer := 1;
1455 REF_JITTER1 : real := 0.0;
1456 REF_JITTER2 : real := 0.0;
1457 STARTUP_WAIT : string := "FALSE"
1458 );
1459 port (
1460 CLKFBOUT : out std_ulogic := '0';
1461 CLKOUT0 : out std_ulogic := '0';
1462 CLKOUT1 : out std_ulogic := '0';
1463 CLKOUT2 : out std_ulogic := '0';
1464 CLKOUT3 : out std_ulogic := '0';
1465 CLKOUT4 : out std_ulogic := '0';
1466 CLKOUT5 : out std_ulogic := '0';
1467 DO : out std_logic_vector (15 downto 0);
1468 DRDY : out std_ulogic := '0';
1469 LOCKED : out std_ulogic := '0';
1470 CLKFBIN : in std_ulogic;
1471 CLKIN1 : in std_ulogic;
1472 CLKIN2 : in std_ulogic;
1473 CLKINSEL : in std_ulogic;
1474 DADDR : in std_logic_vector(6 downto 0);
1475 DCLK : in std_ulogic;
1476 DEN : in std_ulogic;
1477 DI : in std_logic_vector(15 downto 0);
1478 DWE : in std_ulogic;
1479 PWRDWN : in std_ulogic;
1480 RST : in std_ulogic
1481 );
1482 end component;
1483
1484 component PLL_ADV
1485 generic (
1486 BANDWIDTH : string := "OPTIMIZED";
1487 CLKFBOUT_DESKEW_ADJUST : string := "NONE";
1488 CLKFBOUT_MULT : integer := 1;
1489 CLKFBOUT_PHASE : real := 0.0;
1490 CLKIN1_PERIOD : real := 0.000;
1491 CLKIN2_PERIOD : real := 0.000;
1492 CLKOUT0_DESKEW_ADJUST : string := "NONE";
1493 CLKOUT0_DIVIDE : integer := 1;
1494 CLKOUT0_DUTY_CYCLE : real := 0.5;
1495 CLKOUT0_PHASE : real := 0.0;
1496 CLKOUT1_DESKEW_ADJUST : string := "NONE";
1497 CLKOUT1_DIVIDE : integer := 1;
1498 CLKOUT1_DUTY_CYCLE : real := 0.5;
1499 CLKOUT1_PHASE : real := 0.0;
1500 CLKOUT2_DESKEW_ADJUST : string := "NONE";
1501 CLKOUT2_DIVIDE : integer := 1;
1502 CLKOUT2_DUTY_CYCLE : real := 0.5;
1503 CLKOUT2_PHASE : real := 0.0;
1504 CLKOUT3_DESKEW_ADJUST : string := "NONE";
1505 CLKOUT3_DIVIDE : integer := 1;
1506 CLKOUT3_DUTY_CYCLE : real := 0.5;
1507 CLKOUT3_PHASE : real := 0.0;
1508 CLKOUT4_DESKEW_ADJUST : string := "NONE";
1509 CLKOUT4_DIVIDE : integer := 1;
1510 CLKOUT4_DUTY_CYCLE : real := 0.5;
1511 CLKOUT4_PHASE : real := 0.0;
1512 CLKOUT5_DESKEW_ADJUST : string := "NONE";
1513 CLKOUT5_DIVIDE : integer := 1;
1514 CLKOUT5_DUTY_CYCLE : real := 0.5;
1515 CLKOUT5_PHASE : real := 0.0;
1516 CLK_FEEDBACK : string := "CLKFBOUT";
1517 COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
1518 DIVCLK_DIVIDE : integer := 1;
1519 EN_REL : boolean := FALSE;
1520 PLL_PMCD_MODE : boolean := FALSE;
1521 REF_JITTER : real := 0.100;
1522 RESET_ON_LOSS_OF_LOCK : boolean := FALSE;
1523 RST_DEASSERT_CLK : string := "CLKIN1";
1524 SIM_DEVICE : string := "VIRTEX5"
1525 );
1526 port (
1527 CLKFBDCM : out std_ulogic := '0';
1528 CLKFBOUT : out std_ulogic := '0';
1529 CLKOUT0 : out std_ulogic := '0';
1530 CLKOUT1 : out std_ulogic := '0';
1531 CLKOUT2 : out std_ulogic := '0';
1532 CLKOUT3 : out std_ulogic := '0';
1533 CLKOUT4 : out std_ulogic := '0';
1534 CLKOUT5 : out std_ulogic := '0';
1535 CLKOUTDCM0 : out std_ulogic := '0';
1536 CLKOUTDCM1 : out std_ulogic := '0';
1537 CLKOUTDCM2 : out std_ulogic := '0';
1538 CLKOUTDCM3 : out std_ulogic := '0';
1539 CLKOUTDCM4 : out std_ulogic := '0';
1540 CLKOUTDCM5 : out std_ulogic := '0';
1541 DO : out std_logic_vector(15 downto 0);
1542 DRDY : out std_ulogic := '0';
1543 LOCKED : out std_ulogic := '0';
1544 CLKFBIN : in std_ulogic;
1545 CLKIN1 : in std_ulogic;
1546 CLKIN2 : in std_ulogic;
1547 CLKINSEL : in std_ulogic;
1548 DADDR : in std_logic_vector(4 downto 0);
1549 DCLK : in std_ulogic;
1550 DEN : in std_ulogic;
1551 DI : in std_logic_vector(15 downto 0);
1552 DWE : in std_ulogic;
1553 REL : in std_ulogic;
1554 RST : in std_ulogic
1555 );
1556 end component;
1557
1558 component PLL_BASE
1559 generic (
1560 BANDWIDTH : string := "OPTIMIZED";
1561 CLKFBOUT_MULT : integer := 1;
1562 CLKFBOUT_PHASE : real := 0.0;
1563 CLKIN_PERIOD : real := 0.000;
1564 CLKOUT0_DIVIDE : integer := 1;
1565 CLKOUT0_DUTY_CYCLE : real := 0.5;
1566 CLKOUT0_PHASE : real := 0.0;
1567 CLKOUT1_DIVIDE : integer := 1;
1568 CLKOUT1_DUTY_CYCLE : real := 0.5;
1569 CLKOUT1_PHASE : real := 0.0;
1570 CLKOUT2_DIVIDE : integer := 1;
1571 CLKOUT2_DUTY_CYCLE : real := 0.5;
1572 CLKOUT2_PHASE : real := 0.0;
1573 CLKOUT3_DIVIDE : integer := 1;
1574 CLKOUT3_DUTY_CYCLE : real := 0.5;
1575 CLKOUT3_PHASE : real := 0.0;
1576 CLKOUT4_DIVIDE : integer := 1;
1577 CLKOUT4_DUTY_CYCLE : real := 0.5;
1578 CLKOUT4_PHASE : real := 0.0;
1579 CLKOUT5_DIVIDE : integer := 1;
1580 CLKOUT5_DUTY_CYCLE : real := 0.5;
1581 CLKOUT5_PHASE : real := 0.0;
1582 CLK_FEEDBACK : string := "CLKFBOUT";
1583 COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
1584 DIVCLK_DIVIDE : integer := 1;
1585 REF_JITTER : real := 0.100;
1586 RESET_ON_LOSS_OF_LOCK : boolean := FALSE
1587 );
1588 port (
1589 CLKFBOUT : out std_ulogic;
1590 CLKOUT0 : out std_ulogic;
1591 CLKOUT1 : out std_ulogic;
1592 CLKOUT2 : out std_ulogic;
1593 CLKOUT3 : out std_ulogic;
1594 CLKOUT4 : out std_ulogic;
1595 CLKOUT5 : out std_ulogic;
1596 LOCKED : out std_ulogic;
1597 CLKFBIN : in std_ulogic;
1598 CLKIN : in std_ulogic;
1599 RST : in std_ulogic
1600 );
1601 end component;
1602
1603 component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
1604 component BUFG port (O : out std_logic; I : in std_logic); end component;
1605 component BUFGP port (O : out std_logic; I : in std_logic); end component;
1606 component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
1607
1608 component IBUFG generic(
1609 CAPACITANCE : string := "DONT_CARE";
1610 IBUF_LOW_PWR : boolean := TRUE;
1611 IOSTANDARD : string := "LVCMOS25");
1612 port (O : out std_logic; I : in std_logic); end component;
1613 component IBUF generic(
1614 CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
1615 port (O : out std_ulogic; I : in std_ulogic); end component;
1616 component IOBUF generic (
1617 CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
1618 IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE;
1619 IFD_DELAY_VALUE : string := "AUTO";
1620 IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
1621 port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
1622 component OBUF generic (
1623 CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
1624 IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
1625 port (O : out std_ulogic; I : in std_ulogic); end component;
1626 component OBUFT generic (
1627 CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
1628 IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
1629 port (O : out std_ulogic; I, T : in std_ulogic); end component;
1630
1631 component CLKDLL
1632 port (
1633 CLK0 : out std_ulogic;
1634 CLK180 : out std_ulogic;
1635 CLK270 : out std_ulogic;
1636 CLK2X : out std_ulogic;
1637 CLK90 : out std_ulogic;
1638 CLKDV : out std_ulogic;
1639 LOCKED : out std_ulogic;
1640 CLKFB : in std_ulogic;
1641 CLKIN : in std_ulogic;
1642 RST : in std_ulogic);
1643 end component;
1644
1645 component CLKDLLHF
1646 port (
1647 CLK0 : out std_ulogic := '0';
1648 CLK180 : out std_ulogic := '0';
1649 CLKDV : out std_ulogic := '0';
1650 LOCKED : out std_ulogic := '0';
1651 CLKFB : in std_ulogic := '0';
1652 CLKIN : in std_ulogic := '0';
1653 RST : in std_ulogic := '0');
1654 end component;
1655
1656 component BSCAN_VIRTEX
1657 port (CAPTURE : out STD_ULOGIC;
1658 DRCK1 : out STD_ULOGIC;
1659 DRCK2 : out STD_ULOGIC;
1660 RESET : out STD_ULOGIC;
1661 SEL1 : out STD_ULOGIC;
1662 SEL2 : out STD_ULOGIC;
1663 SHIFT : out STD_ULOGIC;
1664 TDI : out STD_ULOGIC;
1665 UPDATE : out STD_ULOGIC;
1666 TDO1 : in STD_ULOGIC;
1667 TDO2 : in STD_ULOGIC);
1668 end component;
1669
1670 component BSCAN_VIRTEX2
1671 port (CAPTURE : out STD_ULOGIC;
1672 DRCK1 : out STD_ULOGIC;
1673 DRCK2 : out STD_ULOGIC;
1674 RESET : out STD_ULOGIC;
1675 SEL1 : out STD_ULOGIC;
1676 SEL2 : out STD_ULOGIC;
1677 SHIFT : out STD_ULOGIC;
1678 TDI : out STD_ULOGIC;
1679 UPDATE : out STD_ULOGIC;
1680 TDO1 : in STD_ULOGIC;
1681 TDO2 : in STD_ULOGIC);
1682 end component;
1683
1684 component BSCAN_SPARTAN3
1685 port (CAPTURE : out STD_ULOGIC;
1686 DRCK1 : out STD_ULOGIC;
1687 DRCK2 : out STD_ULOGIC;
1688 RESET : out STD_ULOGIC;
1689 SEL1 : out STD_ULOGIC;
1690 SEL2 : out STD_ULOGIC;
1691 SHIFT : out STD_ULOGIC;
1692 TDI : out STD_ULOGIC;
1693 UPDATE : out STD_ULOGIC;
1694 TDO1 : in STD_ULOGIC;
1695 TDO2 : in STD_ULOGIC);
1696 end component;
1697
1698 component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
1699 port ( CAPTURE : out std_ulogic;
1700 DRCK : out std_ulogic;
1701 RESET : out std_ulogic;
1702 SEL : out std_ulogic;
1703 SHIFT : out std_ulogic;
1704 TDI : out std_ulogic;
1705 UPDATE : out std_ulogic;
1706 TDO : in std_ulogic);
1707 end component;
1708
1709 component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
1710 port ( CAPTURE : out std_ulogic;
1711 DRCK : out std_ulogic;
1712 RESET : out std_ulogic;
1713 SEL : out std_ulogic;
1714 SHIFT : out std_ulogic;
1715 TDI : out std_ulogic;
1716 UPDATE : out std_ulogic;
1717 TDO : in std_ulogic);
1718 end component;
1719
1720 component IBUFDS
1721 generic (
1722 CAPACITANCE : string := "DONT_CARE";
1723 DIFF_TERM : boolean := FALSE;
1724 IBUF_DELAY_VALUE : string := "0";
1725 IFD_DELAY_VALUE : string := "AUTO";
1726 IOSTANDARD : string := "DEFAULT");
1727 port (
1728 O : out std_ulogic;
1729 I : in std_ulogic;
1730 IB : in std_ulogic
1731 );
1732 end component;
1733
1734
1735 component IBUFDS_LVDS_25
1736 port ( O : out std_ulogic;
1737 I : in std_ulogic;
1738 IB : in std_ulogic);
1739 end component;
1740
1741 component IBUFGDS_LVDS_25
1742 port ( O : out std_ulogic;
1743 I : in std_ulogic;
1744 IB : in std_ulogic);
1745 end component;
1746
1747 component IOBUFDS
1748 generic(
1749 CAPACITANCE : string := "DONT_CARE";
1750 IBUF_DELAY_VALUE : string := "0";
1751 IFD_DELAY_VALUE : string := "AUTO";
1752 IOSTANDARD : string := "DEFAULT");
1753 port (
1754 O : out std_ulogic;
1755 IO : inout std_ulogic;
1756 IOB : inout std_ulogic;
1757 I : in std_ulogic;
1758 T : in std_ulogic
1759 );
1760 end component;
1761
1762 component OBUFDS
1763 generic(
1764 CAPACITANCE : string := "DONT_CARE";
1765 IOSTANDARD : string := "DEFAULT";
1766 SLEW : string := "SLOW"
1767 );
1768 port(
1769 O : out std_ulogic;
1770 OB : out std_ulogic;
1771 I : in std_ulogic
1772 );
1773 end component;
1774
1775 component OBUFDS_LVDS_25
1776 port ( O : out std_ulogic;
1777 OB : out std_ulogic;
1778 I : in std_ulogic);
1779 end component;
1780
1781 component OBUFTDS_LVDS_25
1782 port ( O : out std_ulogic;
1783 OB : out std_ulogic;
1784 I : in std_ulogic;
1785 T : in std_ulogic);
1786 end component;
1787
1788 component IBUFGDS is
1789 generic( CAPACITANCE : string := "DONT_CARE";
1790 DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
1791 IBUF_LOW_PWR : boolean := TRUE;
1792 IOSTANDARD : string := "DEFAULT");
1793 port (O : out std_logic; I, IB : in std_logic);
1794 end component;
1795
1796 component IBUFDS_LVDS_33
1797 port ( O : out std_ulogic;
1798 I : in std_ulogic;
1799 IB : in std_ulogic);
1800 end component;
1801
1802 component IBUFGDS_LVDS_33
1803 port ( O : out std_ulogic;
1804 I : in std_ulogic;
1805 IB : in std_ulogic);
1806 end component;
1807
1808 component OBUFDS_LVDS_33
1809 port ( O : out std_ulogic;
1810 OB : out std_ulogic;
1811 I : in std_ulogic);
1812 end component;
1813
1814 component OBUFTDS_LVDS_33
1815 port ( O : out std_ulogic;
1816 OB : out std_ulogic;
1817 I : in std_ulogic;
1818 T : in std_ulogic);
1819 end component;
1820
1821 component FDCPE
1822 generic ( INIT : bit := '0');
1823 port (
1824 Q : out std_ulogic;
1825 C : in std_ulogic;
1826 CE : in std_ulogic;
1827 CLR : in std_ulogic;
1828 D : in std_ulogic;
1829 PRE : in std_ulogic);
1830 end component;
1831
1832 component IDDR
1833 generic (
1834 DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
1835 INIT_Q1 : bit := '0';
1836 INIT_Q2 : bit := '0';
1837 SRTYPE : string := "SYNC");
1838 port
1839 (
1840 Q1 : out std_ulogic;
1841 Q2 : out std_ulogic;
1842 C : in std_ulogic;
1843 CE : in std_ulogic;
1844 D : in std_ulogic;
1845 R : in std_ulogic;
1846 S : in std_ulogic);
1847 end component;
1848
1849 component ODDR
1850 generic (
1851 DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
1852 INIT : bit := '0';
1853 SRTYPE : string := "SYNC");
1854 port (
1855 Q : out std_ulogic;
1856 C : in std_ulogic;
1857 CE : in std_ulogic;
1858 D1 : in std_ulogic;
1859 D2 : in std_ulogic;
1860 R : in std_ulogic;
1861 S : in std_ulogic);
1862 end component;
1863
1864 component IFDDRRSE
1865 port (
1866 Q0 : out std_ulogic;
1867 Q1 : out std_ulogic;
1868 C0 : in std_ulogic;
1869 C1 : in std_ulogic;
1870 CE : in std_ulogic;
1871 D : in std_ulogic;
1872 R : in std_ulogic;
1873 S : in std_ulogic);
1874 end component;
1875
1876 component OFDDRRSE
1877 port (
1878 Q : out std_ulogic;
1879 C0 : in std_ulogic;
1880 C1 : in std_ulogic;
1881 CE : in std_ulogic;
1882 D0 : in std_ulogic;
1883 D1 : in std_ulogic;
1884 R : in std_ulogic;
1885 S : in std_ulogic);
1886 end component;
1887
1888 component FDDRRSE
1889 generic ( INIT : bit := '0');
1890 port ( Q : out std_ulogic;
1891 C0 : in std_ulogic;
1892 C1 : in std_ulogic;
1893 CE : in std_ulogic;
1894 D0 : in std_ulogic;
1895 D1 : in std_ulogic;
1896 R : in std_ulogic;
1897 S : in std_ulogic);
1898 end component;
1899
1900
1901 component IDELAY
1902 generic ( IOBDELAY_TYPE : string := "DEFAULT";
1903 IOBDELAY_VALUE : integer := 0);
1904 port ( O : out std_ulogic;
1905 C : in std_ulogic;
1906 CE : in std_ulogic;
1907 I : in std_ulogic;
1908 INC : in std_ulogic;
1909 RST : in std_ulogic);
1910 end component;
1911
1912 component IDELAYCTRL
1913 port ( RDY : out std_ulogic;
1914 REFCLK : in std_ulogic;
1915 RST : in std_ulogic);
1916 end component;
1917
1918 component BUFIO
1919 port ( O : out std_ulogic;
1920 I : in std_ulogic);
1921 end component;
1922
1923 component BUFR
1924 generic ( BUFR_DIVIDE : string := "BYPASS";
1925 SIM_DEVICE : string := "VIRTEX4");
1926 port ( O : out std_ulogic;
1927 CE : in std_ulogic;
1928 CLR : in std_ulogic;
1929 I : in std_ulogic);
1930 end component;
1931
1932 component ODDR2
1933 generic
1934 (
1935 DDR_ALIGNMENT : string := "NONE";
1936 INIT : bit := '0';
1937 SRTYPE : string := "SYNC"
1938 );
1939 port
1940 (
1941 Q : out std_ulogic;
1942 C0 : in std_ulogic;
1943 C1 : in std_ulogic;
1944 CE : in std_ulogic;
1945 D0 : in std_ulogic;
1946 D1 : in std_ulogic;
1947 R : in std_ulogic;
1948 S : in std_ulogic
1949 );
1950 end component;
1951
1952 component IDDR2
1953 generic
1954 (
1955 DDR_ALIGNMENT : string := "NONE";
1956 INIT_Q0 : bit := '0';
1957 INIT_Q1 : bit := '0';
1958 SRTYPE : string := "SYNC"
1959 );
1960 port
1961 (
1962 Q0 : out std_ulogic;
1963 Q1 : out std_ulogic;
1964 C0 : in std_ulogic;
1965 C1 : in std_ulogic;
1966 CE : in std_ulogic;
1967 D : in std_ulogic;
1968 R : in std_ulogic;
1969 S : in std_ulogic
1970 );
1971 end component;
1972
1973 component SYSMON
1974 generic
1975 (
1976 INIT_40 : bit_vector := X"0000";
1977 INIT_41 : bit_vector := X"0000";
1978 INIT_42 : bit_vector := X"0800";
1979 INIT_43 : bit_vector := X"0000";
1980 INIT_44 : bit_vector := X"0000";
1981 INIT_45 : bit_vector := X"0000";
1982 INIT_46 : bit_vector := X"0000";
1983 INIT_47 : bit_vector := X"0000";
1984 INIT_48 : bit_vector := X"0000";
1985 INIT_49 : bit_vector := X"0000";
1986 INIT_4A : bit_vector := X"0000";
1987 INIT_4B : bit_vector := X"0000";
1988 INIT_4C : bit_vector := X"0000";
1989 INIT_4D : bit_vector := X"0000";
1990 INIT_4E : bit_vector := X"0000";
1991 INIT_4F : bit_vector := X"0000";
1992 INIT_50 : bit_vector := X"0000";
1993 INIT_51 : bit_vector := X"0000";
1994 INIT_52 : bit_vector := X"0000";
1995 INIT_53 : bit_vector := X"0000";
1996 INIT_54 : bit_vector := X"0000";
1997 INIT_55 : bit_vector := X"0000";
1998 INIT_56 : bit_vector := X"0000";
1999 INIT_57 : bit_vector := X"0000";
2000 SIM_MONITOR_FILE : string := "design.txt"
2001 );
2002 port
2003 (
2004 ALM : out std_logic_vector(2 downto 0);
2005 BUSY : out std_ulogic;
2006 CHANNEL : out std_logic_vector(4 downto 0);
2007 DO : out std_logic_vector(15 downto 0);
2008 DRDY : out std_ulogic;
2009 EOC : out std_ulogic;
2010 EOS : out std_ulogic;
2011 JTAGBUSY : out std_ulogic;
2012 JTAGLOCKED : out std_ulogic;
2013 JTAGMODIFIED : out std_ulogic;
2014 OT : out std_ulogic;
2015 CONVST : in std_ulogic;
2016 CONVSTCLK : in std_ulogic;
2017 DADDR : in std_logic_vector(6 downto 0);
2018 DCLK : in std_ulogic;
2019 DEN : in std_ulogic;
2020 DI : in std_logic_vector(15 downto 0);
2021 DWE : in std_ulogic;
2022 RESET : in std_ulogic;
2023 VAUXN : in std_logic_vector(15 downto 0);
2024 VAUXP : in std_logic_vector(15 downto 0);
2025 VN : in std_ulogic;
2026 VP : in std_ulogic
2027 );
2028 end component;
2029
2030 component FDRSE
2031 generic ( INIT : bit := '0');
2032 port ( Q : out std_ulogic;
2033 C : in std_ulogic;
2034 CE : in std_ulogic;
2035 D : in std_ulogic;
2036 R : in std_ulogic;
2037 S : in std_ulogic);
2038 end component;
2039
2040 component FDR
2041 generic ( INIT : bit := '0');
2042 port ( Q : out std_ulogic;
2043 C : in std_ulogic;
2044 D : in std_ulogic;
2045 R : in std_ulogic);
2046 end component;
2047
2048 component FDRE
2049 generic ( INIT : bit := '0');
2050 port ( Q : out std_ulogic;
2051 C : in std_ulogic;
2052 CE : in std_ulogic;
2053 D : in std_ulogic;
2054 R : in std_ulogic);
2055 end component;
2056
2057 component FD
2058 generic ( INIT : bit := '0');
2059 port ( Q : out std_ulogic;
2060 C : in std_ulogic;
2061 D : in std_ulogic);
2062 end component;
2063
2064 component FDRS
2065 generic ( INIT : bit := '0');
2066 port ( Q : out std_ulogic;
2067 C : in std_ulogic;
2068 D : in std_ulogic;
2069 R : in std_ulogic;
2070 S : in std_ulogic);
2071 end component;
2072
2073 component FDE
2074 generic ( INIT : bit := '0');
2075 port ( Q : out std_ulogic;
2076 C : in std_ulogic;
2077 CE : in std_ulogic;
2078 D : in std_ulogic);
2079 end component;
2080
2081 component MUXF5
2082 port ( O : out std_ulogic;
2083 I0 : in std_ulogic;
2084 I1 : in std_ulogic;
2085 S : in std_ulogic);
2086 end component;
2087
2088 component VCC
2089 port ( P : out std_ulogic := '1');
2090 end component;
2091
2092 component GND
2093 port ( G : out std_ulogic := '0');
2094 end component;
2095
2096 component INV
2097 port
2098 (
2099 O : out std_ulogic;
2100 I : in std_ulogic
2101 );
2102 end component;
2103 component LUT2_L
2104 generic
2105 (
2106 INIT : bit_vector := X"0"
2107 );
2108 port
2109 (
2110 LO : out std_ulogic;
2111 I0 : in std_ulogic;
2112 I1 : in std_ulogic
2113 );
2114 end component;
2115 component LUT4
2116 generic
2117 (
2118 INIT : bit_vector := X"0000"
2119 );
2120 port
2121 (
2122 O : out std_ulogic;
2123 I0 : in std_ulogic;
2124 I1 : in std_ulogic;
2125 I2 : in std_ulogic;
2126 I3 : in std_ulogic
2127 );
2128 end component;
2129 component LUT3
2130 generic
2131 (
2132 INIT : bit_vector := X"00"
2133 );
2134 port
2135 (
2136 O : out std_ulogic;
2137 I0 : in std_ulogic;
2138 I1 : in std_ulogic;
2139 I2 : in std_ulogic
2140 );
2141 end component;
2142 component LUT2
2143 generic
2144 (
2145 INIT : bit_vector := X"0"
2146 );
2147 port
2148 (
2149 O : out std_ulogic;
2150 I0 : in std_ulogic;
2151 I1 : in std_ulogic
2152 );
2153 end component;
2154 component FDC
2155 generic
2156 (
2157 INIT : bit := '0'
2158 );
2159 port
2160 (
2161 Q : out std_ulogic;
2162 C : in std_ulogic;
2163 CLR : in std_ulogic;
2164 D : in std_ulogic
2165 );
2166 end component;
2167 component LUT3_L
2168 generic
2169 (
2170 INIT : bit_vector := X"00"
2171 );
2172 port
2173 (
2174 LO : out std_ulogic;
2175 I0 : in std_ulogic;
2176 I1 : in std_ulogic;
2177 I2 : in std_ulogic
2178 );
2179 end component;
2180 component LUT1
2181 generic
2182 (
2183 INIT : bit_vector := X"0"
2184 );
2185 port
2186 (
2187 O : out std_ulogic;
2188 I0 : in std_ulogic
2189 );
2190 end component;
2191 component LUT4_L
2192 generic
2193 (
2194 INIT : bit_vector := X"0000"
2195 );
2196 port
2197 (
2198 LO : out std_ulogic;
2199 I0 : in std_ulogic;
2200 I1 : in std_ulogic;
2201 I2 : in std_ulogic;
2202 I3 : in std_ulogic
2203 );
2204 end component;
2205 component FDCE
2206 generic
2207 (
2208 INIT : bit := '0'
2209 );
2210 port
2211 (
2212 Q : out std_ulogic;
2213 C : in std_ulogic;
2214 CE : in std_ulogic;
2215 CLR : in std_ulogic;
2216 D : in std_ulogic
2217 );
2218 end component;
2219 component FDC_1
2220 generic
2221 (
2222 INIT : bit := '0'
2223 );
2224 port
2225 (
2226 Q : out std_ulogic;
2227 C : in std_ulogic;
2228 CLR : in std_ulogic;
2229 D : in std_ulogic
2230 );
2231 end component;
2232 component FDP
2233 generic
2234 (
2235 INIT : bit := '1'
2236 );
2237 port
2238 (
2239 Q : out std_ulogic;
2240 C : in std_ulogic;
2241 D : in std_ulogic;
2242 PRE : in std_ulogic
2243 );
2244 end component;
2245 component FDS
2246 generic
2247 (
2248 INIT : bit := '1'
2249 );
2250 port
2251 (
2252 Q : out std_ulogic;
2253 C : in std_ulogic;
2254 D : in std_ulogic;
2255 S : in std_ulogic
2256 );
2257 end component;
2258 component MUXCY
2259 port
2260 (
2261 O : out std_ulogic;
2262 CI : in std_ulogic;
2263 DI : in std_ulogic;
2264 S : in std_ulogic
2265 );
2266 end component;
2267 component LUT1_L
2268 generic
2269 (
2270 INIT : bit_vector := X"0"
2271 );
2272 port
2273 (
2274 LO : out std_ulogic;
2275 I0 : in std_ulogic
2276 );
2277 end component;
2278 component MUXF6
2279 port
2280 (
2281 O : out std_ulogic;
2282 I0 : in std_ulogic;
2283 I1 : in std_ulogic;
2284 S : in std_ulogic
2285 );
2286 end component;
2287 component MUXF5_D
2288 port
2289 (
2290 LO : out std_ulogic;
2291 O : out std_ulogic;
2292 I0 : in std_ulogic;
2293 I1 : in std_ulogic;
2294 S : in std_ulogic
2295 );
2296 end component;
2297 component XORCY
2298 port
2299 (
2300 O : out std_ulogic;
2301 CI : in std_ulogic;
2302 LI : in std_ulogic
2303 );
2304 end component;
2305 component MUXCY_L
2306 port
2307 (
2308 LO : out std_ulogic;
2309 CI : in std_ulogic;
2310 DI : in std_ulogic;
2311 S : in std_ulogic
2312 );
2313 end component;
2314 component FDSE
2315 generic
2316 (
2317 INIT : bit := '1'
2318 );
2319 port
2320 (
2321 Q : out std_ulogic;
2322 C : in std_ulogic;
2323 CE : in std_ulogic;
2324 D : in std_ulogic;
2325 S : in std_ulogic
2326 );
2327 end component;
2328 component MULT_AND
2329 port
2330 (
2331 LO : out std_ulogic;
2332 I0 : in std_ulogic;
2333 I1 : in std_ulogic
2334 );
2335 end component;
2336
2337 component SRL16E
2338 generic
2339 (
2340 INIT : bit_vector := X"0000"
2341 );
2342 port
2343 (
2344 Q : out STD_ULOGIC;
2345 A0 : in STD_ULOGIC;
2346 A1 : in STD_ULOGIC;
2347 A2 : in STD_ULOGIC;
2348 A3 : in STD_ULOGIC;
2349 CE : in STD_ULOGIC;
2350 CLK : in STD_ULOGIC;
2351 D : in STD_ULOGIC
2352 );
2353 end component;
2354
2355 component ROM256X1
2356 generic
2357 (
2358 INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
2359 );
2360 port
2361 (
2362 O : out std_ulogic;
2363 A0 : in std_ulogic;
2364 A1 : in std_ulogic;
2365 A2 : in std_ulogic;
2366 A3 : in std_ulogic;
2367 A4 : in std_ulogic;
2368 A5 : in std_ulogic;
2369 A6 : in std_ulogic;
2370 A7 : in std_ulogic
2371 );
2372 end component;
2373
2374 component FDPE
2375 generic
2376 (
2377 INIT : bit := '1'
2378 );
2379 port
2380 (
2381 Q : out std_ulogic;
2382 C : in std_ulogic;
2383 CE : in std_ulogic;
2384 D : in std_ulogic;
2385 PRE : in std_ulogic
2386 );
2387 end component;
2388
2389 component MULT18X18
2390 port
2391 (
2392 P : out std_logic_vector (35 downto 0);
2393 A : in std_logic_vector (17 downto 0);
2394 B : in std_logic_vector (17 downto 0)
2395 );
2396 end component;
2397
2398 component MULT18X18S
2399 port
2400 (
2401 P : out std_logic_vector (35 downto 0);
2402 A : in std_logic_vector (17 downto 0);
2403 B : in std_logic_vector (17 downto 0);
2404 C : in std_ulogic;
2405 CE : in std_ulogic;
2406 R : in std_ulogic
2407 );
2408 end component;
2409
2410 component MUXF7
2411 port
2412 (
2413 O : out std_ulogic;
2414 I0 : in std_ulogic;
2415 I1 : in std_ulogic;
2416 S : in std_ulogic
2417 );
2418 end component;
2419
2420 component IODELAY
2421 generic
2422 (
2423 DELAY_SRC : string := "I";
2424 HIGH_PERFORMANCE_MODE : boolean := true;
2425 IDELAY_TYPE : string := "DEFAULT";
2426 IDELAY_VALUE : integer := 0;
2427 ODELAY_VALUE : integer := 0;
2428 REFCLK_FREQUENCY : real := 200.0;
2429 SIGNAL_PATTERN : string := "DATA"
2430 );
2431 port
2432 (
2433 DATAOUT : out std_ulogic;
2434 C : in std_ulogic;
2435 CE : in std_ulogic;
2436 DATAIN : in std_ulogic;
2437 IDATAIN : in std_ulogic;
2438 INC : in std_ulogic;
2439 ODATAIN : in std_ulogic;
2440 RST : in std_ulogic;
2441 T : in std_ulogic
2442 );
2443 end component;
2444
2445 component IODELAY2
2446 generic (
2447 COUNTER_WRAPAROUND : string := "WRAPAROUND";
2448 DATA_RATE : string := "SDR";
2449 DELAY_SRC : string := "IO";
2450 IDELAY2_VALUE : integer := 0;
2451 IDELAY_MODE : string := "NORMAL";
2452 IDELAY_TYPE : string := "DEFAULT";
2453 IDELAY_VALUE : integer := 0;
2454 ODELAY_VALUE : integer := 0;
2455 SERDES_MODE : string := "NONE";
2456 SIM_TAPDELAY_VALUE : integer := 75
2457 );
2458 port (
2459 BUSY : out std_ulogic;
2460 DATAOUT : out std_ulogic;
2461 DATAOUT2 : out std_ulogic;
2462 DOUT : out std_ulogic;
2463 TOUT : out std_ulogic;
2464 CAL : in std_ulogic;
2465 CE : in std_ulogic;
2466 CLK : in std_ulogic;
2467 IDATAIN : in std_ulogic;
2468 INC : in std_ulogic;
2469 IOCLK0 : in std_ulogic;
2470 IOCLK1 : in std_ulogic;
2471 ODATAIN : in std_ulogic;
2472 RST : in std_ulogic;
2473 T : in std_ulogic
2474 );
2475 end component;
2476
2477 component ISERDES
2478 generic
2479 (
2480 BITSLIP_ENABLE : boolean := false;
2481 DATA_RATE : string := "DDR";
2482 DATA_WIDTH : integer := 4;
2483 INIT_Q1 : bit := '0';
2484 INIT_Q2 : bit := '0';
2485 INIT_Q3 : bit := '0';
2486 INIT_Q4 : bit := '0';
2487 INTERFACE_TYPE : string := "MEMORY";
2488 IOBDELAY : string := "NONE";
2489 IOBDELAY_TYPE : string := "DEFAULT";
2490 IOBDELAY_VALUE : integer := 0;
2491 NUM_CE : integer := 2;
2492 SERDES_MODE : string := "MASTER";
2493 SRVAL_Q1 : bit := '0';
2494 SRVAL_Q2 : bit := '0';
2495 SRVAL_Q3 : bit := '0';
2496 SRVAL_Q4 : bit := '0'
2497 );
2498 port
2499 (
2500 O : out std_ulogic;
2501 Q1 : out std_ulogic;
2502 Q2 : out std_ulogic;
2503 Q3 : out std_ulogic;
2504 Q4 : out std_ulogic;
2505 Q5 : out std_ulogic;
2506 Q6 : out std_ulogic;
2507 SHIFTOUT1 : out std_ulogic;
2508 SHIFTOUT2 : out std_ulogic;
2509 BITSLIP : in std_ulogic;
2510 CE1 : in std_ulogic;
2511 CE2 : in std_ulogic;
2512 CLK : in std_ulogic;
2513 CLKDIV : in std_ulogic;
2514 D : in std_ulogic;
2515 DLYCE : in std_ulogic;
2516 DLYINC : in std_ulogic;
2517 DLYRST : in std_ulogic;
2518 OCLK : in std_ulogic;
2519 REV : in std_ulogic;
2520 SHIFTIN1 : in std_ulogic;
2521 SHIFTIN2 : in std_ulogic;
2522 SR : in std_ulogic
2523 );
2524 end component;
2525
2526 component RAM16X1S
2527 generic
2528 (
2529 INIT : bit_vector(15 downto 0) := X"0000"
2530 );
2531 port
2532 (
2533 O : out std_ulogic;
2534 A0 : in std_ulogic;
2535 A1 : in std_ulogic;
2536 A2 : in std_ulogic;
2537 A3 : in std_ulogic;
2538 D : in std_ulogic;
2539 WCLK : in std_ulogic;
2540 WE : in std_ulogic
2541 );
2542 end component;
2543
2544 component RAM16X1D
2545 generic
2546 (
2547 INIT : bit_vector(15 downto 0) := X"0000"
2548 );
2549 port
2550 (
2551 DPO : out std_ulogic;
2552 SPO : out std_ulogic;
2553 A0 : in std_ulogic;
2554 A1 : in std_ulogic;
2555 A2 : in std_ulogic;
2556 A3 : in std_ulogic;
2557 D : in std_ulogic;
2558 DPRA0 : in std_ulogic;
2559 DPRA1 : in std_ulogic;
2560 DPRA2 : in std_ulogic;
2561 DPRA3 : in std_ulogic;
2562 WCLK : in std_ulogic;
2563 WE : in std_ulogic
2564 );
2565 end component;
2566
2567 component ROM32X1
2568 generic
2569 (
2570 INIT : bit_vector := X"00000000"
2571 );
2572 port
2573 (
2574 O : out std_ulogic;
2575 A0 : in std_ulogic;
2576 A1 : in std_ulogic;
2577 A2 : in std_ulogic;
2578 A3 : in std_ulogic;
2579 A4 : in std_ulogic
2580 );
2581 end component;
2582
2583 component DSP48
2584 generic
2585 (
2586 AREG : integer := 1;
2587 B_INPUT : string := "DIRECT";
2588 BREG : integer := 1;
2589 CARRYINREG : integer := 1;
2590 CARRYINSELREG : integer := 1;
2591 CREG : integer := 1;
2592 LEGACY_MODE : string := "MULT18X18S";
2593 MREG : integer := 1;
2594 OPMODEREG : integer := 1;
2595 PREG : integer := 1;
2596 SUBTRACTREG : integer := 1
2597 );
2598 port
2599 (
2600 BCOUT : out std_logic_vector(17 downto 0);
2601 P : out std_logic_vector(47 downto 0);
2602 PCOUT : out std_logic_vector(47 downto 0);
2603 A : in std_logic_vector(17 downto 0);
2604 B : in std_logic_vector(17 downto 0);
2605 BCIN : in std_logic_vector(17 downto 0);
2606 C : in std_logic_vector(47 downto 0);
2607 CARRYIN : in std_ulogic;
2608 CARRYINSEL : in std_logic_vector(1 downto 0);
2609 CEA : in std_ulogic;
2610 CEB : in std_ulogic;
2611 CEC : in std_ulogic;
2612 CECARRYIN : in std_ulogic;
2613 CECINSUB : in std_ulogic;
2614 CECTRL : in std_ulogic;
2615 CEM : in std_ulogic;
2616 CEP : in std_ulogic;
2617 CLK : in std_ulogic;
2618 OPMODE : in std_logic_vector(6 downto 0);
2619 PCIN : in std_logic_vector(47 downto 0);
2620 RSTA : in std_ulogic;
2621 RSTB : in std_ulogic;
2622 RSTC : in std_ulogic;
2623 RSTCARRYIN : in std_ulogic;
2624 RSTCTRL : in std_ulogic;
2625 RSTM : in std_ulogic;
2626 RSTP : in std_ulogic;
2627 SUBTRACT : in std_ulogic
2628 );
2629 end component;
2630
2631 component RAMB16
2632 generic
2633 (
2634 DOA_REG : integer := 0;
2635 DOB_REG : integer := 0;
2636 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2637 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2638 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2639 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2640 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2641 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2642 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2643 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2644 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2645 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2646 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2647 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2648 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2649 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2650 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2651 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2652 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2653 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2654 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2655 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2656 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2657 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2658 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2659 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2660 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2661 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2662 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2663 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2664 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2665 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2666 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2667 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2668 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2669 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2670 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2671 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2672 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2673 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2674 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2675 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2676 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2677 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2678 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2679 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2680 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2681 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2682 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2683 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2684 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2685 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2686 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2687 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2688 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2689 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2690 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2691 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2692 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2693 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2694 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2695 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2696 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2697 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2698 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2699 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2700 INIT_A : bit_vector := X"000000000";
2701 INIT_B : bit_vector := X"000000000";
2702 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2703 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2704 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2705 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2706 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2707 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2708 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2709 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
2710 INVERT_CLK_DOA_REG : boolean := false;
2711 INVERT_CLK_DOB_REG : boolean := false;
2712 RAM_EXTENSION_A : string := "NONE";
2713 RAM_EXTENSION_B : string := "NONE";
2714 READ_WIDTH_A : integer := 0;
2715 READ_WIDTH_B : integer := 0;
2716 SIM_COLLISION_CHECK : string := "ALL";
2717 SRVAL_A : bit_vector := X"000000000";
2718 SRVAL_B : bit_vector := X"000000000";
2719 WRITE_MODE_A : string := "WRITE_FIRST";
2720 WRITE_MODE_B : string := "WRITE_FIRST";
2721 WRITE_WIDTH_A : integer := 0;
2722 WRITE_WIDTH_B : integer := 0
2723 );
2724 port
2725 (
2726 CASCADEOUTA : out std_ulogic;
2727 CASCADEOUTB : out std_ulogic;
2728 DOA : out std_logic_vector (31 downto 0);
2729 DOB : out std_logic_vector (31 downto 0);
2730 DOPA : out std_logic_vector (3 downto 0);
2731 DOPB : out std_logic_vector (3 downto 0);
2732 ADDRA : in std_logic_vector (14 downto 0);
2733 ADDRB : in std_logic_vector (14 downto 0);
2734 CASCADEINA : in std_ulogic;
2735 CASCADEINB : in std_ulogic;
2736 CLKA : in std_ulogic;
2737 CLKB : in std_ulogic;
2738 DIA : in std_logic_vector (31 downto 0);
2739 DIB : in std_logic_vector (31 downto 0);
2740 DIPA : in std_logic_vector (3 downto 0);
2741 DIPB : in std_logic_vector (3 downto 0);
2742 ENA : in std_ulogic;
2743 ENB : in std_ulogic;
2744 REGCEA : in std_ulogic;
2745 REGCEB : in std_ulogic;
2746 SSRA : in std_ulogic;
2747 SSRB : in std_ulogic;
2748 WEA : in std_logic_vector (3 downto 0);
2749 WEB : in std_logic_vector (3 downto 0)
2750 );
2751 end component;
2752
2753 component MUXF8
2754 port
2755 (
2756 O : out std_ulogic;
2757 I0 : in std_ulogic;
2758 I1 : in std_ulogic;
2759 S : in std_ulogic
2760 );
2761 end component;
2762
2763 component RAM64X1D
2764 generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
2765 port
2766 (
2767 DPO : out std_ulogic;
2768 SPO : out std_ulogic;
2769 A0 : in std_ulogic;
2770 A1 : in std_ulogic;
2771 A2 : in std_ulogic;
2772 A3 : in std_ulogic;
2773 A4 : in std_ulogic;
2774 A5 : in std_ulogic;
2775 D : in std_ulogic;
2776 DPRA0 : in std_ulogic;
2777 DPRA1 : in std_ulogic;
2778 DPRA2 : in std_ulogic;
2779 DPRA3 : in std_ulogic;
2780 DPRA4 : in std_ulogic;
2781 DPRA5 : in std_ulogic;
2782 WCLK : in std_ulogic;
2783 WE : in std_ulogic
2784 );
2785 end component;
2786
2787
2788 component BUF
2789 port
2790 (
2791 O : out std_ulogic;
2792 I : in std_ulogic
2793 );
2794 end component;
2795 component LUT5
2796 generic
2797 (
2798 INIT : bit_vector := X"00000000"
2799 );
2800 port
2801 (
2802 O : out std_ulogic;
2803 I0 : in std_ulogic;
2804 I1 : in std_ulogic;
2805 I2 : in std_ulogic;
2806 I3 : in std_ulogic;
2807 I4 : in std_ulogic
2808 );
2809 end component;
2810 component LUT5_L
2811 generic
2812 (
2813 INIT : bit_vector := X"00000000"
2814 );
2815 port
2816 (
2817 LO : out std_ulogic;
2818 I0 : in std_ulogic;
2819 I1 : in std_ulogic;
2820 I2 : in std_ulogic;
2821 I3 : in std_ulogic;
2822 I4 : in std_ulogic
2823 );
2824 end component;
2825 component LUT6
2826 generic
2827 (
2828 INIT : bit_vector := X"0000000000000000"
2829 );
2830 port
2831 (
2832 O : out std_ulogic;
2833 I0 : in std_ulogic;
2834 I1 : in std_ulogic;
2835 I2 : in std_ulogic;
2836 I3 : in std_ulogic;
2837 I4 : in std_ulogic;
2838 I5 : in std_ulogic
2839 );
2840 end component;
2841 component LUT6_L
2842 generic
2843 (
2844 INIT : bit_vector := X"0000000000000000"
2845 );
2846 port
2847 (
2848 LO : out std_ulogic;
2849 I0 : in std_ulogic;
2850 I1 : in std_ulogic;
2851 I2 : in std_ulogic;
2852 I3 : in std_ulogic;
2853 I4 : in std_ulogic;
2854 I5 : in std_ulogic
2855 );
2856 end component;
2857
2858 component RAM128X1S
2859
2860 generic (
2861 INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
2862 );
2863
2864 port (
2865 O : out std_ulogic;
2866
2867 A0 : in std_ulogic;
2868 A1 : in std_ulogic;
2869 A2 : in std_ulogic;
2870 A3 : in std_ulogic;
2871 A4 : in std_ulogic;
2872 A5 : in std_ulogic;
2873 A6 : in std_ulogic;
2874 D : in std_ulogic;
2875 WCLK : in std_ulogic;
2876 WE : in std_ulogic
2877 );
2878 end component;
2879
2880 component SRLC16E
2881
2882 generic (
2883 INIT : bit_vector := X"0000"
2884 );
2885
2886 port (
2887 Q : out STD_ULOGIC;
2888 Q15 : out STD_ULOGIC;
2889
2890 A0 : in STD_ULOGIC;
2891 A1 : in STD_ULOGIC;
2892 A2 : in STD_ULOGIC;
2893 A3 : in STD_ULOGIC;
2894 CE : in STD_ULOGIC;
2895 CLK : in STD_ULOGIC;
2896 D : in STD_ULOGIC
2897 );
2898 end component;
2899
2900 component LD_1
2901 generic(
2902 INIT : bit := '0'
2903 );
2904
2905 port(
2906 Q : out std_ulogic := '0';
2907
2908 D : in std_ulogic;
2909 G : in std_ulogic
2910 );
2911 end component;
2912
2913 component RAM32X1D
2914
2915 generic (
2916 INIT : bit_vector(31 downto 0) := X"00000000"
2917 );
2918
2919 port (
2920 DPO : out std_ulogic;
2921 SPO : out std_ulogic;
2922
2923 A0 : in std_ulogic;
2924 A1 : in std_ulogic;
2925 A2 : in std_ulogic;
2926 A3 : in std_ulogic;
2927 A4 : in std_ulogic;
2928 D : in std_ulogic;
2929 DPRA0 : in std_ulogic;
2930 DPRA1 : in std_ulogic;
2931 DPRA2 : in std_ulogic;
2932 DPRA3 : in std_ulogic;
2933 DPRA4 : in std_ulogic;
2934 WCLK : in std_ulogic;
2935 WE : in std_ulogic
2936 );
2937 end component;
2938
2939 component FD_1
2940 generic(
2941 INIT : bit := '0'
2942 );
2943
2944 port(
2945 Q : out std_ulogic;
2946
2947 C : in std_ulogic;
2948 D : in std_ulogic
2949 );
2950 end component;
2951
2952 component XORCY_L
2953 port(
2954 LO : out std_ulogic;
2955
2956 CI : in std_ulogic;
2957 LI : in std_ulogic
2958 );
2959 end component;
2960
2961 component RAM32M
2962 generic (
2963 INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
2964 INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
2965 INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
2966 INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
2967 );
2968
2969 port (
2970 DOA : out std_logic_vector (1 downto 0);
2971 DOB : out std_logic_vector (1 downto 0);
2972 DOC : out std_logic_vector (1 downto 0);
2973 DOD : out std_logic_vector (1 downto 0);
2974
2975 ADDRA : in std_logic_vector(4 downto 0);
2976 ADDRB : in std_logic_vector(4 downto 0);
2977 ADDRC : in std_logic_vector(4 downto 0);
2978 ADDRD : in std_logic_vector(4 downto 0);
2979 DIA : in std_logic_vector (1 downto 0);
2980 DIB : in std_logic_vector (1 downto 0);
2981 DIC : in std_logic_vector (1 downto 0);
2982 DID : in std_logic_vector (1 downto 0);
2983 WCLK : in std_ulogic;
2984 WE : in std_ulogic
2985 );
2986 end component;
2987
2988 component RAM128X1D
2989 generic
2990 (
2991 INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
2992 );
2993 port
2994 (
2995 DPO : out std_ulogic;
2996 SPO : out std_ulogic;
2997 A : in std_logic_vector(6 downto 0);
2998 D : in std_ulogic;
2999 DPRA : in std_logic_vector(6 downto 0);
3000 WCLK : in std_ulogic;
3001 WE : in std_ulogic
3002 );
3003 end component;
3004
3005 component RAM64M
3006 generic (
3007 INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
3008 INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
3009 INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
3010 INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
3011 );
3012
3013 port (
3014 DOA : out std_ulogic;
3015 DOB : out std_ulogic;
3016 DOC : out std_ulogic;
3017 DOD : out std_ulogic;
3018
3019 ADDRA : in std_logic_vector(5 downto 0);
3020 ADDRB : in std_logic_vector(5 downto 0);
3021 ADDRC : in std_logic_vector(5 downto 0);
3022 ADDRD : in std_logic_vector(5 downto 0);
3023 DIA : in std_ulogic;
3024 DIB : in std_ulogic;
3025 DIC : in std_ulogic;
3026 DID : in std_ulogic;
3027 WCLK : in std_ulogic;
3028 WE : in std_ulogic
3029 );
3030 end component;
3031
3032 component XOR2
3033 port(
3034 O : out std_ulogic;
3035
3036 I0 : in std_ulogic;
3037 I1 : in std_ulogic
3038 );
3039 end component;
3040
3041 component BSCANE2
3042 generic (
3043 DISABLE_JTAG : string := "FALSE";
3044 JTAG_CHAIN : integer := 1
3045 );
3046 port (
3047 CAPTURE : out std_ulogic := 'H';
3048 DRCK : out std_ulogic := 'H';
3049 RESET : out std_ulogic := 'H';
3050 RUNTEST : out std_ulogic := 'L';
3051 SEL : out std_ulogic := 'L';
3052 SHIFT : out std_ulogic := 'L';
3053 TCK : out std_ulogic := 'L';
3054 TDI : out std_ulogic := 'L';
3055 TMS : out std_ulogic := 'L';
3056 UPDATE : out std_ulogic := 'L';
3057 TDO : in std_ulogic := 'X'
3058 );
3059 end component;
3060
3061 component BSCAN_SPARTAN6
3062 generic (
3063 JTAG_CHAIN : integer := 1
3064 );
3065 port (
3066 CAPTURE : out std_ulogic := 'H';
3067 DRCK : out std_ulogic := 'H';
3068 RESET : out std_ulogic := 'H';
3069 RUNTEST : out std_ulogic := 'L';
3070 SEL : out std_ulogic := 'L';
3071 SHIFT : out std_ulogic := 'L';
3072 TCK : out std_ulogic := 'L';
3073 TDI : out std_ulogic := 'L';
3074 TMS : out std_ulogic := 'L';
3075 UPDATE : out std_ulogic := 'L';
3076 TDO : in std_ulogic := 'X'
3077 );
3078 end component;
3079
3080 component BSCAN_VIRTEX6
3081 generic (
3082 DISABLE_JTAG : boolean := FALSE;
3083 JTAG_CHAIN : integer := 1
3084 );
3085 port (
3086 CAPTURE : out std_ulogic := 'H';
3087 DRCK : out std_ulogic := 'H';
3088 RESET : out std_ulogic := 'H';
3089 RUNTEST : out std_ulogic := 'L';
3090 SEL : out std_ulogic := 'L';
3091 SHIFT : out std_ulogic := 'L';
3092 TCK : out std_ulogic := 'L';
3093 TDI : out std_ulogic := 'L';
3094 TMS : out std_ulogic := 'L';
3095 UPDATE : out std_ulogic := 'L';
3096 TDO : in std_ulogic := 'X'
3097 );
3098 end component;
3099
3100 component SRL16
3101 generic ( INIT : bit_vector := X"0000");
3102 port (
3103 Q : out STD_ULOGIC;
3104 A0 : in STD_ULOGIC;
3105 A1 : in STD_ULOGIC;
3106 A2 : in STD_ULOGIC;
3107 A3 : in STD_ULOGIC;
3108 CLK : in STD_ULOGIC;
3109 D : in STD_ULOGIC);
3110 end component;
3111
3112 component LUT6_2
3113 generic(
3114 INIT : bit_vector := X"0000000000000000"
3115 );
3116
3117 port(
3118 O5 : out std_ulogic;
3119 O6 : out std_ulogic;
3120
3121 I0 : in std_ulogic;
3122 I1 : in std_ulogic;
3123 I2 : in std_ulogic;
3124 I3 : in std_ulogic;
3125 I4 : in std_ulogic;
3126 I5 : in std_ulogic
3127 );
3128 end component;
3129
3130 component DSP48E
3131
3132 generic(
3133
3134 SIM_MODE : string := "SAFE";
3135
3136 ACASCREG : integer := 1;
3137 ALUMODEREG : integer := 1;
3138 AREG : integer := 1;
3139 AUTORESET_PATTERN_DETECT : boolean := FALSE;
3140 AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH";
3141 A_INPUT : string := "DIRECT";
3142 BCASCREG : integer := 1;
3143 BREG : integer := 1;
3144 B_INPUT : string := "DIRECT";
3145 CARRYINREG : integer := 1;
3146 CARRYINSELREG : integer := 1;
3147 CREG : integer := 1;
3148 MASK : bit_vector := X"3FFFFFFFFFFF";
3149 MREG : integer := 1;
3150 MULTCARRYINREG : integer := 1;
3151 OPMODEREG : integer := 1;
3152 PATTERN : bit_vector := X"000000000000";
3153 PREG : integer := 1;
3154 SEL_MASK : string := "MASK";
3155 SEL_PATTERN : string := "PATTERN";
3156 SEL_ROUNDING_MASK : string := "SEL_MASK";
3157 USE_MULT : string := "MULT_S";
3158 USE_PATTERN_DETECT : string := "NO_PATDET";
3159 USE_SIMD : string := "ONE48"
3160 );
3161
3162 port(
3163 ACOUT : out std_logic_vector(29 downto 0);
3164 BCOUT : out std_logic_vector(17 downto 0);
3165 CARRYCASCOUT : out std_ulogic;
3166 CARRYOUT : out std_logic_vector(3 downto 0);
3167 MULTSIGNOUT : out std_ulogic;
3168 OVERFLOW : out std_ulogic;
3169 P : out std_logic_vector(47 downto 0);
3170 PATTERNBDETECT : out std_ulogic;
3171 PATTERNDETECT : out std_ulogic;
3172 PCOUT : out std_logic_vector(47 downto 0);
3173 UNDERFLOW : out std_ulogic;
3174
3175 A : in std_logic_vector(29 downto 0);
3176 ACIN : in std_logic_vector(29 downto 0);
3177 ALUMODE : in std_logic_vector(3 downto 0);
3178 B : in std_logic_vector(17 downto 0);
3179 BCIN : in std_logic_vector(17 downto 0);
3180 C : in std_logic_vector(47 downto 0);
3181 CARRYCASCIN : in std_ulogic;
3182 CARRYIN : in std_ulogic;
3183 CARRYINSEL : in std_logic_vector(2 downto 0);
3184 CEA1 : in std_ulogic;
3185 CEA2 : in std_ulogic;
3186 CEALUMODE : in std_ulogic;
3187 CEB1 : in std_ulogic;
3188 CEB2 : in std_ulogic;
3189 CEC : in std_ulogic;
3190 CECARRYIN : in std_ulogic;
3191 CECTRL : in std_ulogic;
3192 CEM : in std_ulogic;
3193 CEMULTCARRYIN : in std_ulogic;
3194 CEP : in std_ulogic;
3195 CLK : in std_ulogic;
3196 MULTSIGNIN : in std_ulogic;
3197 OPMODE : in std_logic_vector(6 downto 0);
3198 PCIN : in std_logic_vector(47 downto 0);
3199 RSTA : in std_ulogic;
3200 RSTALLCARRYIN : in std_ulogic;
3201 RSTALUMODE : in std_ulogic;
3202 RSTB : in std_ulogic;
3203 RSTC : in std_ulogic;
3204 RSTCTRL : in std_ulogic;
3205 RSTM : in std_ulogic;
3206 RSTP : in std_ulogic
3207 );
3208
3209 end component;
3210
3211 component RAMB18
3212 generic (
3213
3214 DOA_REG : integer := 0;
3215 DOB_REG : integer := 0;
3216 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3217 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3218 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3219 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3220 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3221 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3222 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3223 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3224 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3225 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3226 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3227 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3228 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3229 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3230 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3231 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3232 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3233 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3234 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3235 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3236 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3237 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3238 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3239 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3240 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3241 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3242 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3243 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3244 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3245 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3246 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3247 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3248 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3249 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3250 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3251 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3252 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3253 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3254 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3255 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3256 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3257 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3258 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3259 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3260 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3261 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3262 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3263 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3264 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3265 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3266 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3267 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3268 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3269 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3270 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3271 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3272 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3273 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3274 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3275 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3276 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3277 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3278 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3279 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3280 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3281 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3282 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3283 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3284 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3285 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3286 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3287 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3288 INIT_A : bit_vector := X"00000";
3289 INIT_B : bit_vector := X"00000";
3290 INIT_FILE : string := "NONE";
3291 READ_WIDTH_A : integer := 0;
3292 READ_WIDTH_B : integer := 0;
3293 SIM_COLLISION_CHECK : string := "ALL";
3294 SIM_MODE : string := "SAFE";
3295 SRVAL_A : bit_vector := X"00000";
3296 SRVAL_B : bit_vector := X"00000";
3297 WRITE_MODE_A : string := "WRITE_FIRST";
3298 WRITE_MODE_B : string := "WRITE_FIRST";
3299 WRITE_WIDTH_A : integer := 0;
3300 WRITE_WIDTH_B : integer := 0
3301
3302 );
3303
3304 port (
3305
3306 DOA : out std_logic_vector(15 downto 0);
3307 DOB : out std_logic_vector(15 downto 0);
3308 DOPA : out std_logic_vector(1 downto 0);
3309 DOPB : out std_logic_vector(1 downto 0);
3310
3311 ADDRA : in std_logic_vector(13 downto 0);
3312 ADDRB : in std_logic_vector(13 downto 0);
3313 CLKA : in std_ulogic;
3314 CLKB : in std_ulogic;
3315 DIA : in std_logic_vector(15 downto 0);
3316 DIB : in std_logic_vector(15 downto 0);
3317 DIPA : in std_logic_vector(1 downto 0);
3318 DIPB : in std_logic_vector(1 downto 0);
3319 ENA : in std_ulogic;
3320 ENB : in std_ulogic;
3321 REGCEA : in std_ulogic;
3322 REGCEB : in std_ulogic;
3323 SSRA : in std_ulogic;
3324 SSRB : in std_ulogic;
3325 WEA : in std_logic_vector(1 downto 0);
3326 WEB : in std_logic_vector(1 downto 0)
3327
3328 );
3329 end component;
3330
3331 component RAMB36
3332 generic (
3333
3334 DOA_REG : integer := 0;
3335 DOB_REG : integer := 0;
3336 INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3337 INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3338 INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3339 INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3340 INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3341 INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3342 INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3343 INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3344 INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3345 INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3346 INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3347 INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3348 INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3349 INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3350 INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3351 INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3352 INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3353 INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3354 INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3355 INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3356 INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3357 INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3358 INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3359 INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3360 INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3361 INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3362 INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3363 INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3364 INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3365 INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3366 INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3367 INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3368 INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3369 INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3370 INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3371 INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3372 INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3373 INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3374 INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3375 INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3376 INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3377 INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3378 INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3379 INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3380 INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3381 INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3382 INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3383 INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3384 INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3385 INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3386 INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3387 INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3388 INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3389 INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3390 INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3391 INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3392 INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3393 INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3394 INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3395 INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3396 INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3397 INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3398 INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3399 INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3400 INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3401 INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3402 INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3403 INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3404 INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3405 INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3406 INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3407 INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3408 INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3409 INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3410 INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3411 INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3412 INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3413 INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3414 INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3415 INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3416 INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3417 INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3418 INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3419 INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3420 INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3421 INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3422 INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3423 INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3424 INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3425 INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3426 INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3427 INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3428 INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3429 INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3430 INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3431 INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3432 INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3433 INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3434 INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3435 INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3436 INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3437 INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3438 INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3439 INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3440 INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3441 INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3442 INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3443 INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3444 INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3445 INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3446 INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3447 INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3448 INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3449 INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3450 INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3451 INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3452 INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3453 INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3454 INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3455 INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3456 INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3457 INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3458 INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3459 INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3460 INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3461 INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3462 INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3463 INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3464 INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3465 INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3466 INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3467 INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3468 INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3469 INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3470 INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3471 INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3472 INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3473 INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3474 INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3475 INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3476 INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3477 INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3478 INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3479 INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
3480 INIT_A : bit_vector := X"000000000";
3481 INIT_B : bit_vector := X"000000000";
3482 INIT_FILE : string := "NONE";
3483 RAM_EXTENSION_A : string := "NONE";
3484 RAM_EXTENSION_B : string := "NONE";
3485 READ_WIDTH_A : integer := 0;
3486 READ_WIDTH_B : integer := 0;
3487 SIM_COLLISION_CHECK : string := "ALL";
3488 SIM_MODE : string := "SAFE";
3489 SRVAL_A : bit_vector := X"000000000";
3490 SRVAL_B : bit_vector := X"000000000";
3491 WRITE_MODE_A : string := "WRITE_FIRST";
3492 WRITE_MODE_B : string := "WRITE_FIRST";
3493 WRITE_WIDTH_A : integer := 0;
3494 WRITE_WIDTH_B : integer := 0
3495
3496 );
3497
3498 port (
3499
3500 CASCADEOUTLATA : out std_ulogic;
3501 CASCADEOUTLATB : out std_ulogic;
3502 CASCADEOUTREGA : out std_ulogic;
3503 CASCADEOUTREGB : out std_ulogic;
3504 DOA : out std_logic_vector(31 downto 0);
3505 DOB : out std_logic_vector(31 downto 0);
3506 DOPA : out std_logic_vector(3 downto 0);
3507 DOPB : out std_logic_vector(3 downto 0);
3508
3509 ADDRA : in std_logic_vector(15 downto 0);
3510 ADDRB : in std_logic_vector(15 downto 0);
3511 CASCADEINLATA : in std_ulogic;
3512 CASCADEINLATB : in std_ulogic;
3513 CASCADEINREGA : in std_ulogic;
3514 CASCADEINREGB : in std_ulogic;
3515 CLKA : in std_ulogic;
3516 CLKB : in std_ulogic;
3517 DIA : in std_logic_vector(31 downto 0);
3518 DIB : in std_logic_vector(31 downto 0);
3519 DIPA : in std_logic_vector(3 downto 0);
3520 DIPB : in std_logic_vector(3 downto 0);
3521 ENA : in std_ulogic;
3522 ENB : in std_ulogic;
3523 REGCEA : in std_ulogic;
3524 REGCEB : in std_ulogic;
3525 SSRA : in std_ulogic;
3526 SSRB : in std_ulogic;
3527 WEA : in std_logic_vector(3 downto 0);
3528 WEB : in std_logic_vector(3 downto 0)
3529
3530 );
3531 end component;
3532
3533 component BUFGCE
3534 port(
3535 O : out STD_ULOGIC;
3536
3537 CE: in STD_ULOGIC;
3538 I : in STD_ULOGIC
3539 );
3540 end component;
3541
3542 component RAM64X1S
3543 generic (
3544 INIT : bit_vector(63 downto 0) := X"0000000000000000"
3545 );
3546
3547 port (
3548 O : out std_ulogic;
3549
3550 A0 : in std_ulogic;
3551 A1 : in std_ulogic;
3552 A2 : in std_ulogic;
3553 A3 : in std_ulogic;
3554 A4 : in std_ulogic;
3555 A5 : in std_ulogic;
3556 D : in std_ulogic;
3557 WCLK : in std_ulogic;
3558 WE : in std_ulogic
3559 );
3560 end component;
3561
3562 component IBUFDS_GTXE1
3563 generic (
3564 CLKCM_CFG : boolean := TRUE;
3565 CLKRCV_TRST : boolean := TRUE;
3566 REFCLKOUT_DLY : bit_vector := b"0000000000"
3567 );
3568 port (
3569 O : out std_ulogic;
3570 ODIV2 : out std_ulogic;
3571 CEB : in std_ulogic;
3572 I : in std_ulogic;
3573 IB : in std_ulogic
3574 );
3575 end component;
3576
3577 ----- component MMCM_ADV -----
3578 component MMCM_ADV
3579 generic (
3580 BANDWIDTH : string := "OPTIMIZED";
3581 CLKFBOUT_MULT_F : real := 5.000;
3582 CLKFBOUT_PHASE : real := 0.000;
3583 CLKFBOUT_USE_FINE_PS : boolean := FALSE;
3584 CLKIN1_PERIOD : real := 0.000;
3585 CLKIN2_PERIOD : real := 0.000;
3586 CLKOUT0_DIVIDE_F : real := 1.000;
3587 CLKOUT0_DUTY_CYCLE : real := 0.500;
3588 CLKOUT0_PHASE : real := 0.000;
3589 CLKOUT0_USE_FINE_PS : boolean := FALSE;
3590 CLKOUT1_DIVIDE : integer := 1;
3591 CLKOUT1_DUTY_CYCLE : real := 0.500;
3592 CLKOUT1_PHASE : real := 0.000;
3593 CLKOUT1_USE_FINE_PS : boolean := FALSE;
3594 CLKOUT2_DIVIDE : integer := 1;
3595 CLKOUT2_DUTY_CYCLE : real := 0.500;
3596 CLKOUT2_PHASE : real := 0.000;
3597 CLKOUT2_USE_FINE_PS : boolean := FALSE;
3598 CLKOUT3_DIVIDE : integer := 1;
3599 CLKOUT3_DUTY_CYCLE : real := 0.500;
3600 CLKOUT3_PHASE : real := 0.000;
3601 CLKOUT3_USE_FINE_PS : boolean := FALSE;
3602 CLKOUT4_CASCADE : boolean := FALSE;
3603 CLKOUT4_DIVIDE : integer := 1;
3604 CLKOUT4_DUTY_CYCLE : real := 0.500;
3605 CLKOUT4_PHASE : real := 0.000;
3606 CLKOUT4_USE_FINE_PS : boolean := FALSE;
3607 CLKOUT5_DIVIDE : integer := 1;
3608 CLKOUT5_DUTY_CYCLE : real := 0.500;
3609 CLKOUT5_PHASE : real := 0.000;
3610 CLKOUT5_USE_FINE_PS : boolean := FALSE;
3611 CLKOUT6_DIVIDE : integer := 1;
3612 CLKOUT6_DUTY_CYCLE : real := 0.500;
3613 CLKOUT6_PHASE : real := 0.000;
3614 CLKOUT6_USE_FINE_PS : boolean := FALSE;
3615 CLOCK_HOLD : boolean := FALSE;
3616 COMPENSATION : string := "ZHOLD";
3617 DIVCLK_DIVIDE : integer := 1;
3618 REF_JITTER1 : real := 0.0;
3619 REF_JITTER2 : real := 0.0;
3620 STARTUP_WAIT : boolean := FALSE
3621 );
3622 port (
3623 CLKFBOUT : out std_ulogic := '0';
3624 CLKFBOUTB : out std_ulogic := '0';
3625 CLKFBSTOPPED : out std_ulogic := '0';
3626 CLKINSTOPPED : out std_ulogic := '0';
3627 CLKOUT0 : out std_ulogic := '0';
3628 CLKOUT0B : out std_ulogic := '0';
3629 CLKOUT1 : out std_ulogic := '0';
3630 CLKOUT1B : out std_ulogic := '0';
3631 CLKOUT2 : out std_ulogic := '0';
3632 CLKOUT2B : out std_ulogic := '0';
3633 CLKOUT3 : out std_ulogic := '0';
3634 CLKOUT3B : out std_ulogic := '0';
3635 CLKOUT4 : out std_ulogic := '0';
3636 CLKOUT5 : out std_ulogic := '0';
3637 CLKOUT6 : out std_ulogic := '0';
3638 DO : out std_logic_vector (15 downto 0);
3639 DRDY : out std_ulogic := '0';
3640 LOCKED : out std_ulogic := '0';
3641 PSDONE : out std_ulogic := '0';
3642 CLKFBIN : in std_ulogic;
3643 CLKIN1 : in std_ulogic;
3644 CLKIN2 : in std_ulogic;
3645 CLKINSEL : in std_ulogic;
3646 DADDR : in std_logic_vector(6 downto 0);
3647 DCLK : in std_ulogic;
3648 DEN : in std_ulogic;
3649 DI : in std_logic_vector(15 downto 0);
3650 DWE : in std_ulogic;
3651 PSCLK : in std_ulogic;
3652 PSEN : in std_ulogic;
3653 PSINCDEC : in std_ulogic;
3654 PWRDWN : in std_ulogic;
3655 RST : in std_ulogic
3656 );
3657 end component;
3658
3659 component OSERDESE1
3660 generic (
3661 DATA_RATE_OQ : string := "DDR";
3662 DATA_RATE_TQ : string := "DDR";
3663 DATA_WIDTH : integer := 4;
3664 DDR3_DATA : integer := 1;
3665 INIT_OQ : bit := '0';
3666 INIT_TQ : bit := '0';
3667 INTERFACE_TYPE : string := "DEFAULT";
3668 ODELAY_USED : integer := 0;
3669 SERDES_MODE : string := "MASTER";
3670 SRVAL_OQ : bit := '0';
3671 SRVAL_TQ : bit := '0';
3672 TRISTATE_WIDTH : integer := 4
3673 );
3674 port (
3675 OCBEXTEND : out std_ulogic;
3676 OFB : out std_ulogic;
3677 OQ : out std_ulogic;
3678 SHIFTOUT1 : out std_ulogic;
3679 SHIFTOUT2 : out std_ulogic;
3680 TFB : out std_ulogic;
3681 TQ : out std_ulogic;
3682 CLK : in std_ulogic;
3683 CLKDIV : in std_ulogic;
3684 CLKPERF : in std_ulogic;
3685 CLKPERFDELAY : in std_ulogic;
3686 D1 : in std_ulogic;
3687 D2 : in std_ulogic;
3688 D3 : in std_ulogic;
3689 D4 : in std_ulogic;
3690 D5 : in std_ulogic;
3691 D6 : in std_ulogic;
3692 OCE : in std_ulogic;
3693 ODV : in std_ulogic;
3694 RST : in std_ulogic;
3695 SHIFTIN1 : in std_ulogic;
3696 SHIFTIN2 : in std_ulogic;
3697 T1 : in std_ulogic;
3698 T2 : in std_ulogic;
3699 T3 : in std_ulogic;
3700 T4 : in std_ulogic;
3701 TCE : in std_ulogic;
3702 WC : in std_ulogic
3703 );
3704 end component;
3705
3706 component IODELAYE1
3707 generic (
3708 CINVCTRL_SEL : boolean := FALSE;
3709 DELAY_SRC : string := "I";
3710 HIGH_PERFORMANCE_MODE : boolean := FALSE;
3711 IDELAY_TYPE : string := "DEFAULT";
3712 IDELAY_VALUE : integer := 0;
3713 ODELAY_TYPE : string := "FIXED";
3714 ODELAY_VALUE : integer := 0;
3715 REFCLK_FREQUENCY : real := 200.0;
3716 SIGNAL_PATTERN : string := "DATA"
3717 );
3718 port (
3719 CNTVALUEOUT : out std_logic_vector(4 downto 0);
3720 DATAOUT : out std_ulogic;
3721 C : in std_ulogic;
3722 CE : in std_ulogic;
3723 CINVCTRL : in std_ulogic;
3724 CLKIN : in std_ulogic;
3725 CNTVALUEIN : in std_logic_vector(4 downto 0);
3726 DATAIN : in std_ulogic;
3727 IDATAIN : in std_ulogic;
3728 INC : in std_ulogic;
3729 ODATAIN : in std_ulogic;
3730 RST : in std_ulogic;
3731 T : in std_ulogic
3732 );
3733 end component;
3734
3735 component ISERDESE1
3736 generic (
3737 DATA_RATE : string := "DDR";
3738 DATA_WIDTH : integer := 4;
3739 DYN_CLKDIV_INV_EN : boolean := FALSE;
3740 DYN_CLK_INV_EN : boolean := FALSE;
3741 INIT_Q1 : bit := '0';
3742 INIT_Q2 : bit := '0';
3743 INIT_Q3 : bit := '0';
3744 INIT_Q4 : bit := '0';
3745 INTERFACE_TYPE : string := "MEMORY";
3746 IOBDELAY : string := "NONE";
3747 NUM_CE : integer := 2;
3748 OFB_USED : boolean := FALSE;
3749 SERDES_MODE : string := "MASTER";
3750 SRVAL_Q1 : bit := '0';
3751 SRVAL_Q2 : bit := '0';
3752 SRVAL_Q3 : bit := '0';
3753 SRVAL_Q4 : bit := '0'
3754 );
3755 port (
3756 O : out std_ulogic;
3757 Q1 : out std_ulogic;
3758 Q2 : out std_ulogic;
3759 Q3 : out std_ulogic;
3760 Q4 : out std_ulogic;
3761 Q5 : out std_ulogic;
3762 Q6 : out std_ulogic;
3763 SHIFTOUT1 : out std_ulogic;
3764 SHIFTOUT2 : out std_ulogic;
3765 BITSLIP : in std_ulogic;
3766 CE1 : in std_ulogic;
3767 CE2 : in std_ulogic;
3768 CLK : in std_ulogic;
3769 CLKB : in std_ulogic;
3770 CLKDIV : in std_ulogic;
3771 D : in std_ulogic;
3772 DDLY : in std_ulogic;
3773 DYNCLKDIVSEL : in std_ulogic;
3774 DYNCLKSEL : in std_ulogic;
3775 OCLK : in std_ulogic;
3776 OFB : in std_ulogic;
3777 RST : in std_ulogic;
3778 SHIFTIN1 : in std_ulogic;
3779 SHIFTIN2 : in std_ulogic
3780 );
3781 end component;
3782
3783 component IOBUFDS_DIFF_OUT
3784 generic (
3785 DIFF_TERM : boolean := FALSE;
3786 IBUF_LOW_PWR : boolean := TRUE;
3787 IOSTANDARD : string := "DEFAULT"
3788 );
3789 port (
3790 O : out std_ulogic;
3791 OB : out std_ulogic;
3792 IO : inout std_ulogic;
3793 IOB : inout std_ulogic;
3794 I : in std_ulogic;
3795 TM : in std_ulogic;
3796 TS : in std_ulogic
3797 );
3798 end component;
3799
3800 component SRLC32E
3801 generic (
3802 INIT : bit_vector := X"00000000"
3803 );
3804 port (
3805 Q : out STD_ULOGIC;
3806 Q31 : out STD_ULOGIC;
3807 A : in STD_LOGIC_VECTOR (4 downto 0);
3808 CE : in STD_ULOGIC;
3809 CLK : in STD_ULOGIC;
3810 D : in STD_ULOGIC
3811 );
3812 end component;
3813
3814 end;
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1 #================================================================================================
2 #
3 # _| _| _| _| _|_|_|_|_| _|
4 # _| _| _|_|_| _|_|_| _|_|_| _| _|_| _|_| _| _|_|_
5 # _|_| _| _| _| _| _| _| _| _| _| _| _| _| _|_|
6 # _| _| _| _| _| _| _| _| _| _| _| _| _| _| _|_
7 # _| _| _| _|_|_| _|_|_| _|_|_| _| _|_| _|_| _| _|_|_|
8 #
9 #================================================================================================
10 #
11 #
12
13
14 TEMPLATE = subdirs
15 CONFIG += ordered release
16
17 SUBDIRS += \
18 vhdlparser \
19 tests/basic_VHDL_parser
20
21
22
23 OTHER_FILES += \
24 README.md \
25 COPYING
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1 #==================================================
2 #
3 # _|_| _|_|_| _| _| _|
4 # _| _| _| _| _|_|_|
5 # _| _|_| _| _| _| _| _|
6 # _| _| _| _| _| _| _|
7 # _|_| _| _|_|_| _| _| _|_|_|
8 #
9 #==================================================
10 #
11 #
12
13 message(" Check if Flex is installed ")
14 !system( "flex -V > temp" ){
15 error("flex isn't installed, you should install it first or check that it is in the PATH")
16 }
17 system( $$QMAKE_DEL_FILE $$PWD"/temp" )
18
19 message(" Success Flex is installed ")
20
21 FLEXSOURCES += \
22 $${PWD}/vhdl.l
23
24 vhdlHeaders.path = $$[QT_INSTALL_HEADERS]/VDHL_Tools/vhdl
25 vhdlHeaders.files = \
26 $${DESTDIR}/../vhdlparser/vhdl/lispLike.hpp \
27 $${DESTDIR}/../vhdlparser/vhdl/location.hh \
28 $${DESTDIR}/../vhdlparser/vhdl/position.hh \
29 $${DESTDIR}/../vhdlparser/vhdl/stack.hh
30
31
32 INSTALLS += vhdlHeaders
33
34 flex.name = Flex
35 flex.input = FLEXSOURCES
36 flex.output = ${QMAKE_FILE_BASE}"/lex."${QMAKE_FILE_BASE}.cpp
37 flex.commands = flex -i -o${QMAKE_FILE_OUT} ${QMAKE_FILE_IN}
38 flex.variable_out = SOURCES
39 QMAKE_EXTRA_COMPILERS += flex
40
41
42 OTHER_FILES += \
43 $$FLEXSOURCES
44
45
46
47
48
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1 %{
2 /* C++ string header, for string ops below */
3 #include <string>
4 #include <QString>
5 /* Implementation of yyFlexScanner */
6 #include "vhdl_scanner.h"
7 #include <QDebug>
8 /* define to keep from re-typing the same code over and over */
9 #define STOKEN( x ) ( new QString( x ) )
10
11 /* define yyterminate as this instead of NULL */
12 //#define yyterminate() return( token::END )
13
14 /* msvc2010 requires that we exclude this header file. */
15 #define YY_NO_UNISTD_H
16 %}
17
18 %option debug
19 %option nodefault
20 %option yyclass="vhdl_Scanner"
21 %option case-insensitive yylineno
22 %option noyywrap
23 %option c++
24
25
26 %%
27
28 /*-----------------------------------------------------------*/
29 /*Separators*/
30 [ \t\n]+ { } //skip new lines, blanc spaces and tabulations
31 /*-----------------------------------------------------------*/
32
33
34 /*comment*/
35 --.* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::comment));}
36 /*-----------------------------------------------------------*/
37
38 /*Reserved words*/
39
40 abs |
41 access |
42 after |
43 alias |
44 all |
45 and |
46 architecture |
47 array |
48 assert |
49 attribute |
50 begin |
51 block |
52 body |
53 buffer |
54 bus |
55 case |
56 component |
57 configuration |
58 constant |
59 disconnect |
60 downto |
61 else |
62 elsif |
63 end |
64 entity |
65 exit |
66 file |
67 for |
68 function |
69 generate |
70 generic |
71 group |
72 guarded |
73 if |
74 impure |
75 in |
76 inertial |
77 inout |
78 is |
79 label |
80 library |
81 linkage |
82 literal |
83 loop |
84 map |
85 mod |
86 nand |
87 new |
88 next |
89 nor |
90 not |
91 null |
92 of |
93 on |
94 open |
95 or |
96 others |
97 out |
98 package |
99 port |
100 postponed |
101 procedure |
102 process |
103 pure |
104 range |
105 record |
106 register |
107 reject |
108 rem |
109 report |
110 return |
111 rol |
112 ror |
113 select |
114 severity |
115 shared |
116 signal |
117 sla |
118 sll |
119 sra |
120 srl |
121 subtype |
122 then |
123 to |
124 transport |
125 type |
126 unaffected |
127 units |
128 until |
129 use |
130 variable |
131 wait |
132 when |
133 while |
134 with |
135 xnor |
136 xor |
137 (true|false) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::keyword));}
138
139
140 /* delimiter*/
141 \. | \| | \[ | \] |
142 \:= | \>\= |
143 \<\= |
144 \/\= |
145 \= |
146 \> |
147 \< |
148 \& |
149 \‘ |
150 \=\> |
151 \: |
152 \<\> |
153 \; |
154 \, |
155 \( |
156 \) |
157 \* |
158 \+ |
159 \- |
160 \/ |
161 \*\* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::separator)); }
162
163
164 /*-----------------------------------------------------------*/
165
166 /*identifier (may be a reserved word)*/
167 [a-z][a-z0-9\_]+[a-z] |
168 [a-z]+ |
169 \\.*\\ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::identifier));}
170
171 /*-----------------------------------------------------------*/
172
173 /*abstract literal (integer or floating point type)*/
174 /*Numerical literals*/
175 (\+|\-)?([0-9\_]+)|(\+|\-)?([0-9\_]+E[0-9\_]+)|((2|3|4|5|6|7|8|9|10|11|12|13|14|15|16)\#[0-9\_]\#) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
176
177 (\+|\-)?[0-9\_]+\.[0-9\_]+|[0-9\_]+\.[0-9\_]+E[0-9\_]+ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
178
179 \'(0|1)\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
180
181 \'.\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
182
183
184 (\+|\-)?([0-9\_]+)(fs|ps|ns|us|ms|sec|min|hr) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
185
186 /*Bit string literals*/
187 \"[0-1\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
188
189 /*String literals*/
190 \".*\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
191
192 x\"[0-9A-F\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
193
194 o\"[0-7\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
195
196 /*The NULL literal*/
197
198 \[NULL\] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));}
199
200 /*-----------------------------------------------------------*/
201
202 /*character literal (a graphical character surrounded by ‘, e.g.: ‘H’)*/
203 /*-----------------------------------------------------------*/
204
205 /*string literal (a sequence of graphical characters surrounded by ”, e.g.: ”HAR-DI”)*/
206 /*-----------------------------------------------------------*/
207
208 /* bit string literal (a sequence of extended digits * surrounded by ”, e.g.: ”011”)*/
209 /*-----------------------------------------------------------*/
210
211
212
213
214
215 %%
216
217
218
219
220
221
222
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@@ -0,0 +1,46
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the VHDL Tools Software
3 -- Copyright (C) 2014, Plasma Physics Laboratory - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ----------------------------------------------------------------------------*/
22 #include "vhdl_scanner.h"
23 #include <QDebug>
24
25 VHDL_Tools::vhdl_Scanner::vhdl_Scanner(std::istream *in)
26 : yyFlexLexer(in)
27 {
28 this->rootNode = new VHDL_Tools::VHDL_AST_Node("rootNode",VHDL_Tools::rootNode);
29 }
30
31 int VHDL_Tools::vhdl_Scanner::scan()
32 {
33 return( yylex() );
34 }
35
36 void VHDL_Tools::vhdl_Scanner::stackData(QString data)
37 {
38 qDebug()<<data;
39 }
40
41 void VHDL_Tools::vhdl_Scanner::appendNode(VHDL_Tools::VHDL_AST_Node *node)
42 {
43 this->rootNode->childs.append(node);
44 }
45
46
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@@ -0,0 +1,64
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the VHDL Tools Software
3 -- Copyright (C) 2014, Plasma Physics Laboratory - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ----------------------------------------------------------------------------*/
22 #ifndef vhdl_SCANNER_H
23 #define vhdl_SCANNER_H
24 #if ! defined(yyFlexLexerOnce)
25 #include <FlexLexer.h>
26 #endif
27 #include <iostream>
28 #include <cstdlib>
29 #include <fstream>
30 #include <QString>
31 #include <QList>
32
33 #undef YY_DECL
34 #define YY_DECL int VHDL_Tools::vhdl_Scanner::yylex()
35
36 namespace VHDL_Tools{
37
38 enum VHDL_AST_Node_type {separator,keyword,identifier,literal,rootNode,comment};
39 class VHDL_AST_Node
40 {
41 public:
42 VHDL_AST_Node(const QString& value,VHDL_Tools::VHDL_AST_Node_type type):value(value),type(type) {}
43 QString value;
44 VHDL_Tools::VHDL_AST_Node_type type;
45 VHDL_Tools::VHDL_AST_Node* parent;
46 QList<VHDL_Tools::VHDL_AST_Node*> childs;
47 };
48
49 class vhdl_Scanner : public yyFlexLexer
50 {
51 public:
52 vhdl_Scanner(std::istream *in);
53 int scan();
54
55 private:
56 /* hide this one from public view */
57 int yylex();
58 void stackData(QString data);
59 void appendNode(VHDL_Tools::VHDL_AST_Node* node);
60 VHDL_Tools::VHDL_AST_Node* rootNode;
61 };
62 }
63
64 #endif // vhdl_SCANNER_H
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1 #include "vhdl_file.h"
2
3
4 VHDL_Tools::VHDL_File::VHDL_File()
5 {
6 this->scanner = NULL;
7 }
8
9
10 bool VHDL_Tools::VHDL_File::parseFile(const QString &file)
11 {
12 std::ifstream in_file( file.toStdString().c_str() );
13 if( ! in_file.good() ) return false;
14 if(scanner)
15 delete(scanner);
16 try
17 {
18 scanner = new VHDL_Tools::vhdl_Scanner( &in_file );
19 }
20 catch( std::bad_alloc &ba )
21 {
22 std::cerr << "Failed to allocate scanner: (" <<
23 ba.what() << ")\n";
24 return false;
25 }
26 while (scanner->scan()!=0);
27 //parse(file.toStdString().c_str());
28
29 return false;
30 }
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1 #ifndef VHDL_FILE_H
2 #define VHDL_FILE_H
3
4 #include "vhdlparser_global.h"
5 #include "scanner/vhdl_scanner.h"
6 #include <QString>
7 namespace VHDL_Tools {
8 class VHDL_File
9 {
10
11 public:
12 VHDL_File();
13 bool parseFile(const QString& file);
14
15 private:
16 VHDL_Tools::vhdl_Scanner *scanner;
17 };
18
19 }
20 #endif // VHDL_FILE_H
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@@ -0,0 +1,36
1 #-------------------------------------------------
2 #
3 # Project created by QtCreator 2014-07-20T21:32:03
4 #
5 #-------------------------------------------------
6
7 QT -= gui
8
9
10 include ( ./scanner/Flex_Bison_FIles/Flex_Bison_FIles.pri )
11
12 TARGET = vhdlparser
13 TEMPLATE = lib
14
15 LIBS += -lfl
16
17 DEFINES += LIBVHDLPARSER_LIBRARY
18 DESTDIR = ../bin
19
20 INCLUDEPATH += ./scanner
21 INCLUDEPATH += \
22 ../vhdlparser
23
24
25 SOURCES += vhdl_file.cpp \
26 scanner/vhdl_scanner.cpp
27
28 HEADERS += vhdl_file.h\
29 libvhdlparser_global.h \
30 scanner/vhdl_scanner.h
31
32 unix {
33 target.path = /usr/lib
34 INSTALLS += target
35 }
36
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@@ -0,0 +1,12
1 #ifndef LIBVHDLPARSER_GLOBAL_H
2 #define LIBVHDLPARSER_GLOBAL_H
3
4 #include <QtCore/qglobal.h>
5
6 #if defined(LIBVHDLPARSER_LIBRARY)
7 # define LIBVHDLPARSERSHARED_EXPORT Q_DECL_EXPORT
8 #else
9 # define LIBVHDLPARSERSHARED_EXPORT Q_DECL_IMPORT
10 #endif
11
12 #endif // LIBVHDLPARSER_GLOBAL_H
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