vhdl.l
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r0 | %{ | |||
/* C++ string header, for string ops below */ | ||||
#include <string> | ||||
#include <QString> | ||||
/* Implementation of yyFlexScanner */ | ||||
#include "vhdl_scanner.h" | ||||
#include <QDebug> | ||||
/* define to keep from re-typing the same code over and over */ | ||||
#define STOKEN( x ) ( new QString( x ) ) | ||||
/* define yyterminate as this instead of NULL */ | ||||
//#define yyterminate() return( token::END ) | ||||
/* msvc2010 requires that we exclude this header file. */ | ||||
#define YY_NO_UNISTD_H | ||||
%} | ||||
%option debug | ||||
%option nodefault | ||||
%option yyclass="vhdl_Scanner" | ||||
%option case-insensitive yylineno | ||||
%option noyywrap | ||||
%option c++ | ||||
%% | ||||
/*-----------------------------------------------------------*/ | ||||
/*Separators*/ | ||||
[ \t\n]+ { } //skip new lines, blanc spaces and tabulations | ||||
/*-----------------------------------------------------------*/ | ||||
/*comment*/ | ||||
--.* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::comment));} | ||||
/*-----------------------------------------------------------*/ | ||||
/*Reserved words*/ | ||||
abs | | ||||
access | | ||||
after | | ||||
alias | | ||||
all | | ||||
and | | ||||
architecture | | ||||
array | | ||||
assert | | ||||
attribute | | ||||
begin | | ||||
block | | ||||
body | | ||||
buffer | | ||||
bus | | ||||
case | | ||||
component | | ||||
configuration | | ||||
constant | | ||||
disconnect | | ||||
downto | | ||||
else | | ||||
elsif | | ||||
end | | ||||
entity | | ||||
exit | | ||||
file | | ||||
for | | ||||
function | | ||||
generate | | ||||
generic | | ||||
group | | ||||
guarded | | ||||
if | | ||||
impure | | ||||
in | | ||||
inertial | | ||||
inout | | ||||
is | | ||||
label | | ||||
library | | ||||
linkage | | ||||
literal | | ||||
loop | | ||||
map | | ||||
mod | | ||||
nand | | ||||
new | | ||||
next | | ||||
nor | | ||||
not | | ||||
null | | ||||
of | | ||||
on | | ||||
open | | ||||
or | | ||||
others | | ||||
out | | ||||
package | | ||||
port | | ||||
postponed | | ||||
procedure | | ||||
process | | ||||
pure | | ||||
range | | ||||
record | | ||||
register | | ||||
reject | | ||||
rem | | ||||
report | | ||||
return | | ||||
rol | | ||||
ror | | ||||
select | | ||||
severity | | ||||
shared | | ||||
signal | | ||||
sla | | ||||
sll | | ||||
sra | | ||||
srl | | ||||
subtype | | ||||
then | | ||||
to | | ||||
transport | | ||||
type | | ||||
unaffected | | ||||
units | | ||||
until | | ||||
use | | ||||
variable | | ||||
wait | | ||||
when | | ||||
while | | ||||
with | | ||||
xnor | | ||||
xor | | ||||
(true|false) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::keyword));} | ||||
/* delimiter*/ | ||||
\. | \| | \[ | \] | | ||||
\:= | \>\= | | ||||
\<\= | | ||||
\/\= | | ||||
\= | | ||||
\> | | ||||
\< | | ||||
\& | | ||||
\‘ | | ||||
\=\> | | ||||
\: | | ||||
\<\> | | ||||
\; | | ||||
\, | | ||||
\( | | ||||
\) | | ||||
\* | | ||||
\+ | | ||||
\- | | ||||
\/ | | ||||
\*\* {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::separator)); } | ||||
/*-----------------------------------------------------------*/ | ||||
/*identifier (may be a reserved word)*/ | ||||
[a-z][a-z0-9\_]+[a-z] | | ||||
[a-z]+ | | ||||
\\.*\\ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::identifier));} | ||||
/*-----------------------------------------------------------*/ | ||||
/*abstract literal (integer or floating point type)*/ | ||||
/*Numerical literals*/ | ||||
(\+|\-)?([0-9\_]+)|(\+|\-)?([0-9\_]+E[0-9\_]+)|((2|3|4|5|6|7|8|9|10|11|12|13|14|15|16)\#[0-9\_]\#) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
(\+|\-)?[0-9\_]+\.[0-9\_]+|[0-9\_]+\.[0-9\_]+E[0-9\_]+ {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
\'(0|1)\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
\'.\' {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
(\+|\-)?([0-9\_]+)(fs|ps|ns|us|ms|sec|min|hr) {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
/*Bit string literals*/ | ||||
\"[0-1\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
/*String literals*/ | ||||
\".*\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
x\"[0-9A-F\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
o\"[0-7\_]+\" {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
/*The NULL literal*/ | ||||
\[NULL\] {this->appendNode(new VHDL_Tools::VHDL_AST_Node(YYText(),VHDL_Tools::literal));} | ||||
/*-----------------------------------------------------------*/ | ||||
/*character literal (a graphical character surrounded by ‘, e.g.: ‘H’)*/ | ||||
/*-----------------------------------------------------------*/ | ||||
/*string literal (a sequence of graphical characters surrounded by ”, e.g.: ”HAR-DI”)*/ | ||||
/*-----------------------------------------------------------*/ | ||||
/* bit string literal (a sequence of extended digits * surrounded by ”, e.g.: ”011”)*/ | ||||
/*-----------------------------------------------------------*/ | ||||
%% | ||||