		Commit message	Age	Author	Refs
	`r598:a4da461dd67d`	LFR-EQM 2.1.81 > all is ok, the ADC data are sampled at 500M.sample.Hz	Mon, 18 May 2015 12:42:37	pellion	simu_with_Leon3	0
	`r597:ec6fbc748101`	save	Mon, 18 May 2015 12:09:03	pellion	simu_with_Leon3	0
	`r596:04687799528c`	ok	Fri, 15 May 2015 07:59:58	pellion	simu_with_Leon3	0
	`r595:eb603d70d051`	register the data outputed by ADC_driver	Tue, 05 May 2015 09:12:31	pellion	simu_with_Leon3	0
	`r594:a9702b7364d2`	temp : update ADC driver - conversion part clocked by clk_49 (49.152 MHz) - cnv_clk = clk_49.152/100 with duty cycle of 50% - 3 period for each Ren, - Data sampling during the 2nd cycle of Ren, - each 2 data input, 1 data output (@)	Mon, 04 May 2015 14:31:01	pellion	simu_with_Leon3	0
	`r593:173a643f1c9c`	temp	Thu, 30 Apr 2015 11:58:47	pellion	simu_with_Leon3	0
	`r592:7b23905bc9f6`	temp	Thu, 30 Apr 2015 09:47:15	pellion	JC	0
	`r591:e0250657227b`	ADD SDC constraint	Fri, 24 Apr 2015 14:16:40	pellion	JC	0
	`r590:f6390d699855`	merge simu_with_leon3 (add lpp_dma_SEND16B_FIFO2DMA)	Fri, 24 Apr 2015 10:31:42	pellion	JC	0
	`r589:ebd290519818`	update ok ??	Thu, 23 Apr 2015 17:11:39	pellion	simu_with_Leon3	0

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