@@ -207,8 +207,10 enum apid_destid{ | |||||
207 | #define SID_K_DUMP 11 |
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207 | #define SID_K_DUMP 11 | |
208 |
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208 | |||
209 | // HEADER_LENGTH |
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209 | // HEADER_LENGTH | |
210 | #define TM_HEADER_LEN 16 |
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210 | //#define TM_HEADER_LEN 16 | |
211 |
#define HEADER_LENGTH_TM_LFR_SCIENCE_ |
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211 | #define HEADER_LENGTH_TM_LFR_SCIENCE_CWF 32 | |
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212 | #define HEADER_LENGTH_TM_LFR_SCIENCE_SWF 34 | |||
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213 | #define HEADER_LENGTH_TM_LFR_SCIENCE_ASM 34 | |||
212 | // PACKET_LENGTH |
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214 | // PACKET_LENGTH | |
213 | #define PACKET_LENGTH_TC_EXE_SUCCESS (20 - CCSDS_TC_TM_PACKET_OFFSET) |
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215 | #define PACKET_LENGTH_TC_EXE_SUCCESS (20 - CCSDS_TC_TM_PACKET_OFFSET) | |
214 | #define PACKET_LENGTH_TC_EXE_INCONSISTENT (26 - CCSDS_TC_TM_PACKET_OFFSET) |
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216 | #define PACKET_LENGTH_TC_EXE_INCONSISTENT (26 - CCSDS_TC_TM_PACKET_OFFSET) | |
@@ -220,8 +222,10 enum apid_destid{ | |||||
220 | #define PACKET_LENGTH_PARAMETER_DUMP (84 - CCSDS_TC_TM_PACKET_OFFSET) |
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222 | #define PACKET_LENGTH_PARAMETER_DUMP (84 - CCSDS_TC_TM_PACKET_OFFSET) | |
221 | #define PACKET_LENGTH_K_DUMP (3920 - CCSDS_TC_TM_PACKET_OFFSET) |
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223 | #define PACKET_LENGTH_K_DUMP (3920 - CCSDS_TC_TM_PACKET_OFFSET) | |
222 | // SCIENCE ASM |
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224 | // SCIENCE ASM | |
223 |
#define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0 |
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225 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_1 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 32 bins (32 + 32 + 24 ), 3 packets | |
224 |
#define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F |
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226 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0_2 (2430 - CCSDS_TC_TM_PACKET_OFFSET) // 24 * 25 * 4 + 30 => 24 bins (32 + 32 + 24 ), 3 packets | |
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227 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1_1 (3630 - CCSDS_TC_TM_PACKET_OFFSET) // 36 * 25 * 4 + 30 => 36 bins (36 + 36 + 32 ), 3 packets | |||
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228 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1_2 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 32 bins (36 + 36 + 32 ), 3 packets | |||
225 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F2 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 96 bins (32 + 32 + 32 ), 3 packets |
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229 | #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F2 (3230 - CCSDS_TC_TM_PACKET_OFFSET) // 32 * 25 * 4 + 30 => 96 bins (32 + 32 + 32 ), 3 packets | |
226 | // SCIENCE NORM |
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230 | // SCIENCE NORM | |
227 | #define PACKET_LENGTH_TM_LFR_SCIENCE_NORM_BP1_F0 (150 - CCSDS_TC_TM_PACKET_OFFSET) // 11 * 11 + 29 (1 spare byte in the header) |
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231 | #define PACKET_LENGTH_TM_LFR_SCIENCE_NORM_BP1_F0 (150 - CCSDS_TC_TM_PACKET_OFFSET) // 11 * 11 + 29 (1 spare byte in the header) |
@@ -224,7 +224,7 typedef struct ring_node | |||||
224 | #define MSG_QUEUE_COUNT_PRC0 10 |
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224 | #define MSG_QUEUE_COUNT_PRC0 10 | |
225 | #define MSG_QUEUE_COUNT_PRC1 10 |
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225 | #define MSG_QUEUE_COUNT_PRC1 10 | |
226 | #define MSG_QUEUE_COUNT_PRC2 5 |
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226 | #define MSG_QUEUE_COUNT_PRC2 5 | |
227 |
#define MSG_QUEUE_SIZE_SEND 81 |
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227 | #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1 | |
228 | #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options |
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228 | #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options | |
229 | #define MSG_QUEUE_SIZE_PRC0 28 // two pointers, one rtems_event + 4 integers |
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229 | #define MSG_QUEUE_SIZE_PRC0 28 // two pointers, one rtems_event + 4 integers | |
230 | #define MSG_QUEUE_SIZE_PRC1 28 // two pointers, one rtems_event + 4 integers |
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230 | #define MSG_QUEUE_SIZE_PRC1 28 // two pointers, one rtems_event + 4 integers |
@@ -24,20 +24,24 | |||||
24 | #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3 |
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24 | #define NB_RING_NODES_ASM_F2 3 // AT LEAST 3 | |
25 | // |
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25 | // | |
26 | #define NB_BINS_PER_ASM_F0 88 |
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26 | #define NB_BINS_PER_ASM_F0 88 | |
27 |
#define NB_BINS_PER_PKT_ASM_F0 |
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27 | #define NB_BINS_PER_PKT_ASM_F0_1 32 | |
28 | #define TOTAL_SIZE_ASM_F0_IN_BYTES 4400 // 25 * 88 * 2 |
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28 | #define NB_BINS_PER_PKT_ASM_F0_2 24 | |
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29 | #define DLEN_ASM_F0_PKT_1 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |||
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30 | #define DLEN_ASM_F0_PKT_2 2400 // 24 * 25 * 4, 25 components per matrix, 4 bytes per float | |||
29 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour |
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31 | #define ASM_F0_INDICE_START 16 // 17 - 1, (-1) due to the VHDL behaviour | |
30 | #define ASM_F0_INDICE_STOP 103 // 104 - 1, 2 packets of 44 bins |
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32 | #define ASM_F0_INDICE_STOP 103 // 104 - 1, 2 packets of 44 bins | |
31 | // |
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33 | // | |
32 | #define NB_BINS_PER_ASM_F1 104 |
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34 | #define NB_BINS_PER_ASM_F1 104 | |
33 |
#define NB_BINS_PER_PKT_ASM_F1 |
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35 | #define NB_BINS_PER_PKT_ASM_F1_1 36 | |
34 | #define TOTAL_SIZE_ASM_F1_IN_BYTES 5200 // 25 * 104 * 2 |
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36 | #define NB_BINS_PER_PKT_ASM_F1_2 32 | |
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37 | #define DLEN_ASM_F1_PKT_1 3600 // 36 * 25 * 4, 25 components per matrix, 4 bytes per float | |||
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38 | #define DLEN_ASM_F1_PKT_2 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |||
35 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour |
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39 | #define ASM_F1_INDICE_START 5 // 6 - 1, (-1) due to the VHDL behaviour | |
36 | #define ASM_F1_INDICE_STOP 108 // 109 - 1, 2 packets of 52 bins |
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40 | #define ASM_F1_INDICE_STOP 108 // 109 - 1, 2 packets of 52 bins | |
37 | // |
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41 | // | |
38 | #define NB_BINS_PER_ASM_F2 96 |
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42 | #define NB_BINS_PER_ASM_F2 96 | |
39 |
#define NB_BINS_PER_PKT_ASM_F2 |
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43 | #define NB_BINS_PER_PKT_ASM_F2 32 | |
40 | #define TOTAL_SIZE_ASM_F2_IN_BYTES 4800 // 25 * 96 * 2 |
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44 | #define DLEN_ASM_F2_PKT 3200 // 32 * 25 * 4, 25 components per matrix, 4 bytes per float | |
41 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour |
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45 | #define ASM_F2_INDICE_START 6 // 7 - 1, (-1) due to the VHDL behaviour | |
42 | #define ASM_F2_INDICE_STOP 101 // 102 - 1, 2 packets of 48 bins |
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46 | #define ASM_F2_INDICE_STOP 101 // 102 - 1, 2 packets of 48 bins | |
43 | // |
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47 | // |
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