##// END OF EJS Templates
HALF_ACQUISITION_DURATION_Fx added...
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1 #ifndef FSW_PARAMS_H_INCLUDED
1 #ifndef FSW_PARAMS_H_INCLUDED
2 #define FSW_PARAMS_H_INCLUDED
2 #define FSW_PARAMS_H_INCLUDED
3
3
4 #include "fsw_params_processing.h"
4 #include "fsw_params_processing.h"
5 #include "fsw_params_nb_bytes.h"
5 #include "fsw_params_nb_bytes.h"
6 #include "tm_byte_positions.h"
6 #include "tm_byte_positions.h"
7 #include "ccsds_types.h"
7 #include "ccsds_types.h"
8
8
9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
9 #define GRSPW_DEVICE_NAME "/dev/grspw0"
10 #define UART_DEVICE_NAME "/dev/console"
10 #define UART_DEVICE_NAME "/dev/console"
11
11
12 //*******
12 //*******
13 // MACROS
13 // MACROS
14 #ifdef PRINT_MESSAGES_ON_CONSOLE
14 #ifdef PRINT_MESSAGES_ON_CONSOLE
15 #define PRINTF(x) printf(x);
15 #define PRINTF(x) printf(x);
16 #define PRINTF1(x,y) printf(x,y);
16 #define PRINTF1(x,y) printf(x,y);
17 #define PRINTF2(x,y,z) printf(x,y,z);
17 #define PRINTF2(x,y,z) printf(x,y,z);
18 #else
18 #else
19 #define PRINTF(x) ;
19 #define PRINTF(x) ;
20 #define PRINTF1(x,y) ;
20 #define PRINTF1(x,y) ;
21 #define PRINTF2(x,y,z) ;
21 #define PRINTF2(x,y,z) ;
22 #endif
22 #endif
23
23
24 #ifdef BOOT_MESSAGES
24 #ifdef BOOT_MESSAGES
25 #define BOOT_PRINTF(x) printf(x);
25 #define BOOT_PRINTF(x) printf(x);
26 #define BOOT_PRINTF1(x,y) printf(x,y);
26 #define BOOT_PRINTF1(x,y) printf(x,y);
27 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
27 #define BOOT_PRINTF2(x,y,z) printf(x,y,z);
28 #else
28 #else
29 #define BOOT_PRINTF(x) ;
29 #define BOOT_PRINTF(x) ;
30 #define BOOT_PRINTF1(x,y) ;
30 #define BOOT_PRINTF1(x,y) ;
31 #define BOOT_PRINTF2(x,y,z) ;
31 #define BOOT_PRINTF2(x,y,z) ;
32 #endif
32 #endif
33
33
34 #ifdef DEBUG_MESSAGES
34 #ifdef DEBUG_MESSAGES
35 #define DEBUG_PRINTF(x) printf(x);
35 #define DEBUG_PRINTF(x) printf(x);
36 #define DEBUG_PRINTF1(x,y) printf(x,y);
36 #define DEBUG_PRINTF1(x,y) printf(x,y);
37 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
37 #define DEBUG_PRINTF2(x,y,z) printf(x,y,z);
38 #else
38 #else
39 #define DEBUG_PRINTF(x) ;
39 #define DEBUG_PRINTF(x) ;
40 #define DEBUG_PRINTF1(x,y) ;
40 #define DEBUG_PRINTF1(x,y) ;
41 #define DEBUG_PRINTF2(x,y,z) ;
41 #define DEBUG_PRINTF2(x,y,z) ;
42 #endif
42 #endif
43
43
44 #define CONST_65536 65536 // 2^16
44 #define CONST_65536 65536 // 2^16
45 #define CONST_2048 2048 // 2^11
45 #define CONST_2048 2048 // 2^11
46 #define CONST_512 512 // 2^9
46 #define CONST_512 512 // 2^9
47 #define CONST_256 256 // 2^8
47 #define CONST_256 256 // 2^8
48 #define CONST_128 128 // 2^7
48 #define CONST_128 128 // 2^7
49 #define UINT8_MAX 255
49 #define UINT8_MAX 255
50
50
51 #define FLOAT_MSBYTE 0
51 #define FLOAT_MSBYTE 0
52 #define FLOAT_LSBYTE 3
52 #define FLOAT_LSBYTE 3
53 #define BITS_PER_BYTE 8
53 #define BITS_PER_BYTE 8
54 #define INIT_FLOAT 0.
54 #define INIT_FLOAT 0.
55 #define INIT_CHAR 0x00
55 #define INIT_CHAR 0x00
56 #define INIT_INT 0
56 #define INIT_INT 0
57 #define INT8_ALL_F 0xff
57 #define INT8_ALL_F 0xff
58 #define INT16_ALL_F 0xffff
58 #define INT16_ALL_F 0xffff
59 #define INT32_ALL_F 0xffffffff
59 #define INT32_ALL_F 0xffffffff
60 #define INT32_ALL_0 0x00000000
60 #define INT32_ALL_0 0x00000000
61 #define SHIFT_1_BYTE 8
61 #define SHIFT_1_BYTE 8
62 #define SHIFT_2_BYTES 16
62 #define SHIFT_2_BYTES 16
63 #define SHIFT_3_BYTES 24
63 #define SHIFT_3_BYTES 24
64 #define SHIFT_4_BYTES 32
64 #define SHIFT_4_BYTES 32
65 #define SHIFT_5_BYTES 40
65 #define SHIFT_5_BYTES 40
66 #define SHIFT_2_BITS 2
66 #define SHIFT_2_BITS 2
67 #define SHIFT_3_BITS 3
67 #define SHIFT_3_BITS 3
68 #define SHIFT_4_BITS 4
68 #define SHIFT_4_BITS 4
69 #define SHIFT_5_BITS 5
69 #define SHIFT_5_BITS 5
70 #define SHIFT_6_BITS 6
70 #define SHIFT_6_BITS 6
71 #define SHIFT_7_BITS 7
71 #define SHIFT_7_BITS 7
72 #define BYTE_0 0
72 #define BYTE_0 0
73 #define BYTE_1 1
73 #define BYTE_1 1
74 #define BYTE_2 2
74 #define BYTE_2 2
75 #define BYTE_3 3
75 #define BYTE_3 3
76 #define BYTE_4 4
76 #define BYTE_4 4
77 #define BYTE_5 5
77 #define BYTE_5 5
78 #define BYTE_6 6
78 #define BYTE_6 6
79 #define BYTE_7 7
79 #define BYTE_7 7
80 #define BYTE0_MASK 0xff00
80 #define BYTE0_MASK 0xff00
81 #define BYTE1_MASK 0x00ff
81 #define BYTE1_MASK 0x00ff
82
82
83 enum lfr_transition_type_t{
83 enum lfr_transition_type_t{
84 TRANSITION_NOT_SPECIFIC,
84 TRANSITION_NOT_SPECIFIC,
85 TRANSITION_NORM_TO_S1,
85 TRANSITION_NORM_TO_S1,
86 TRANSITION_NORM_TO_S2,
86 TRANSITION_NORM_TO_S2,
87 TRANSITION_S1_TO_NORM,
87 TRANSITION_S1_TO_NORM,
88 TRANSITION_S2_TO_NORM,
88 TRANSITION_S2_TO_NORM,
89 TRANSITION_S1_TO_S2,
89 TRANSITION_S1_TO_S2,
90 TRANSITION_S2_TO_S1
90 TRANSITION_S2_TO_S1
91 };
91 };
92
92
93 typedef struct ring_node
93 typedef struct ring_node
94 {
94 {
95 struct ring_node *previous;
95 struct ring_node *previous;
96 struct ring_node *next;
96 struct ring_node *next;
97 unsigned int sid;
97 unsigned int sid;
98 unsigned int coarseTime;
98 unsigned int coarseTime;
99 unsigned int fineTime;
99 unsigned int fineTime;
100 int buffer_address;
100 int buffer_address;
101 unsigned int status;
101 unsigned int status;
102 } ring_node;
102 } ring_node;
103
103
104 //************************
104 //************************
105 // flight software version
105 // flight software version
106 // this parameters is handled by the Qt project options
106 // this parameters is handled by the Qt project options
107
107
108 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
108 #define NB_PACKETS_PER_GROUP_OF_CWF 8 // 8 packets containing 336 blk
109 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
109 #define NB_PACKETS_PER_GROUP_OF_CWF_LIGHT 4 // 4 packets containing 672 blk
110 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
110 #define NB_SAMPLES_PER_SNAPSHOT 2688 // 336 * 8 = 672 * 4 = 2688
111 #define TIME_OFFSET 2
111 #define TIME_OFFSET 2
112 #define TIME_OFFSET_IN_BYTES 8
112 #define TIME_OFFSET_IN_BYTES 8
113 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
113 //#define WAVEFORM_EXTENDED_HEADER_OFFSET 22
114 #define NB_BYTES_SWF_BLK (2 * 6)
114 #define NB_BYTES_SWF_BLK (2 * 6)
115 #define NB_WORDS_SWF_BLK 3
115 #define NB_WORDS_SWF_BLK 3
116 #define NB_BYTES_CWF3_LIGHT_BLK 6
116 #define NB_BYTES_CWF3_LIGHT_BLK 6
117 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
117 //#define WFRM_INDEX_OF_LAST_PACKET 6 // waveforms are transmitted in groups of 2048 blocks, 6 packets of 340 and 1 of 8
118 #define NB_RING_NODES_F0 3 // AT LEAST 3
118 #define NB_RING_NODES_F0 3 // AT LEAST 3
119 #define NB_RING_NODES_F1 5 // AT LEAST 3
119 #define NB_RING_NODES_F1 5 // AT LEAST 3
120 #define NB_RING_NODES_F2 5 // AT LEAST 3
120 #define NB_RING_NODES_F2 5 // AT LEAST 3
121 #define NB_RING_NODES_F3 3 // AT LEAST 3
121 #define NB_RING_NODES_F3 3 // AT LEAST 3
122
122
123 //**********
123 //**********
124 // LFR MODES
124 // LFR MODES
125 #define LFR_MODE_STANDBY 0
125 #define LFR_MODE_STANDBY 0
126 #define LFR_MODE_NORMAL 1
126 #define LFR_MODE_NORMAL 1
127 #define LFR_MODE_BURST 2
127 #define LFR_MODE_BURST 2
128 #define LFR_MODE_SBM1 3
128 #define LFR_MODE_SBM1 3
129 #define LFR_MODE_SBM2 4
129 #define LFR_MODE_SBM2 4
130
130
131 #define TDS_MODE_LFM 5
131 #define TDS_MODE_LFM 5
132 #define TDS_MODE_STANDBY 0
132 #define TDS_MODE_STANDBY 0
133 #define TDS_MODE_NORMAL 1
133 #define TDS_MODE_NORMAL 1
134 #define TDS_MODE_BURST 2
134 #define TDS_MODE_BURST 2
135 #define TDS_MODE_SBM1 3
135 #define TDS_MODE_SBM1 3
136 #define TDS_MODE_SBM2 4
136 #define TDS_MODE_SBM2 4
137
137
138 #define THR_MODE_STANDBY 0
138 #define THR_MODE_STANDBY 0
139 #define THR_MODE_NORMAL 1
139 #define THR_MODE_NORMAL 1
140 #define THR_MODE_BURST 2
140 #define THR_MODE_BURST 2
141
141
142 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
142 #define RTEMS_EVENT_MODE_STANDBY RTEMS_EVENT_0
143 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
143 #define RTEMS_EVENT_MODE_NORMAL RTEMS_EVENT_1
144 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
144 #define RTEMS_EVENT_MODE_BURST RTEMS_EVENT_2
145 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
145 #define RTEMS_EVENT_MODE_SBM1 RTEMS_EVENT_3
146 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
146 #define RTEMS_EVENT_MODE_SBM2 RTEMS_EVENT_4
147 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
147 #define RTEMS_EVENT_MODE_NORM_S1_S2 RTEMS_EVENT_5
148 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
148 #define RTEMS_EVENT_NORM_BP1_F0 RTEMS_EVENT_6
149 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
149 #define RTEMS_EVENT_NORM_BP2_F0 RTEMS_EVENT_7
150 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
150 #define RTEMS_EVENT_NORM_ASM_F0 RTEMS_EVENT_8 // ASM only in NORM mode
151 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
151 #define RTEMS_EVENT_NORM_BP1_F1 RTEMS_EVENT_9
152 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
152 #define RTEMS_EVENT_NORM_BP2_F1 RTEMS_EVENT_10
153 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
153 #define RTEMS_EVENT_NORM_ASM_F1 RTEMS_EVENT_11 // ASM only in NORM mode
154 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
154 #define RTEMS_EVENT_NORM_BP1_F2 RTEMS_EVENT_12
155 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
155 #define RTEMS_EVENT_NORM_BP2_F2 RTEMS_EVENT_13
156 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
156 #define RTEMS_EVENT_NORM_ASM_F2 RTEMS_EVENT_14 // ASM only in NORM mode
157 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
157 #define RTEMS_EVENT_SBM_BP1_F0 RTEMS_EVENT_15
158 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
158 #define RTEMS_EVENT_SBM_BP2_F0 RTEMS_EVENT_16
159 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
159 #define RTEMS_EVENT_SBM_BP1_F1 RTEMS_EVENT_17
160 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
160 #define RTEMS_EVENT_SBM_BP2_F1 RTEMS_EVENT_18
161 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
161 #define RTEMS_EVENT_BURST_BP1_F0 RTEMS_EVENT_19
162 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
162 #define RTEMS_EVENT_BURST_BP2_F0 RTEMS_EVENT_20
163 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
163 #define RTEMS_EVENT_BURST_BP1_F1 RTEMS_EVENT_21
164 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
164 #define RTEMS_EVENT_BURST_BP2_F1 RTEMS_EVENT_22
165 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
165 #define RTEMS_EVENT_SWF_RESYNCH RTEMS_EVENT_23
166
166
167 //********************************************
167 //********************************************
168 //********************************************
168 //********************************************
169 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
169 // LFR PARAMETERS: DEFAULT, MIN AND MAX VALUES
170
170
171 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
171 #define DEFAULT_LAST_VALID_TRANSITION_DATE 0xffffffff
172
172
173 // COMMON
173 // COMMON
174 #define DEFAULT_SY_LFR_COMMON0 0x00
174 #define DEFAULT_SY_LFR_COMMON0 0x00
175 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
175 #define DEFAULT_SY_LFR_COMMON1 0x20 // default value bw sp0 sp1 r0 r1 r2 = 1 0 0 0 0 0
176
176
177 // NORM
177 // NORM
178 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
178 #define DFLT_SY_LFR_N_SWF_L 2048 // nb sample
179 #define DFLT_SY_LFR_N_SWF_P 300 // sec
179 #define DFLT_SY_LFR_N_SWF_P 300 // sec
180 #define MIN_SY_LFR_N_SWF_P 22 // sec
180 #define MIN_SY_LFR_N_SWF_P 22 // sec
181 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
181 #define DFLT_SY_LFR_N_ASM_P 3600 // sec
182 #define DFLT_SY_LFR_N_BP_P0 4 // sec
182 #define DFLT_SY_LFR_N_BP_P0 4 // sec
183 #define DFLT_SY_LFR_N_BP_P1 20 // sec
183 #define DFLT_SY_LFR_N_BP_P1 20 // sec
184 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
184 #define DFLT_SY_LFR_N_CWF_LONG_F3 0 // 0 => production of light continuous waveforms at f3
185 #define MIN_DELTA_SNAPSHOT 16 // sec
185 #define MIN_DELTA_SNAPSHOT 16 // sec
186
186
187 // BURST
187 // BURST
188 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
188 #define DEFAULT_SY_LFR_B_BP_P0 1 // sec
189 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
189 #define DEFAULT_SY_LFR_B_BP_P1 5 // sec
190
190
191 // SBM1
191 // SBM1
192 #define S1_BP_P0_SCALE 0.25
192 #define S1_BP_P0_SCALE 0.25
193 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
193 #define DEFAULT_SY_LFR_S1_BP_P0 1 // 0.25 sec
194 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
194 #define DEFAULT_SY_LFR_S1_BP_P1 1 // sec
195
195
196 // SBM2
196 // SBM2
197 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
197 #define DEFAULT_SY_LFR_S2_BP_P0 1 // sec
198 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
198 #define DEFAULT_SY_LFR_S2_BP_P1 5 // sec
199
199
200 // ADDITIONAL PARAMETERS
200 // ADDITIONAL PARAMETERS
201 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
201 #define TIME_BETWEEN_TWO_SWF_PACKETS 30 // nb x 10 ms => 300 ms
202 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
202 #define TIME_BETWEEN_TWO_CWF3_PACKETS 1000 // nb x 10 ms => 10 s
203
203
204 // STATUS WORD
204 // STATUS WORD
205 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
205 #define DEFAULT_STATUS_WORD_BYTE0 0x0d // [0000] [1] [101] mode 4 bits / SPW enabled 1 bit / state is run 3 bits
206
206
207 #define DEFAULT_STATUS_WORD_BYTE1 0x00
207 #define DEFAULT_STATUS_WORD_BYTE1 0x00
208 // TC_LFR_LOAD_FILTER_PAR
208 // TC_LFR_LOAD_FILTER_PAR
209 #define MIN_PAS_FILTER_MODULUS 4
209 #define MIN_PAS_FILTER_MODULUS 4
210 #define MAX_PAS_FILTER_MODULUS 8
210 #define MAX_PAS_FILTER_MODULUS 8
211 #define MIN_PAS_FILTER_TBAD 0.0
211 #define MIN_PAS_FILTER_TBAD 0.0
212 #define MAX_PAS_FILTER_TBAD 4.0
212 #define MAX_PAS_FILTER_TBAD 4.0
213 #define MIN_PAS_FILTER_OFFSET 0
213 #define MIN_PAS_FILTER_OFFSET 0
214 #define MAX_PAS_FILTER_OFFSET 7
214 #define MAX_PAS_FILTER_OFFSET 7
215 #define MIN_PAS_FILTER_SHIFT 0.0
215 #define MIN_PAS_FILTER_SHIFT 0.0
216 #define MAX_PAS_FILTER_SHIFT 1.0
216 #define MAX_PAS_FILTER_SHIFT 1.0
217 #define MIN_SY_LFR_SC_RW_DELTA_F 0
217 #define MIN_SY_LFR_SC_RW_DELTA_F 0
218 #define MIN_SY_LFR_RW_K 0
218 #define MIN_SY_LFR_RW_K 0
219 #define MIN_SY_LFR_RW_F 0
219 #define MIN_SY_LFR_RW_F 0
220 //
220 //
221 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
221 #define SY_LFR_DPU_CONNECT_TIMEOUT 100 // 100 * 10 ms = 1 s
222 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
222 #define SY_LFR_DPU_CONNECT_ATTEMPT 3
223 //****************************
223 //****************************
224
224
225 //*****************************
225 //*****************************
226 // APB REGISTERS BASE ADDRESSES
226 // APB REGISTERS BASE ADDRESSES
227 #define REGS_ADDR_APBUART 0x80000100
227 #define REGS_ADDR_APBUART 0x80000100
228 #define REGS_ADDR_GPTIMER 0x80000300
228 #define REGS_ADDR_GPTIMER 0x80000300
229 #define REGS_ADDR_GRSPW 0x80000500
229 #define REGS_ADDR_GRSPW 0x80000500
230 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
230 #define APB_OFFSET_GRSPW_STATUS_REGISTER 0x04
231 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
231 #define APB_OFFSET_GRSPW_TIME_REGISTER 0x14
232 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
232 #define REGS_ADDR_TIME_MANAGEMENT 0x80000600
233 #define REGS_ADDR_GRGPIO 0x80000b00
233 #define REGS_ADDR_GRGPIO 0x80000b00
234
234
235 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
235 #define REGS_ADDR_SPECTRAL_MATRIX 0x80000f00
236 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
236 #define REGS_ADDR_WAVEFORM_PICKER 0x80000f54 // PDB >= 0.1.28
237 #define APB_OFFSET_VHDL_REV 0xb0
237 #define APB_OFFSET_VHDL_REV 0xb0
238 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
238 #define REGS_ADDR_VHDL_VERSION 0x80000ff0
239
239
240 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
240 #define APBUART_CTRL_REG_MASK_DB 0xfffff7ff
241 #define APBUART_CTRL_REG_MASK_TE 0x00000002
241 #define APBUART_CTRL_REG_MASK_TE 0x00000002
242 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
242 // scaler value = system_clock_frequency / ( baud_rate * 8 ) - 1
243 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
243 #define APBUART_SCALER_RELOAD_VALUE 0x00000050 // 25 MHz => about 38400
244
244
245 //**********
245 //**********
246 // IRQ LINES
246 // IRQ LINES
247 #define IRQ_GPTIMER_WATCHDOG 9
247 #define IRQ_GPTIMER_WATCHDOG 9
248 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
248 #define IRQ_SPARC_GPTIMER_WATCHDOG 0x19 // see sparcv8.pdf p.76 for interrupt levels
249 #define IRQ_WAVEFORM_PICKER 14
249 #define IRQ_WAVEFORM_PICKER 14
250 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
250 #define IRQ_SPARC_WAVEFORM_PICKER 0x1e // see sparcv8.pdf p.76 for interrupt levels
251 #define IRQ_SPECTRAL_MATRIX 6
251 #define IRQ_SPECTRAL_MATRIX 6
252 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
252 #define IRQ_SPARC_SPECTRAL_MATRIX 0x16 // see sparcv8.pdf p.76 for interrupt levels
253
253
254 //*****
254 //*****
255 // TIME
255 // TIME
256 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
256 #define CLKDIV_WATCHDOG (10000000 - 1) // 10.0s => 10 000 000
257 #define TIMER_WATCHDOG 1
257 #define TIMER_WATCHDOG 1
258 #define WATCHDOG_PERIOD 100 // 1s
258 #define WATCHDOG_PERIOD 100 // 1s
259 #define HK_PERIOD 100 // 100 * 10ms => 1s
259 #define HK_PERIOD 100 // 100 * 10ms => 1s
260 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
260 #define AVGV_PERIOD 6 // 6 * 10ms => 60ms (1 / 16 = 62.5ms)
261 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
261 #define SY_LFR_TIME_SYN_TIMEOUT_in_ticks 200 // 200 * 10 ms = 2 s
262 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
262 #define HK_SYNC_WAIT 10 // 10 * 10 ms = 100 ms
263 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
263 #define SPW_LINK_WAIT 10 // 10 * 10 ms = 100 ms
264 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
264 #define TIMECODE_TIMER_TIMEOUT 120 // 120 * 10 ms = 1.2 s
265 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
265 #define TIMECODE_TIMER_TIMEOUT_INIT 200 // 200 * 10 ms = 2.0 s
266 #define TIMECODE_MASK 0x3f // 0011 1111
266 #define TIMECODE_MASK 0x3f // 0011 1111
267
267
268 //**********
268 //**********
269 // LPP CODES
269 // LPP CODES
270 #define LFR_SUCCESSFUL 0
270 #define LFR_SUCCESSFUL 0
271 #define LFR_DEFAULT 1
271 #define LFR_DEFAULT 1
272 #define LFR_EXE_ERROR 2
272 #define LFR_EXE_ERROR 2
273 #define LFR_DEFAULT_ALT -1
273 #define LFR_DEFAULT_ALT -1
274
274
275 //******
275 //******
276 // RTEMS
276 // RTEMS
277 #define STACK_SIZE_MULT 2
277 #define STACK_SIZE_MULT 2
278
278
279 #define TASKID_AVGV 0
279 #define TASKID_AVGV 0
280 #define TASKID_RECV 1
280 #define TASKID_RECV 1
281 #define TASKID_ACTN 2
281 #define TASKID_ACTN 2
282 #define TASKID_SPIQ 3
282 #define TASKID_SPIQ 3
283 #define TASKID_LOAD 4
283 #define TASKID_LOAD 4
284 #define TASKID_AVF0 5
284 #define TASKID_AVF0 5
285 #define TASKID_SWBD 6
285 #define TASKID_SWBD 6
286 #define TASKID_WFRM 7
286 #define TASKID_WFRM 7
287 #define TASKID_DUMB 8
287 #define TASKID_DUMB 8
288 #define TASKID_HOUS 9
288 #define TASKID_HOUS 9
289 #define TASKID_PRC0 10
289 #define TASKID_PRC0 10
290 #define TASKID_CWF3 11
290 #define TASKID_CWF3 11
291 #define TASKID_CWF2 12
291 #define TASKID_CWF2 12
292 #define TASKID_CWF1 13
292 #define TASKID_CWF1 13
293 #define TASKID_SEND 14
293 #define TASKID_SEND 14
294 #define TASKID_LINK 15
294 #define TASKID_LINK 15
295 #define TASKID_AVF1 16
295 #define TASKID_AVF1 16
296 #define TASKID_PRC1 17
296 #define TASKID_PRC1 17
297 #define TASKID_AVF2 18
297 #define TASKID_AVF2 18
298 #define TASKID_PRC2 19
298 #define TASKID_PRC2 19
299
299
300 #define TASK_PRIORITY_SPIQ 5
300 #define TASK_PRIORITY_SPIQ 5
301 #define TASK_PRIORITY_LINK 20
301 #define TASK_PRIORITY_LINK 20
302 #define TASK_PRIORITY_AVGV 25
302 #define TASK_PRIORITY_AVGV 25
303 #define TASK_PRIORITY_HOUS 30
303 #define TASK_PRIORITY_HOUS 30
304 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
304 #define TASK_PRIORITY_CWF1 35 // CWF1 and CWF2 are never running together
305 #define TASK_PRIORITY_CWF2 35 //
305 #define TASK_PRIORITY_CWF2 35 //
306 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
306 #define TASK_PRIORITY_SWBD 37 // SWBD has a lower priority than WFRM, this is to extract the snapshot before sending it
307 #define TASK_PRIORITY_WFRM 40
307 #define TASK_PRIORITY_WFRM 40
308 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
308 #define TASK_PRIORITY_CWF3 40 // there is a printf in this function, be careful with its priority wrt CWF1
309 #define TASK_PRIORITY_SEND 45
309 #define TASK_PRIORITY_SEND 45
310 #define TASK_PRIORITY_RECV 50
310 #define TASK_PRIORITY_RECV 50
311 #define TASK_PRIORITY_ACTN 50
311 #define TASK_PRIORITY_ACTN 50
312 #define TASK_PRIORITY_AVF0 60
312 #define TASK_PRIORITY_AVF0 60
313 #define TASK_PRIORITY_AVF1 70
313 #define TASK_PRIORITY_AVF1 70
314 #define TASK_PRIORITY_PRC0 100
314 #define TASK_PRIORITY_PRC0 100
315 #define TASK_PRIORITY_PRC1 100
315 #define TASK_PRIORITY_PRC1 100
316 #define TASK_PRIORITY_AVF2 110
316 #define TASK_PRIORITY_AVF2 110
317 #define TASK_PRIORITY_PRC2 110
317 #define TASK_PRIORITY_PRC2 110
318 #define TASK_PRIORITY_LOAD 190
318 #define TASK_PRIORITY_LOAD 190
319 #define TASK_PRIORITY_DUMB 200
319 #define TASK_PRIORITY_DUMB 200
320
320
321 #define MSG_QUEUE_COUNT_RECV 10
321 #define MSG_QUEUE_COUNT_RECV 10
322 #define MSG_QUEUE_COUNT_SEND 50
322 #define MSG_QUEUE_COUNT_SEND 50
323 #define MSG_QUEUE_COUNT_PRC0 10
323 #define MSG_QUEUE_COUNT_PRC0 10
324 #define MSG_QUEUE_COUNT_PRC1 10
324 #define MSG_QUEUE_COUNT_PRC1 10
325 #define MSG_QUEUE_COUNT_PRC2 5
325 #define MSG_QUEUE_COUNT_PRC2 5
326 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
326 #define MSG_QUEUE_SIZE_SEND 812 // 808 + 4 => TM_LFR_SCIENCE_BURST_BP2_F1
327 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
327 #define ACTION_MSG_SPW_IOCTL_SEND_SIZE 24 // hlen *hdr dlen *data sent options
328 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
328 #define MSG_QUEUE_SIZE_PRC0 36 // two pointers, one rtems_event + 6 integers
329 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
329 #define MSG_QUEUE_SIZE_PRC1 36 // two pointers, one rtems_event + 6 integers
330 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
330 #define MSG_QUEUE_SIZE_PRC2 36 // two pointers, one rtems_event + 6 integers
331
331
332 #define QUEUE_RECV 0
332 #define QUEUE_RECV 0
333 #define QUEUE_SEND 1
333 #define QUEUE_SEND 1
334 #define QUEUE_PRC0 2
334 #define QUEUE_PRC0 2
335 #define QUEUE_PRC1 3
335 #define QUEUE_PRC1 3
336 #define QUEUE_PRC2 4
336 #define QUEUE_PRC2 4
337
337
338 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
338 #define CPU_USAGE_REPORT_PERIOD 6 // * 10 s = period
339
339
340 struct param_local_str{
340 struct param_local_str{
341 unsigned int local_sbm1_nb_cwf_sent;
341 unsigned int local_sbm1_nb_cwf_sent;
342 unsigned int local_sbm1_nb_cwf_max;
342 unsigned int local_sbm1_nb_cwf_max;
343 unsigned int local_sbm2_nb_cwf_sent;
343 unsigned int local_sbm2_nb_cwf_sent;
344 unsigned int local_sbm2_nb_cwf_max;
344 unsigned int local_sbm2_nb_cwf_max;
345 };
345 };
346
346
347 //************
347 //************
348 // FBINS MASKS
348 // FBINS MASKS
349
349
350 #define BYTES_PER_FBINS_MASK 16
350 #define BYTES_PER_FBINS_MASK 16
351
351
352 typedef struct {
352 typedef struct {
353 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
353 unsigned char merged_fbins_mask_f0[BYTES_PER_FBINS_MASK];
354 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
354 unsigned char merged_fbins_mask_f1[BYTES_PER_FBINS_MASK];
355 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
355 unsigned char merged_fbins_mask_f2[BYTES_PER_FBINS_MASK];
356 } fbins_masks_t;
356 } fbins_masks_t;
357
357
358 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
358 #define DEFAULT_SY_LFR_PAS_FILTER_ENABLED 0
359 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
359 #define DEFAULT_SY_LFR_PAS_FILTER_MODULUS 4
360 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
360 #define DEFAULT_SY_LFR_PAS_FILTER_TBAD 1.0
361 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
361 #define DEFAULT_SY_LFR_PAS_FILTER_OFFSET 0
362 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
362 #define DEFAULT_SY_LFR_PAS_FILTER_SHIFT 0.5
363 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
363 #define DEFAULT_SY_LFR_SC_RW_DELTA_F 0.045
364 #define DEFAULT_SY_LFR_RW_K1 1.
364 #define DEFAULT_SY_LFR_RW_K1 1.
365 #define DEFAULT_SY_LFR_RW_K2 8.
365 #define DEFAULT_SY_LFR_RW_K2 8.
366 #define DEFAULT_SY_LFR_RW_K3 24.
366 #define DEFAULT_SY_LFR_RW_K3 24.
367 #define DEFAULT_SY_LFR_RW_K4 48.
367 #define DEFAULT_SY_LFR_RW_K4 48.
368
368
369 typedef struct{
369 typedef struct{
370 unsigned char spare_sy_lfr_pas_filter_enabled;
370 unsigned char spare_sy_lfr_pas_filter_enabled;
371 unsigned char sy_lfr_pas_filter_modulus;
371 unsigned char sy_lfr_pas_filter_modulus;
372 float sy_lfr_pas_filter_tbad;
372 float sy_lfr_pas_filter_tbad;
373 unsigned char sy_lfr_pas_filter_offset;
373 unsigned char sy_lfr_pas_filter_offset;
374 float sy_lfr_pas_filter_shift;
374 float sy_lfr_pas_filter_shift;
375 float sy_lfr_sc_rw_delta_f;
375 float sy_lfr_sc_rw_delta_f;
376 // rw1_k
376 // rw1_k
377 float sy_lfr_rw1_k1;
377 float sy_lfr_rw1_k1;
378 float sy_lfr_rw1_k2;
378 float sy_lfr_rw1_k2;
379 float sy_lfr_rw1_k3;
379 float sy_lfr_rw1_k3;
380 float sy_lfr_rw1_k4;
380 float sy_lfr_rw1_k4;
381 // rw2_k
381 // rw2_k
382 float sy_lfr_rw2_k1;
382 float sy_lfr_rw2_k1;
383 float sy_lfr_rw2_k2;
383 float sy_lfr_rw2_k2;
384 float sy_lfr_rw2_k3;
384 float sy_lfr_rw2_k3;
385 float sy_lfr_rw2_k4;
385 float sy_lfr_rw2_k4;
386 // rw3_k
386 // rw3_k
387 float sy_lfr_rw3_k1;
387 float sy_lfr_rw3_k1;
388 float sy_lfr_rw3_k2;
388 float sy_lfr_rw3_k2;
389 float sy_lfr_rw3_k3;
389 float sy_lfr_rw3_k3;
390 float sy_lfr_rw3_k4;
390 float sy_lfr_rw3_k4;
391 // rw4_k
391 // rw4_k
392 float sy_lfr_rw4_k1;
392 float sy_lfr_rw4_k1;
393 float sy_lfr_rw4_k2;
393 float sy_lfr_rw4_k2;
394 float sy_lfr_rw4_k3;
394 float sy_lfr_rw4_k3;
395 float sy_lfr_rw4_k4;
395 float sy_lfr_rw4_k4;
396 } filterPar_t;
396 } filterPar_t;
397
397
398 typedef struct{
398 typedef struct{
399 // rw1_f
399 // rw1_f
400 float cp_rpw_sc_rw1_f1;
400 float cp_rpw_sc_rw1_f1;
401 float cp_rpw_sc_rw1_f2;
401 float cp_rpw_sc_rw1_f2;
402 float cp_rpw_sc_rw1_f3;
402 float cp_rpw_sc_rw1_f3;
403 float cp_rpw_sc_rw1_f4;
403 float cp_rpw_sc_rw1_f4;
404 // rw2_f
404 // rw2_f
405 float cp_rpw_sc_rw2_f1;
405 float cp_rpw_sc_rw2_f1;
406 float cp_rpw_sc_rw2_f2;
406 float cp_rpw_sc_rw2_f2;
407 float cp_rpw_sc_rw2_f3;
407 float cp_rpw_sc_rw2_f3;
408 float cp_rpw_sc_rw2_f4;
408 float cp_rpw_sc_rw2_f4;
409 // rw3_f
409 // rw3_f
410 float cp_rpw_sc_rw3_f1;
410 float cp_rpw_sc_rw3_f1;
411 float cp_rpw_sc_rw3_f2;
411 float cp_rpw_sc_rw3_f2;
412 float cp_rpw_sc_rw3_f3;
412 float cp_rpw_sc_rw3_f3;
413 float cp_rpw_sc_rw3_f4;
413 float cp_rpw_sc_rw3_f4;
414 // rw4_f
414 // rw4_f
415 float cp_rpw_sc_rw4_f1;
415 float cp_rpw_sc_rw4_f1;
416 float cp_rpw_sc_rw4_f2;
416 float cp_rpw_sc_rw4_f2;
417 float cp_rpw_sc_rw4_f3;
417 float cp_rpw_sc_rw4_f3;
418 float cp_rpw_sc_rw4_f4;
418 float cp_rpw_sc_rw4_f4;
419 } rw_f_t;
419 } rw_f_t;
420
420
421 #define NB_ACQUISITION_DURATION 3
421 #define MATRIX_IS_POLLUTED 0
422 #define MATRIX_IS_NOT_POLLUTED 1
422 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
423 #define ACQUISITION_DURATION_F0 683 // 256 / 24576 * 65536
423 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
424 #define ACQUISITION_DURATION_F1 4096 // 256 / 4096 * 65536
424 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
425 #define ACQUISITION_DURATION_F2 65536 // 256 / 256 * 65536
426 #define HALF_ACQUISITION_DURATION_F0 341 // 256 / 24576 * 65536 / 2
427 #define HALF_ACQUISITION_DURATION_F1 2048 // 256 / 4096 * 65536 / 2
428 #define HALF_ACQUISITION_DURATION_F2 32768 // 256 / 256 * 65536 / 2
425
429
426 #endif // FSW_PARAMS_H_INCLUDED
430 #endif // FSW_PARAMS_H_INCLUDED
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