@@ -50,6 +50,7 volatile int sm_f1[ NB_RING_NODES_SM_F1 | |||
|
50 | 50 | volatile int sm_f2[ NB_RING_NODES_SM_F2 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100))); |
|
51 | 51 | |
|
52 | 52 | // APB CONFIGURATION REGISTERS |
|
53 | struct grgpio_regs_str *grgpio_regs = (struct grgpio_regs_str *) REGS_ADDR_GRGPIO; | |
|
53 | 54 | time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT; |
|
54 | 55 | gptimer_regs_t *gptimer_regs = (gptimer_regs_t *) REGS_ADDR_GPTIMER; |
|
55 | 56 | waveform_picker_regs_0_1_18_t *waveform_picker_regs = (waveform_picker_regs_0_1_18_t*) REGS_ADDR_WAVEFORM_PICKER; |
@@ -251,6 +251,14 rtems_task Init( rtems_task_argument ign | |||
|
251 | 251 | |
|
252 | 252 | set_hk_lfr_sc_potential_flag( true ); |
|
253 | 253 | |
|
254 | //********************************* | |
|
255 | // init GPIO for trigger generation | |
|
256 | struct grgpio_regs_str *grgpio_regs = (struct grgpio_regs_str *) REGS_ADDR_GRGPIO; | |
|
257 | grgpio_regs->io_port_direction_register = | |
|
258 | grgpio_regs->io_port_direction_register | 0x08; // [0000 1000], 0 = output disabled, 1 = output enabled | |
|
259 | grgpio_regs->io_port_direction_register = | |
|
260 | grgpio_regs->io_port_direction_register | 0x04; // [0000 0100], 0 = output disabled, 1 = output enabled | |
|
261 | ||
|
254 | 262 | status = rtems_task_delete(RTEMS_SELF); |
|
255 | 263 | |
|
256 | 264 | } |
@@ -192,6 +192,20 rtems_task hous_task(rtems_task_argument | |||
|
192 | 192 | set_hk_lfr_reset_cause( POWER_ON ); |
|
193 | 193 | |
|
194 | 194 | while(1){ // launch the rate monotonic task |
|
195 | // //******* | |
|
196 | // // GPIO 3 | |
|
197 | // struct grgpio_regs_str *grgpio_regs = (struct grgpio_regs_str *) REGS_ADDR_GRGPIO; | |
|
198 | // if ( (grgpio_regs->io_port_output_register & 0x07) == 0x02 ) // [010] | |
|
199 | // { | |
|
200 | // grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8; // [1111 1000] | |
|
201 | // } | |
|
202 | // else | |
|
203 | // { | |
|
204 | // grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02; // [0000 0010] | |
|
205 | // } | |
|
206 | // | |
|
207 | //******* | |
|
208 | ||
|
195 | 209 | status = rtems_rate_monotonic_period( HK_id, HK_PERIOD ); |
|
196 | 210 | if ( status != RTEMS_SUCCESSFUL ) { |
|
197 | 211 | PRINTF1( "in HOUS *** ERR period: %d\n", status); |
@@ -22,6 +22,10 Header_TM_LFR_SCIENCE_CWF_t headerCWF; | |||
|
22 | 22 | Header_TM_LFR_SCIENCE_SWF_t headerSWF; |
|
23 | 23 | Header_TM_LFR_SCIENCE_ASM_t headerASM; |
|
24 | 24 | |
|
25 | extern struct grgpio_regs_str *grgpio_regs; | |
|
26 | #define OUTPUT_1 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8; | |
|
27 | #define OUTPUT_0 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02; | |
|
28 | ||
|
25 | 29 | //*********** |
|
26 | 30 | // RTEMS TASK |
|
27 | 31 | rtems_task spiq_task(rtems_task_argument unused) |
@@ -660,6 +664,8 void spacewire_update_statistics( void ) | |||
|
660 | 664 | |
|
661 | 665 | void timecode_irq_handler( void *pDev, void *regs, int minor, unsigned int tc ) |
|
662 | 666 | { |
|
667 | OUTPUT_1; | |
|
668 | ||
|
663 | 669 | // a valid timecode has been received, write it in the HK report |
|
664 | 670 | unsigned int *grspwPtr; |
|
665 | 671 | unsigned char timecodeCtr; |
@@ -693,6 +699,8 void timecode_irq_handler( void *pDev, v | |||
|
693 | 699 | housekeeping_packet.hk_lfr_time_timecode_ctr = housekeeping_packet.hk_lfr_time_timecode_ctr + 1; |
|
694 | 700 | } |
|
695 | 701 | } |
|
702 | ||
|
703 | OUTPUT_0; | |
|
696 | 704 | } |
|
697 | 705 | |
|
698 | 706 | rtems_timer_service_routine user_routine( rtems_id timer_id, void *user_data ) |
@@ -16,6 +16,10 unsigned int nb_sm_f0_aux_f1; | |||
|
16 | 16 | unsigned int nb_sm_f1; |
|
17 | 17 | unsigned int nb_sm_f0_aux_f2; |
|
18 | 18 | |
|
19 | extern struct grgpio_regs_str *grgpio_regs; | |
|
20 | #define OUTPUT_1 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8; | |
|
21 | #define OUTPUT_0 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02; | |
|
22 | ||
|
19 | 23 | //************************ |
|
20 | 24 | // spectral matrices rings |
|
21 | 25 | ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ]; |
@@ -56,6 +60,8 ring_node * getRingNodeForAveraging( uns | |||
|
56 | 60 | |
|
57 | 61 | void spectral_matrices_isr_f0( unsigned char statusReg ) |
|
58 | 62 | { |
|
63 | // OUTPUT_1; | |
|
64 | ||
|
59 | 65 | unsigned char status; |
|
60 | 66 | rtems_status_code status_code; |
|
61 | 67 | ring_node *full_ring_node; |
@@ -110,10 +116,13 void spectral_matrices_isr_f0( unsigned | |||
|
110 | 116 | spectral_matrix_regs->status = 0x02; // [0000 0010] |
|
111 | 117 | break; |
|
112 | 118 | } |
|
119 | // OUTPUT_0; | |
|
113 | 120 | } |
|
114 | 121 | |
|
115 | 122 | void spectral_matrices_isr_f1( unsigned char statusReg ) |
|
116 | 123 | { |
|
124 | // OUTPUT_1; | |
|
125 | ||
|
117 | 126 | rtems_status_code status_code; |
|
118 | 127 | unsigned char status; |
|
119 | 128 | ring_node *full_ring_node; |
@@ -168,10 +177,14 void spectral_matrices_isr_f1( unsigned | |||
|
168 | 177 | spectral_matrix_regs->status = 0x08; // [1000 0000] |
|
169 | 178 | break; |
|
170 | 179 | } |
|
180 | ||
|
181 | // OUTPUT_0; | |
|
171 | 182 | } |
|
172 | 183 | |
|
173 | 184 | void spectral_matrices_isr_f2( unsigned char statusReg ) |
|
174 | 185 | { |
|
186 | // OUTPUT_1; | |
|
187 | ||
|
175 | 188 | unsigned char status; |
|
176 | 189 | rtems_status_code status_code; |
|
177 | 190 | |
@@ -211,6 +224,8 void spectral_matrices_isr_f2( unsigned | |||
|
211 | 224 | } |
|
212 | 225 | break; |
|
213 | 226 | } |
|
227 | ||
|
228 | // OUTPUT_0; | |
|
214 | 229 | } |
|
215 | 230 | |
|
216 | 231 | void spectral_matrix_isr_error_handler( unsigned char statusReg ) |
@@ -235,6 +250,8 rtems_isr spectral_matrices_isr( rtems_v | |||
|
235 | 250 | |
|
236 | 251 | unsigned char statusReg; |
|
237 | 252 | |
|
253 | // OUTPUT_1; | |
|
254 | ||
|
238 | 255 | statusReg = spectral_matrix_regs->status; |
|
239 | 256 | |
|
240 | 257 | spectral_matrices_isr_f0( statusReg ); |
@@ -244,6 +261,9 rtems_isr spectral_matrices_isr( rtems_v | |||
|
244 | 261 | spectral_matrices_isr_f2( statusReg ); |
|
245 | 262 | |
|
246 | 263 | spectral_matrix_isr_error_handler( statusReg ); |
|
264 | ||
|
265 | // OUTPUT_0; | |
|
266 | ||
|
247 | 267 | } |
|
248 | 268 | |
|
249 | 269 | rtems_isr spectral_matrices_isr_simu( rtems_vector_number vector ) |
@@ -9,6 +9,10 | |||
|
9 | 9 | |
|
10 | 10 | #include "wf_handler.h" |
|
11 | 11 | |
|
12 | extern struct grgpio_regs_str *grgpio_regs; | |
|
13 | #define OUTPUT_1 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8; | |
|
14 | #define OUTPUT_0 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02; | |
|
15 | ||
|
12 | 16 | //*************** |
|
13 | 17 | // waveform rings |
|
14 | 18 | // F0 |
@@ -409,6 +413,8 rtems_isr waveforms_isr( rtems_vector_nu | |||
|
409 | 413 | // 7 6 5 4 3 2 1 0 |
|
410 | 414 | // f3_1 f3_0 f2_1 f2_0 f1_1 f1_0 f0_1 f0_0 |
|
411 | 415 | |
|
416 | // OUTPUT_1; | |
|
417 | ||
|
412 | 418 | rtems_status_code spare_status; |
|
413 | 419 | |
|
414 | 420 | waveforms_isr_f3(); |
@@ -454,6 +460,8 rtems_isr waveforms_isr( rtems_vector_nu | |||
|
454 | 460 | default: |
|
455 | 461 | break; |
|
456 | 462 | } |
|
463 | ||
|
464 | // OUTPUT_0; | |
|
457 | 465 | } |
|
458 | 466 | |
|
459 | 467 | //************ |
General Comments 0
You need to be logged in to leave comments.
Login now