HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/JEANDET/LFR_FSW Commit - r242:feeb51833794

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r242:feeb51833794 R3

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r242:feeb51833794

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src/fsw_globals.c +1 0

             volatile int sm_f2[ NB_RING_NODES_SM_F2 * TOTAL_SIZE_SM ] __attribute__((aligned(0x100)));
             // APB CONFIGURATION REGISTERS
+            struct grgpio_regs_str          *grgpio_regs            = (struct grgpio_regs_str *)        REGS_ADDR_GRGPIO;
             time_management_regs_t          *time_management_regs   = (time_management_regs_t*)         REGS_ADDR_TIME_MANAGEMENT;
             gptimer_regs_t                  *gptimer_regs           = (gptimer_regs_t *)                REGS_ADDR_GPTIMER;
             waveform_picker_regs_0_1_18_t   *waveform_picker_regs   = (waveform_picker_regs_0_1_18_t*)  REGS_ADDR_WAVEFORM_PICKER;

src/fsw_init.c +8 0

                 set_hk_lfr_sc_potential_flag( true );
+                //*********************************
+                // init GPIO for trigger generation
+                struct grgpio_regs_str *grgpio_regs = (struct grgpio_regs_str *) REGS_ADDR_GRGPIO;
+                grgpio_regs->io_port_direction_register =
+                        grgpio_regs->io_port_direction_register | 0x08; // [0000 1000], 0 = output disabled, 1 = output enabled
+                grgpio_regs->io_port_direction_register =
+                        grgpio_regs->io_port_direction_register | 0x04; // [0000 0100], 0 = output disabled, 1 = output enabled
                 status = rtems_task_delete(RTEMS_SELF);
             }

src/fsw_misc.c +14 0

@@ -192,6 +192,20 rtems_task hous_task(rtems_task_argument
192	set_hk_lfr_reset_cause( POWER_ON );	192	set_hk_lfr_reset_cause( POWER_ON );
193		193
194	while(1){ // launch the rate monotonic task	194	while(1){ // launch the rate monotonic task
		195	// //*******
		196	// // GPIO 3
		197	// struct grgpio_regs_str grgpio_regs = (struct grgpio_regs_str ) REGS_ADDR_GRGPIO;
		198	// if ( (grgpio_regs->io_port_output_register & 0x07) == 0x02 ) // [010]
		199	// {
		200	// grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8; // [1111 1000]
		201	// }
		202	// else
		203	// {
		204	// grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register \| 0x02; // [0000 0010]
		205	// }
		206	//
		207	//*******
		208
195	status = rtems_rate_monotonic_period( HK_id, HK_PERIOD );	209	status = rtems_rate_monotonic_period( HK_id, HK_PERIOD );
196	if ( status != RTEMS_SUCCESSFUL ) {	210	if ( status != RTEMS_SUCCESSFUL ) {
197	PRINTF1( "in HOUS *** ERR period: %d\n", status);	211	PRINTF1( "in HOUS *** ERR period: %d\n", status);

src/fsw_spacewire.c +8 0

             Header_TM_LFR_SCIENCE_SWF_t headerSWF;
             Header_TM_LFR_SCIENCE_ASM_t headerASM;
+            extern struct grgpio_regs_str *grgpio_regs;
+            #define OUTPUT_1 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8;
+            #define OUTPUT_0 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02;
             //***********
             // RTEMS TASK
             rtems_task spiq_task(rtems_task_argument unused)
             void timecode_irq_handler( void *pDev, void *regs, int minor, unsigned int tc )
             {
+                OUTPUT_1;
                 // a valid timecode has been received, write it in the HK report
                 unsigned int *grspwPtr;
                 unsigned char timecodeCtr;
                         housekeeping_packet.hk_lfr_time_timecode_ctr = housekeeping_packet.hk_lfr_time_timecode_ctr + 1;
                     }
                 }
+                OUTPUT_0;
             }
             rtems_timer_service_routine user_routine( rtems_id timer_id, void *user_data )

src/processing/fsw_processing.c +20 0

             unsigned int nb_sm_f1;
             unsigned int nb_sm_f0_aux_f2;
+            extern struct grgpio_regs_str *grgpio_regs;
+            #define OUTPUT_1 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8;
+            #define OUTPUT_0 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02;
             //************************
             // spectral matrices rings
             ring_node sm_ring_f0[ NB_RING_NODES_SM_F0 ];
             void spectral_matrices_isr_f0( unsigned char statusReg )
             {
+            //    OUTPUT_1;
                 unsigned char status;
                 rtems_status_code status_code;
                 ring_node *full_ring_node;
                     spectral_matrix_regs->status = 0x02;   // [0000 0010]
                     break;
                 }
+            //    OUTPUT_0;
             }
             void spectral_matrices_isr_f1( unsigned char statusReg )
             {
+            //    OUTPUT_1;
                 rtems_status_code status_code;
                 unsigned char status;
                 ring_node *full_ring_node;
                     spectral_matrix_regs->status = 0x08;   // [1000 0000]
                     break;
                 }
+            //    OUTPUT_0;
             }
             void spectral_matrices_isr_f2( unsigned char statusReg )
             {
+            //    OUTPUT_1;
                 unsigned char status;
                 rtems_status_code status_code;
                     }
                     break;
                 }
+            //    OUTPUT_0;
             }
             void spectral_matrix_isr_error_handler( unsigned char statusReg )
                 unsigned char statusReg;
+            //    OUTPUT_1;
                 statusReg = spectral_matrix_regs->status;
                 spectral_matrices_isr_f0( statusReg );
                 spectral_matrices_isr_f2( statusReg );
                 spectral_matrix_isr_error_handler( statusReg );
+            //    OUTPUT_0;
             }
             rtems_isr spectral_matrices_isr_simu( rtems_vector_number vector )

src/wf_handler.c +8 0

             #include "wf_handler.h"
+            extern struct grgpio_regs_str *grgpio_regs;
+            #define OUTPUT_1 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register & 0xf8;
+            #define OUTPUT_0 grgpio_regs->io_port_output_register = grgpio_regs->io_port_output_register | 0x02;
             //***************
             // waveform rings
             // F0
                 // 7    6    5    4    3    2    1    0
                 // f3_1 f3_0 f2_1 f2_0 f1_1 f1_0 f0_1 f0_0
+            //    OUTPUT_1;
                 rtems_status_code spare_status;
                 waveforms_isr_f3();
                     default:
                     break;
                 }
+            //    OUTPUT_0;
             }
             //************

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