##// END OF EJS Templates
SM simulator functionnal...
paul -
r100:e4348633316b VHDLib206
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@@ -1,6 +1,6
1 <?xml version="1.0" encoding="UTF-8"?>
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!DOCTYPE QtCreatorProject>
2 <!DOCTYPE QtCreatorProject>
3 <!-- Written by QtCreator 3.0.0, 2014-02-19T07:19:44. -->
3 <!-- Written by QtCreator 3.0.0, 2014-02-20T06:55:01. -->
4 <qtcreator>
4 <qtcreator>
5 <data>
5 <data>
6 <variable>ProjectExplorer.Project.ActiveTarget</variable>
6 <variable>ProjectExplorer.Project.ActiveTarget</variable>
@@ -202,15 +202,12 enum apid_destid{
202 #define PACKET_LENGTH_TC_EXE_CORRUPTED (32 - CCSDS_TC_TM_PACKET_OFFSET)
202 #define PACKET_LENGTH_TC_EXE_CORRUPTED (32 - CCSDS_TC_TM_PACKET_OFFSET)
203 #define PACKET_LENGTH_HK (124 - CCSDS_TC_TM_PACKET_OFFSET)
203 #define PACKET_LENGTH_HK (124 - CCSDS_TC_TM_PACKET_OFFSET)
204 #define PACKET_LENGTH_PARAMETER_DUMP (36 - CCSDS_TC_TM_PACKET_OFFSET)
204 #define PACKET_LENGTH_PARAMETER_DUMP (36 - CCSDS_TC_TM_PACKET_OFFSET)
205 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0 (TOTAL_SIZE_ASM_F0 + HEADER_LENGTH_TM_LFR_SCIENCE_ASM - CCSDS_TC_TM_PACKET_OFFSET)
205 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0 2221 // 44 * 25 * 2 + 28 - 7
206 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1 (TOTAL_SIZE_ASM_F1 + HEADER_LENGTH_TM_LFR_SCIENCE_ASM - CCSDS_TC_TM_PACKET_OFFSET)
206 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F1 2621 // 52 * 25 * 2 + 28 - 7
207 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F2 (TOTAL_SIZE_ASM_F2 + HEADER_LENGTH_TM_LFR_SCIENCE_ASM - CCSDS_TC_TM_PACKET_OFFSET)
207 #define PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F2 2421 // 48 * 25 * 2 + 28 - 7
208
208
209 #define SPARE1_PUSVERSION_SPARE2 0x10
209 #define SPARE1_PUSVERSION_SPARE2 0x10
210
210
211 #define LEN_TM_LFR_HK 130 // 126 + 4
212 #define LEN_TM_LFR_TC_EXE_NOT_IMP 28 // 24 + 4
213
214 // R1
211 // R1
215 #define TM_LEN_SCI_SWF_340 4101 // 340 * 12 + 10 + 12 - 1
212 #define TM_LEN_SCI_SWF_340 4101 // 340 * 12 + 10 + 12 - 1
216 #define TM_LEN_SCI_SWF_8 117 // 8 * 12 + 10 + 12 - 1
213 #define TM_LEN_SCI_SWF_8 117 // 8 * 12 + 10 + 12 - 1
@@ -7,16 +7,19
7 #define SM_HEADER 0 //
7 #define SM_HEADER 0 //
8 //
8 //
9 #define NB_BINS_PER_ASM_F0 88
9 #define NB_BINS_PER_ASM_F0 88
10 #define TOTAL_SIZE_ASM_F0 2200 // 25 * 88
10 #define NB_BINS_PER_PKT_ASM_F0 44
11 #define TOTAL_SIZE_ASM_F0_IN_BYTES 4400 // 25 * 88 * 2
11 #define ASM_F0_INDICE_START 17 // 88 bins
12 #define ASM_F0_INDICE_START 17 // 88 bins
12 #define ASM_F0_INDICE_STOP 104 // 2 packets of 44 bins
13 #define ASM_F0_INDICE_STOP 104 // 2 packets of 44 bins
13 //
14 //
14 #define NB_BINS_PER_ASM_F1 104
15 #define NB_BINS_PER_ASM_F1 104
16 #define NB_BINS_PER_PKT_ASM_F1 52
15 #define TOTAL_SIZE_ASM_F1 2600 // 25 * 104
17 #define TOTAL_SIZE_ASM_F1 2600 // 25 * 104
16 #define ASM_F1_INDICE_START 6 // 104 bins
18 #define ASM_F1_INDICE_START 6 // 104 bins
17 #define ASM_F1_INDICE_STOP 109 // 2 packets of 52 bins
19 #define ASM_F1_INDICE_STOP 109 // 2 packets of 52 bins
18 //
20 //
19 #define NB_BINS_PER_ASM_F2 96
21 #define NB_BINS_PER_ASM_F2 96
22 #define NB_BINS_PER_PKT_ASM_F2 48
20 #define TOTAL_SIZE_ASM_F2 2400 // 25 * 96
23 #define TOTAL_SIZE_ASM_F2 2400 // 25 * 96
21 #define ASM_F2_INDICE_START 7 // 96 bins
24 #define ASM_F2_INDICE_START 7 // 96 bins
22 #define ASM_F2_INDICE_STOP 102 // 2 packets of 48 bins
25 #define ASM_F2_INDICE_STOP 102 // 2 packets of 48 bins
@@ -19,9 +19,9 extern int fdSPW;
19 // F0
19 // F0
20 //extern volatile int wf_snap_f0[ ];
20 //extern volatile int wf_snap_f0[ ];
21 // F1 F2
21 // F1 F2
22 extern volatile int wf_snap_f0[ ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ];
22 extern volatile int wf_snap_f0[ ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 62 ];
23 extern volatile int wf_snap_f1[ ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ];
23 extern volatile int wf_snap_f1[ ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 62 ];
24 extern volatile int wf_snap_f2[ ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ];
24 extern volatile int wf_snap_f2[ ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 62 ];
25 // F3
25 // F3
26 extern volatile int wf_cont_f3_a[ ];
26 extern volatile int wf_cont_f3_a[ ];
27 extern volatile int wf_cont_f3_b[ ];
27 extern volatile int wf_cont_f3_b[ ];
@@ -31,22 +31,24 int fdSPW = 0;
31 int fdUART = 0;
31 int fdUART = 0;
32 unsigned char lfrCurrentMode;
32 unsigned char lfrCurrentMode;
33
33
34 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes
34 // WAVEFORMS GLOBAL VARIABLES // 2048 * 3 * 4 + 2 * 4 = 24576 + 8 bytes = 24584
35 // 97 * 256 = 24832 => delta = 248 bytes = 62 words
36 // WAVEFORMS GLOBAL VARIABLES // 2688 * 3 * 4 + 2 * 4 = 32256 + 8 bytes = 32264
37 // 127 * 256 = 32512 => delta = 248 bytes = 62 words
35 // F0
38 // F0
36 //volatile int wf_snap_f0 [ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ] __attribute__((aligned(0x100)));
39 volatile int wf_snap_f0[ NB_RING_NODES_F0 ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 62 ] __attribute__((aligned(0x100)));
37 volatile int wf_snap_f0[ NB_RING_NODES_F0 ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ] __attribute__((aligned(0x100)));
38 // F1 F2
40 // F1 F2
39 volatile int wf_snap_f1[ NB_RING_NODES_F1 ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ] __attribute__((aligned(0x100)));
41 volatile int wf_snap_f1[ NB_RING_NODES_F1 ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 62 ] __attribute__((aligned(0x100)));
40 volatile int wf_snap_f2[ NB_RING_NODES_F2 ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 46 ] __attribute__((aligned(0x100)));
42 volatile int wf_snap_f2[ NB_RING_NODES_F2 ][ (NB_SAMPLES_PER_SNAPSHOT * NB_WORDS_SWF_BLK) + TIME_OFFSET + 62 ] __attribute__((aligned(0x100)));
41 // F3
43 // F3
42 volatile int wf_cont_f3_a [ (NB_SAMPLES_PER_SNAPSHOT) * NB_WORDS_SWF_BLK + TIME_OFFSET ] __attribute__((aligned(0x100)));
44 volatile int wf_cont_f3_a [ (NB_SAMPLES_PER_SNAPSHOT) * NB_WORDS_SWF_BLK + TIME_OFFSET ] __attribute__((aligned(0x100)));
43 volatile int wf_cont_f3_b [ (NB_SAMPLES_PER_SNAPSHOT) * NB_WORDS_SWF_BLK + TIME_OFFSET ] __attribute__((aligned(0x100)));
45 volatile int wf_cont_f3_b [ (NB_SAMPLES_PER_SNAPSHOT) * NB_WORDS_SWF_BLK + TIME_OFFSET ] __attribute__((aligned(0x100)));
44 char wf_cont_f3_light[ (NB_SAMPLES_PER_SNAPSHOT) * NB_BYTES_CWF3_LIGHT_BLK + TIME_OFFSET_IN_BYTES ] __attribute__((aligned(0x100)));
46 char wf_cont_f3_light[ (NB_SAMPLES_PER_SNAPSHOT) * NB_BYTES_CWF3_LIGHT_BLK + TIME_OFFSET_IN_BYTES ] __attribute__((aligned(0x100)));
45
47
46 // SPECTRAL MATRICES GLOBAL VARIABLES
48 // SPECTRAL MATRICES GLOBAL VARIABLES
47 volatile int sm_f0[ NB_RING_NODES_ASM_F0 ][ SM_HEADER + TOTAL_SIZE_SM ];
49 volatile int sm_f0[ NB_RING_NODES_ASM_F0 ][ SM_HEADER + TOTAL_SIZE_SM ] __attribute__((aligned(0x100)));
48 volatile int sm_f1[ NB_RING_NODES_ASM_F1 ][ SM_HEADER + TOTAL_SIZE_SM ];
50 volatile int sm_f1[ NB_RING_NODES_ASM_F1 ][ SM_HEADER + TOTAL_SIZE_SM ] __attribute__((aligned(0x100)));
49 volatile int sm_f2[ NB_RING_NODES_ASM_F2 ][ SM_HEADER + TOTAL_SIZE_SM ];
51 volatile int sm_f2[ NB_RING_NODES_ASM_F2 ][ SM_HEADER + TOTAL_SIZE_SM ] __attribute__((aligned(0x100)));
50
52
51 // APB CONFIGURATION REGISTERS
53 // APB CONFIGURATION REGISTERS
52 time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT;
54 time_management_regs_t *time_management_regs = (time_management_regs_t*) REGS_ADDR_TIME_MANAGEMENT;
@@ -25,6 +25,8 void configure_timer(gptimer_regs_t *gpt
25 rtems_status_code status;
25 rtems_status_code status;
26 rtems_isr_entry old_isr_handler;
26 rtems_isr_entry old_isr_handler;
27
27
28 gptimer_regs->timer[timer].ctrl = 0x00; // reset the control register
29
28 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
30 status = rtems_interrupt_catch( timer_isr, interrupt_level, &old_isr_handler) ; // see sparcv8.pdf p.76 for interrupt levels
29 if (status!=RTEMS_SUCCESSFUL)
31 if (status!=RTEMS_SUCCESSFUL)
30 {
32 {
@@ -109,24 +109,23 rtems_isr spectral_matrices_isr( rtems_v
109
109
110 rtems_isr spectral_matrices_isr_simu( rtems_vector_number vector )
110 rtems_isr spectral_matrices_isr_simu( rtems_vector_number vector )
111 {
111 {
112 current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
112 //current_ring_node_sm_f0 = current_ring_node_sm_f0->next;
113 spectral_matrix_regs->matrixF0_Address0 = current_ring_node_sm_f0->buffer_address;
113 //spectral_matrix_regs->matrixF0_Address0 = current_ring_node_sm_f0->buffer_address;
114 spectral_matrix_regs->status = spectral_matrix_regs->status & 0xfffffffe;
114 //spectral_matrix_regs->status = spectral_matrix_regs->status & 0xfffffffe;
115
115
116 rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 );
116 if (nb_sm_f0 == (NB_SM_TO_RECEIVE_BEFORE_AVF0-1) )
117 // if (nb_sm_f0 == NB_SM_TO_RECEIVE_BEFORE_AVF0 )
117 {
118 // {
118 ring_node_for_averaging_sm_f0 = current_ring_node_sm_f0;
119 // ring_node_for_averaging_sm_f0 = current_ring_node_sm_f0;
119 if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
120 // if (rtems_event_send( Task_id[TASKID_AVF0], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL)
120 {
121 // {
121 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
122 // rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_3 );
122 }
123 // }
123 nb_sm_f0 = 0;
124 // nb_sm_f0 = 0;
124 }
125 // }
125 else
126 // else
126 {
127 // {
127 nb_sm_f0 = nb_sm_f0 + 1;
128 // nb_sm_f0 = nb_sm_f0 + 1;
128 }
129 // }
130 }
129 }
131
130
132 //************
131 //************
@@ -169,12 +168,12 rtems_task avf0_task(rtems_task_argument
169
168
170 while(1){
169 while(1){
171 rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT0
170 rtems_event_receive(RTEMS_EVENT_0, RTEMS_WAIT, RTEMS_NO_TIMEOUT, &event_out); // wait for an RTEMS_EVENT0
172 PRINTF("avf0\n")
171 ring_node_for_averaging_sm_f0 = &sm_ring_f0[NB_SM_TO_RECEIVE_BEFORE_AVF0-1];
173 ring_node_tab[NB_SM_TO_RECEIVE_BEFORE_AVF0-1] = ring_node_for_averaging_sm_f0;
172 ring_node_tab[NB_SM_TO_RECEIVE_BEFORE_AVF0-1] = ring_node_for_averaging_sm_f0;
174 for (i=0; i<NB_SM_TO_RECEIVE_BEFORE_AVF0-1; i++)
173 for (i=2; i<NB_SM_TO_RECEIVE_BEFORE_AVF0+1; i++)
175 {
174 {
176 ring_node_for_averaging_sm_f0 = ring_node_for_averaging_sm_f0->previous;
175 ring_node_for_averaging_sm_f0 = ring_node_for_averaging_sm_f0->previous;
177 ring_node_tab[i] = ring_node_for_averaging_sm_f0;
176 ring_node_tab[NB_SM_TO_RECEIVE_BEFORE_AVF0-i] = ring_node_for_averaging_sm_f0;
178 }
177 }
179 for(i=0; i<TOTAL_SIZE_SM; i++)
178 for(i=0; i<TOTAL_SIZE_SM; i++)
180 {
179 {
@@ -509,11 +508,11 void send_spectral_matrix(Header_TM_LFR_
509 switch(sid)
508 switch(sid)
510 {
509 {
511 case SID_NORM_ASM_F0:
510 case SID_NORM_ASM_F0:
512 spw_ioctl_send->dlen = TOTAL_SIZE_ASM_F0 / 2;
511 spw_ioctl_send->dlen = TOTAL_SIZE_ASM_F0_IN_BYTES / 2;
513 spw_ioctl_send->data = &spectral_matrix[ ASM_F0_INDICE_START + i * (TOTAL_SIZE_ASM_F0/2)];
512 spw_ioctl_send->data = &spectral_matrix[ ( (ASM_F0_INDICE_START+ (i*NB_BINS_PER_PKT_ASM_F0)) * NB_VALUES_PER_SM) * 2 ];
514 length = PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0;
513 length = PACKET_LENGTH_TM_LFR_SCIENCE_ASM_F0;
515 header->pa_lfr_asm_blk_nr[0] = (unsigned char) ( (NB_BINS_PER_ASM_F0/2) >> 8 ); // BLK_NR MSB
514 header->pa_lfr_asm_blk_nr[0] = (unsigned char) ( (NB_BINS_PER_PKT_ASM_F0) >> 8 ); // BLK_NR MSB
516 header->pa_lfr_asm_blk_nr[1] = (unsigned char) (NB_BINS_PER_ASM_F0/2); // BLK_NR LSB
515 header->pa_lfr_asm_blk_nr[1] = (unsigned char) (NB_BINS_PER_PKT_ASM_F0); // BLK_NR LSB
517 break;
516 break;
518 case SID_NORM_ASM_F1:
517 case SID_NORM_ASM_F1:
519 break;
518 break;
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