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waveform picker registers updated to be compliant with the new VHDL design
paul -
r52:e2d761f8e287 nov2013
parent child
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@@ -24,8 +24,7 extern volatile int wf_snap_f2_norm[ ];
24 24 extern volatile int wf_cont_f3[ ];
25 25 extern volatile int wf_cont_f3_bis[ ];
26 26 extern char wf_cont_f3_light[ ];
27 extern waveform_picker_regs_t *waveform_picker_regs;
28 extern waveform_picker_regs_t_alt *waveform_picker_regs_alt;
27 extern new_waveform_picker_regs_t *new_waveform_picker_regs;
29 28 extern time_management_regs_t *time_management_regs;
30 29 extern Packet_TM_LFR_HK_t housekeeping_packet;
31 30 extern Packet_TM_LFR_PARAMETER_DUMP_t parameter_dump_packet;
@@ -68,7 +67,7 char set_wfp_delta_snapshot();
68 67 void set_wfp_burst_enable_register( unsigned char mode);
69 68 void reset_wfp_burst_enable();
70 69 void reset_wfp_status();
71 void reset_waveform_picker_regs();
70 void reset_new_waveform_picker_regs();
72 71
73 72 //*****************
74 73 // local parameters
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@@ -36,8 +36,7 time_management_regs_t *time_management_
36 36 gptimer_regs_t *gptimer_regs = (gptimer_regs_t *) REGS_ADDR_GPTIMER;
37 37 #ifdef GSA
38 38 #else
39 waveform_picker_regs_t *waveform_picker_regs = (waveform_picker_regs_t*) REGS_ADDR_WAVEFORM_PICKER;
40 waveform_picker_regs_t_alt *waveform_picker_regs_alt = (waveform_picker_regs_t_alt*) REGS_ADDR_WAVEFORM_PICKER;
39 new_waveform_picker_regs_t *new_waveform_picker_regs = (new_waveform_picker_regs_t*) REGS_ADDR_WAVEFORM_PICKER;
41 40 #endif
42 41 spectral_matrix_regs_t *spectral_matrix_regs = (spectral_matrix_regs_t*) REGS_ADDR_SPECTRAL_MATRIX;
43 42
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@@ -38,19 +38,19 rtems_isr waveforms_isr( rtems_vector_nu
38 38 if ( (lfrCurrentMode == LFR_MODE_NORMAL)
39 39 || (lfrCurrentMode == LFR_MODE_SBM1) || (lfrCurrentMode == LFR_MODE_SBM2) )
40 40 { // in modes other than STANDBY and BURST, send the CWF_F3 data
41 if ((waveform_picker_regs->status & 0x08) == 0x08){ // [1000] f3 is full
41 if ((new_waveform_picker_regs->status & 0x08) == 0x08){ // [1000] f3 is full
42 42 // (1) change the receiving buffer for the waveform picker
43 if (waveform_picker_regs->addr_data_f3 == (int) wf_cont_f3) {
44 waveform_picker_regs->addr_data_f3 = (int) (wf_cont_f3_bis);
43 if (new_waveform_picker_regs->addr_data_f3 == (int) wf_cont_f3) {
44 new_waveform_picker_regs->addr_data_f3 = (int) (wf_cont_f3_bis);
45 45 }
46 46 else {
47 waveform_picker_regs->addr_data_f3 = (int) (wf_cont_f3);
47 new_waveform_picker_regs->addr_data_f3 = (int) (wf_cont_f3);
48 48 }
49 49 // (2) send an event for the waveforms transmission
50 50 if (rtems_event_send( Task_id[TASKID_CWF3], RTEMS_EVENT_0 ) != RTEMS_SUCCESSFUL) {
51 51 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
52 52 }
53 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffff777; // reset f3 bits to 0, [1111 0111 0111 0111]
53 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffff777; // reset f3 bits to 0, [1111 0111 0111 0111]
54 54 }
55 55 }
56 56 #endif
@@ -68,18 +68,18 rtems_isr waveforms_isr( rtems_vector_nu
68 68 #ifdef GSA
69 69 PRINTF("in waveform_isr *** unexpected waveform picker interruption\n")
70 70 #else
71 if ( (waveform_picker_regs->burst_enable & 0x7) == 0x0 ){ // if no channel is enable
71 if ( (new_waveform_picker_regs->run_burst_enable & 0x7) == 0x0 ){ // if no channel is enable
72 72 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
73 73 }
74 74 else {
75 if ( (waveform_picker_regs->status & 0x7) == 0x7 ){ // f2 f1 and f0 are full
76 waveform_picker_regs->burst_enable = waveform_picker_regs->burst_enable & 0x08;
75 if ( (new_waveform_picker_regs->status & 0x7) == 0x7 ){ // f2 f1 and f0 are full
76 new_waveform_picker_regs->run_burst_enable = new_waveform_picker_regs->run_burst_enable & 0x08;
77 77 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_NORMAL ) != RTEMS_SUCCESSFUL) {
78 78 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
79 79 }
80 // waveform_picker_regs->status = waveform_picker_regs->status & 0x00;
81 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffff888;
82 waveform_picker_regs->burst_enable = waveform_picker_regs->burst_enable | 0x07; // [0111] enable f2 f1 f0
80 // new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0x00;
81 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffff888;
82 new_waveform_picker_regs->run_burst_enable = new_waveform_picker_regs->run_burst_enable | 0x07; // [0111] enable f2 f1 f0
83 83 }
84 84 }
85 85 #endif
@@ -91,19 +91,19 rtems_isr waveforms_isr( rtems_vector_nu
91 91 #ifdef GSA
92 92 PRINTF("in waveform_isr *** unexpected waveform picker interruption\n")
93 93 #else
94 if ((waveform_picker_regs->status & 0x04) == 0x04){ // [0100] check the f2 full bit
94 if ((new_waveform_picker_regs->status & 0x04) == 0x04){ // [0100] check the f2 full bit
95 95 // (1) change the receiving buffer for the waveform picker
96 if (waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
97 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2_bis);
96 if (new_waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
97 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2_bis);
98 98 }
99 99 else {
100 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2);
100 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2);
101 101 }
102 102 // (2) send an event for the waveforms transmission
103 103 if (rtems_event_send( Task_id[TASKID_CWF2], RTEMS_EVENT_MODE_BURST ) != RTEMS_SUCCESSFUL) {
104 104 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
105 105 }
106 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffbbb; // [1111 1011 1011 1011] f2 bits = 0
106 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffbbb; // [1111 1011 1011 1011] f2 bits = 0
107 107 }
108 108 #endif
109 109 break;
@@ -114,34 +114,34 rtems_isr waveforms_isr( rtems_vector_nu
114 114 #ifdef GSA
115 115 PRINTF("in waveform_isr *** unexpected waveform picker interruption\n")
116 116 #else
117 if ((waveform_picker_regs->status & 0x02) == 0x02){ // [0010] check the f1 full bit
117 if ((new_waveform_picker_regs->status & 0x02) == 0x02){ // [0010] check the f1 full bit
118 118 // (1) change the receiving buffer for the waveform picker
119 119 if ( param_local.local_sbm1_nb_cwf_sent == (param_local.local_sbm1_nb_cwf_max-1) )
120 120 {
121 waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1_norm);
121 new_waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1_norm);
122 122 }
123 else if ( waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1_norm )
123 else if ( new_waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1_norm )
124 124 {
125 125 doubleSendCWF1 = 1;
126 waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1);
126 new_waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1);
127 127 }
128 else if ( waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1 ) {
129 waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1_bis);
128 else if ( new_waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1 ) {
129 new_waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1_bis);
130 130 }
131 131 else {
132 waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1);
132 new_waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1);
133 133 }
134 134 // (2) send an event for the waveforms transmission
135 135 if (rtems_event_send( Task_id[TASKID_CWF1], RTEMS_EVENT_MODE_SBM1 ) != RTEMS_SUCCESSFUL) {
136 136 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
137 137 }
138 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffddd; // [1111 1101 1101 1101] f1 bit = 0
138 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffddd; // [1111 1101 1101 1101] f1 bit = 0
139 139 }
140 if ( ( (waveform_picker_regs->status & 0x05) == 0x05 ) ) { // [0101] check the f2 and f0 full bit
140 if ( ( (new_waveform_picker_regs->status & 0x05) == 0x05 ) ) { // [0101] check the f2 and f0 full bit
141 141 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_NORMAL ) != RTEMS_SUCCESSFUL) {
142 142 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
143 143 }
144 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffaaa; // [1111 1010 1010 1010] f2 and f0 bits = 0
144 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffaaa; // [1111 1010 1010 1010] f2 and f0 bits = 0
145 145 reset_local_sbm1_nb_cwf_sent();
146 146 }
147 147
@@ -154,37 +154,37 rtems_isr waveforms_isr( rtems_vector_nu
154 154 #ifdef GSA
155 155 PRINTF("in waveform_isr *** unexpected waveform picker interruption\n")
156 156 #else
157 if ((waveform_picker_regs->status & 0x04) == 0x04){ // [0100] check the f2 full bit
157 if ((new_waveform_picker_regs->status & 0x04) == 0x04){ // [0100] check the f2 full bit
158 158 // (1) change the receiving buffer for the waveform picker
159 159 if ( param_local.local_sbm2_nb_cwf_sent == (param_local.local_sbm2_nb_cwf_max-1) )
160 160 {
161 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2_norm);
161 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2_norm);
162 162 }
163 else if ( waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2_norm ) {
164 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2);
163 else if ( new_waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2_norm ) {
164 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2);
165 165 doubleSendCWF2 = 1;
166 166 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_SBM2_WFRM ) != RTEMS_SUCCESSFUL) {
167 167 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
168 168 }
169 169 reset_local_sbm2_nb_cwf_sent();
170 170 }
171 else if ( waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2 ) {
172 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2_bis);
171 else if ( new_waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2 ) {
172 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2_bis);
173 173 }
174 174 else {
175 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2);
175 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2);
176 176 }
177 177 // (2) send an event for the waveforms transmission
178 178 if (rtems_event_send( Task_id[TASKID_CWF2], RTEMS_EVENT_MODE_SBM2 ) != RTEMS_SUCCESSFUL) {
179 179 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
180 180 }
181 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffbbb; // [1111 1011 1011 1011] f2 bit = 0
181 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffbbb; // [1111 1011 1011 1011] f2 bit = 0
182 182 }
183 if ( ( (waveform_picker_regs->status & 0x03) == 0x03 ) ) { // [0011] f3 f2 f1 f0, f1 and f0 are full
183 if ( ( (new_waveform_picker_regs->status & 0x03) == 0x03 ) ) { // [0011] f3 f2 f1 f0, f1 and f0 are full
184 184 if (rtems_event_send( Task_id[TASKID_WFRM], RTEMS_EVENT_MODE_SBM2 ) != RTEMS_SUCCESSFUL) {
185 185 rtems_event_send( Task_id[TASKID_DUMB], RTEMS_EVENT_2 );
186 186 }
187 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffccc; // [1111 1100 1100 1100] f1, f0 bits = 0
187 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffccc; // [1111 1100 1100 1100] f1, f0 bits = 0
188 188 }
189 189 #endif
190 190 break;
@@ -262,7 +262,7 rtems_task wfrm_task(rtems_task_argument
262 262 send_waveform_SWF(wf_snap_f1, SID_NORM_SWF_F1, headerSWF_F1, queue_id);
263 263 send_waveform_SWF(wf_snap_f2, SID_NORM_SWF_F2, headerSWF_F2, queue_id);
264 264 #ifdef GSA
265 waveform_picker_regs->status = waveform_picker_regs->status & 0xf888; // [1111 1000 1000 1000] f2, f1, f0 bits =0
265 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xf888; // [1111 1000 1000 1000] f2, f1, f0 bits =0
266 266 #endif
267 267 }
268 268 else if (event_out == RTEMS_EVENT_MODE_SBM1)
@@ -271,7 +271,7 rtems_task wfrm_task(rtems_task_argument
271 271 send_waveform_SWF(wf_snap_f1_norm, SID_NORM_SWF_F1, headerSWF_F1, queue_id);
272 272 send_waveform_SWF(wf_snap_f2, SID_NORM_SWF_F2, headerSWF_F2, queue_id);
273 273 #ifdef GSA
274 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffaaa; // [1111 1010 1010 1010] f2, f0 bits = 0
274 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffaaa; // [1111 1010 1010 1010] f2, f0 bits = 0
275 275 #endif
276 276 }
277 277 else if (event_out == RTEMS_EVENT_MODE_SBM2)
@@ -279,7 +279,7 rtems_task wfrm_task(rtems_task_argument
279 279 send_waveform_SWF(wf_snap_f0, SID_NORM_SWF_F0, headerSWF_F0, queue_id);
280 280 send_waveform_SWF(wf_snap_f1, SID_NORM_SWF_F1, headerSWF_F1, queue_id);
281 281 #ifdef GSA
282 waveform_picker_regs->status = waveform_picker_regs->status & 0xfffffccc; // [1111 1100 1100 1100] f1, f0 bits = 0
282 new_waveform_picker_regs->status = new_waveform_picker_regs->status & 0xfffffccc; // [1111 1100 1100 1100] f1, f0 bits = 0
283 283 #endif
284 284 }
285 285 else if (event_out == RTEMS_EVENT_MODE_SBM2_WFRM)
@@ -329,7 +329,7 rtems_task cwf3_task(rtems_task_argument
329 329 PRINTF("send CWF F3 \n")
330 330 #ifdef GSA
331 331 #else
332 if (waveform_picker_regs->addr_data_f3 == (int) wf_cont_f3) {
332 if (new_waveform_picker_regs->addr_data_f3 == (int) wf_cont_f3) {
333 333 send_waveform_CWF3_light( wf_cont_f3_bis, headerCWF_F3_light, queue_id );
334 334 }
335 335 else {
@@ -371,7 +371,7 rtems_task cwf2_task(rtems_task_argument
371 371 // F2
372 372 #ifdef GSA
373 373 #else
374 if (waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
374 if (new_waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
375 375 send_waveform_CWF( wf_snap_f2_bis, SID_BURST_CWF_F2, headerCWF_F2_BURST, queue_id );
376 376 }
377 377 else {
@@ -389,7 +389,7 rtems_task cwf2_task(rtems_task_argument
389 389 doubleSendCWF2 = 0;
390 390 send_waveform_CWF( wf_snap_f2_norm, SID_SBM2_CWF_F2, headerCWF_F2_SBM2, queue_id );
391 391 }
392 else if (waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
392 else if (new_waveform_picker_regs->addr_data_f2 == (int) wf_snap_f2) {
393 393 send_waveform_CWF( wf_snap_f2_bis, SID_SBM2_CWF_F2, headerCWF_F2_SBM2, queue_id );
394 394 }
395 395 else {
@@ -438,7 +438,7 rtems_task cwf1_task(rtems_task_argument
438 438 doubleSendCWF1 = 0;
439 439 send_waveform_CWF( wf_snap_f1_norm, SID_SBM1_CWF_F1, headerCWF_F1, queue_id );
440 440 }
441 else if (waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1) {
441 else if (new_waveform_picker_regs->addr_data_f1 == (int) wf_snap_f1) {
442 442 send_waveform_CWF( wf_snap_f1_bis, SID_SBM1_CWF_F1, headerCWF_F1, queue_id );
443 443 }
444 444 else {
@@ -935,7 +935,7 void set_wfp_data_shaping()
935 935
936 936 #ifdef GSA
937 937 #else
938 waveform_picker_regs->data_shaping =
938 new_waveform_picker_regs->data_shaping =
939 939 ( (data_shaping & 0x10) >> 4 ) // BW
940 940 + ( (data_shaping & 0x08) >> 2 ) // SP0
941 941 + ( (data_shaping & 0x04) ) // SP1
@@ -976,7 +976,7 char set_wfp_delta_snapshot()
976 976 aux = delta_snapshot ;
977 977 ret = LFR_SUCCESSFUL;
978 978 }
979 waveform_picker_regs->delta_snapshot = aux - 1; // max 2 bytes
979 new_waveform_picker_regs->delta_snapshot = aux - 1; // max 2 bytes
980 980 #endif
981 981
982 982 return ret;
@@ -998,23 +998,23 void set_wfp_burst_enable_register( unsi
998 998 // the burst bits shall be set first, before the enable bits
999 999 switch(mode) {
1000 1000 case(LFR_MODE_NORMAL):
1001 waveform_picker_regs->burst_enable = 0x00; // [0000 0000] no burst enable
1002 waveform_picker_regs->burst_enable = 0x0f; // [0000 1111] enable f3 f2 f1 f0
1001 new_waveform_picker_regs->run_burst_enable = 0x00; // [0000 0000] no burst enable
1002 new_waveform_picker_regs->run_burst_enable = 0x0f; // [0000 1111] enable f3 f2 f1 f0
1003 1003 break;
1004 1004 case(LFR_MODE_BURST):
1005 waveform_picker_regs->burst_enable = 0x40; // [0100 0000] f2 burst enabled
1006 waveform_picker_regs->burst_enable = waveform_picker_regs->burst_enable | 0x04; // [0100] enable f2
1005 new_waveform_picker_regs->run_burst_enable = 0x40; // [0100 0000] f2 burst enabled
1006 new_waveform_picker_regs->run_burst_enable = new_waveform_picker_regs->run_burst_enable | 0x04; // [0100] enable f2
1007 1007 break;
1008 1008 case(LFR_MODE_SBM1):
1009 waveform_picker_regs->burst_enable = 0x20; // [0010 0000] f1 burst enabled
1010 waveform_picker_regs->burst_enable = waveform_picker_regs->burst_enable | 0x0f; // [1111] enable f3 f2 f1 f0
1009 new_waveform_picker_regs->run_burst_enable = 0x20; // [0010 0000] f1 burst enabled
1010 new_waveform_picker_regs->run_burst_enable = new_waveform_picker_regs->run_burst_enable | 0x0f; // [1111] enable f3 f2 f1 f0
1011 1011 break;
1012 1012 case(LFR_MODE_SBM2):
1013 waveform_picker_regs->burst_enable = 0x40; // [0100 0000] f2 burst enabled
1014 waveform_picker_regs->burst_enable = waveform_picker_regs->burst_enable | 0x0f; // [1111] enable f3 f2 f1 f0
1013 new_waveform_picker_regs->run_burst_enable = 0x40; // [0100 0000] f2 burst enabled
1014 new_waveform_picker_regs->run_burst_enable = new_waveform_picker_regs->run_burst_enable | 0x0f; // [1111] enable f3 f2 f1 f0
1015 1015 break;
1016 1016 default:
1017 waveform_picker_regs->burst_enable = 0x00; // [0000 0000] no burst enabled, no waveform enabled
1017 new_waveform_picker_regs->run_burst_enable = 0x00; // [0000 0000] no burst enabled, no waveform enabled
1018 1018 break;
1019 1019 }
1020 1020 #endif
@@ -1030,7 +1030,7 void reset_wfp_burst_enable()
1030 1030
1031 1031 #ifdef GSA
1032 1032 #else
1033 waveform_picker_regs->burst_enable = 0x00; // burst f2, f1, f0 enable f3, f2, f1, f0
1033 new_waveform_picker_regs->run_burst_enable = 0x00; // burst f2, f1, f0 enable f3, f2, f1, f0
1034 1034 #endif
1035 1035 }
1036 1036
@@ -1044,66 +1044,27 void reset_wfp_status()
1044 1044
1045 1045 #ifdef GSA
1046 1046 #else
1047 waveform_picker_regs->status = 0x00; // burst f2, f1, f0 enable f3, f2, f1, f0
1047 new_waveform_picker_regs->status = 0x00; // burst f2, f1, f0 enable f3, f2, f1, f0
1048 1048 #endif
1049 1049 }
1050 1050
1051 void reset_waveform_picker_regs()
1051 void reset_new_waveform_picker_regs()
1052 1052 {
1053 /** This function resets the waveform picker module registers.
1054 *
1055 * The registers affected by this function are located at the following offset addresses:
1056 * - 0x00 data_shaping
1057 * - 0x04 burst_enable
1058 * - 0x08 addr_data_f0
1059 * - 0x0C addr_data_f1
1060 * - 0x10 addr_data_f2
1061 * - 0x14 addr_data_f3
1062 * - 0x18 status
1063 * - 0x1C delta_snapshot
1064 * - 0x20 delta_f2_f1
1065 * - 0x24 delta_f2_f0
1066 * - 0x28 nb_burst
1067 * - 0x2C nb_snapshot
1068 *
1069 */
1070
1071 #ifdef GSA
1072 #else
1073 reset_wfp_burst_enable();
1074 reset_wfp_status();
1075 // set buffer addresses
1076 waveform_picker_regs->addr_data_f0 = (int) (wf_snap_f0); //
1077 waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1); //
1078 waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2); //
1079 waveform_picker_regs->addr_data_f3 = (int) (wf_cont_f3); //
1080 // set other parameters
1081 set_wfp_data_shaping();
1082 set_wfp_delta_snapshot(); // time in seconds between two snapshots
1083 waveform_picker_regs->delta_f2_f1 = 0xffff; // 0x16800 => 92160 (max 4 bytes)
1084 waveform_picker_regs->delta_f2_f0 = 0x17c00; // 97 280 (max 5 bytes)
1085 waveform_picker_regs->nb_burst_available = 0x180; // max 3 bytes, size of the buffer in burst (1 burst = 16 x 4 octets)
1086 waveform_picker_regs->nb_snapshot_param = 0x7ff; // max 3 octets, 2048 - 1
1087 #endif
1088 }
1089
1090 void reset_waveform_picker_regs_alt()
1091 {
1092 waveform_picker_regs_alt->data_shaping = 0x01; // 0x00 00 *** R1 R0 SP1 SP0 BW
1093 waveform_picker_regs_alt->run_burst_enable = 0x00; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
1094 waveform_picker_regs_alt->addr_data_f0 = (int) (wf_snap_f0); // 0x08
1095 waveform_picker_regs_alt->addr_data_f1 = (int) (wf_snap_f1); // 0x0c
1096 waveform_picker_regs_alt->addr_data_f2 = (int) (wf_snap_f2); // 0x10
1097 waveform_picker_regs_alt->addr_data_f3 = (int) (wf_cont_f3); // 0x14
1098 waveform_picker_regs_alt->status = 0x00; // 0x18
1099 waveform_picker_regs_alt->delta_snapshot = 0x12800; // 0x1c
1100 waveform_picker_regs_alt->delta_f0 = 0x3f5; // 0x20 *** 1013
1101 waveform_picker_regs_alt->delta_f0_2 = 0x7; // 0x24 *** 7
1102 waveform_picker_regs_alt->delta_f1 = 0x3c0; // 0x28 *** 960
1103 waveform_picker_regs_alt->delta_f2 = 0x12200; // 0x2c *** 74240
1104 waveform_picker_regs_alt->nb_data_by_buffer = 0x1802; // 0x30 *** 2048 * 3 + 2
1105 waveform_picker_regs_alt->snapshot_param = 0x7ff; // 0x34 *** 2048 -1
1106 waveform_picker_regs_alt->start_date = 0x00;
1053 new_waveform_picker_regs->data_shaping = 0x01; // 0x00 00 *** R1 R0 SP1 SP0 BW
1054 new_waveform_picker_regs->run_burst_enable = 0x00; // 0x04 01 *** [run *** burst f2, f1, f0 *** enable f3, f2, f1, f0 ]
1055 new_waveform_picker_regs->addr_data_f0 = (int) (wf_snap_f0); // 0x08
1056 new_waveform_picker_regs->addr_data_f1 = (int) (wf_snap_f1); // 0x0c
1057 new_waveform_picker_regs->addr_data_f2 = (int) (wf_snap_f2); // 0x10
1058 new_waveform_picker_regs->addr_data_f3 = (int) (wf_cont_f3); // 0x14
1059 new_waveform_picker_regs->status = 0x00; // 0x18
1060 new_waveform_picker_regs->delta_snapshot = 0x12800; // 0x1c
1061 new_waveform_picker_regs->delta_f0 = 0x3f5; // 0x20 *** 1013
1062 new_waveform_picker_regs->delta_f0_2 = 0x7; // 0x24 *** 7
1063 new_waveform_picker_regs->delta_f1 = 0x3c0; // 0x28 *** 960
1064 new_waveform_picker_regs->delta_f2 = 0x12200; // 0x2c *** 74240
1065 new_waveform_picker_regs->nb_data_by_buffer = 0x1802; // 0x30 *** 2048 * 3 + 2
1066 new_waveform_picker_regs->snapshot_param = 0x7ff; // 0x34 *** 2048 -1
1067 new_waveform_picker_regs->start_date = 0x00;
1107 1068 }
1108 1069
1109 1070 //*****************
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